2014-05-11 04:13:51 +02:00
|
|
|
{
|
|
|
|
|
"name": null,
|
|
|
|
|
"sim_quantum": 0,
|
|
|
|
|
"system": {
|
2014-09-21 22:15:14 +02:00
|
|
|
"kernel": "",
|
2014-05-11 04:13:51 +02:00
|
|
|
"l2c": {
|
2014-09-21 22:15:14 +02:00
|
|
|
"is_top_level": false,
|
|
|
|
|
"prefetcher": null,
|
|
|
|
|
"clk_domain": "system.cpu_clk_domain",
|
|
|
|
|
"write_buffers": 8,
|
|
|
|
|
"response_latency": 20,
|
|
|
|
|
"cxx_class": "BaseCache",
|
|
|
|
|
"size": 4194304,
|
2014-05-11 04:13:51 +02:00
|
|
|
"tags": {
|
|
|
|
|
"name": "tags",
|
|
|
|
|
"eventq_index": 0,
|
|
|
|
|
"hit_latency": 20,
|
2014-09-21 22:15:14 +02:00
|
|
|
"clk_domain": "system.cpu_clk_domain",
|
2014-05-11 04:13:51 +02:00
|
|
|
"sequential_access": false,
|
|
|
|
|
"assoc": 8,
|
|
|
|
|
"cxx_class": "LRU",
|
|
|
|
|
"path": "system.l2c.tags",
|
|
|
|
|
"block_size": 64,
|
|
|
|
|
"type": "LRU",
|
|
|
|
|
"size": 4194304
|
|
|
|
|
},
|
2014-09-21 22:15:14 +02:00
|
|
|
"system": "system",
|
2014-05-11 04:13:51 +02:00
|
|
|
"max_miss_count": 0,
|
|
|
|
|
"eventq_index": 0,
|
2014-09-21 22:15:14 +02:00
|
|
|
"mem_side": {
|
|
|
|
|
"peer": "system.membus.slave[1]",
|
|
|
|
|
"role": "MASTER"
|
|
|
|
|
},
|
|
|
|
|
"mshrs": 20,
|
|
|
|
|
"forward_snoops": true,
|
|
|
|
|
"hit_latency": 20,
|
|
|
|
|
"tgts_per_mshr": 12,
|
|
|
|
|
"addr_ranges": [
|
|
|
|
|
"0:18446744073709551615"
|
|
|
|
|
],
|
|
|
|
|
"assoc": 8,
|
2014-05-11 04:13:51 +02:00
|
|
|
"prefetch_on_access": false,
|
|
|
|
|
"path": "system.l2c",
|
2014-09-21 22:15:14 +02:00
|
|
|
"name": "l2c",
|
2014-05-11 04:13:51 +02:00
|
|
|
"type": "BaseCache",
|
2014-09-21 22:15:14 +02:00
|
|
|
"sequential_access": false,
|
|
|
|
|
"cpu_side": {
|
|
|
|
|
"peer": "system.toL2Bus.master[0]",
|
|
|
|
|
"role": "SLAVE"
|
|
|
|
|
},
|
|
|
|
|
"two_queue": false
|
2014-05-11 04:13:51 +02:00
|
|
|
},
|
2014-09-01 23:55:52 +02:00
|
|
|
"kernel_addr_check": true,
|
2014-09-21 22:15:14 +02:00
|
|
|
"membus": {
|
|
|
|
|
"slave": {
|
|
|
|
|
"peer": [
|
|
|
|
|
"system.system_port",
|
|
|
|
|
"system.l2c.mem_side"
|
|
|
|
|
],
|
2014-05-11 04:13:51 +02:00
|
|
|
"role": "SLAVE"
|
|
|
|
|
},
|
2014-09-21 22:15:14 +02:00
|
|
|
"name": "membus",
|
|
|
|
|
"snoop_filter": null,
|
|
|
|
|
"clk_domain": "system.clk_domain",
|
|
|
|
|
"header_cycles": 1,
|
|
|
|
|
"system": "system",
|
|
|
|
|
"width": 8,
|
|
|
|
|
"eventq_index": 0,
|
|
|
|
|
"master": {
|
|
|
|
|
"peer": [
|
|
|
|
|
"system.physmem.port"
|
|
|
|
|
],
|
|
|
|
|
"role": "MASTER"
|
|
|
|
|
},
|
|
|
|
|
"cxx_class": "CoherentXBar",
|
|
|
|
|
"path": "system.membus",
|
|
|
|
|
"type": "CoherentXBar",
|
|
|
|
|
"use_default_range": false
|
2014-05-11 04:13:51 +02:00
|
|
|
},
|
2014-09-21 22:15:14 +02:00
|
|
|
"symbolfile": "",
|
|
|
|
|
"readfile": "",
|
2014-05-11 04:13:51 +02:00
|
|
|
"cxx_class": "System",
|
|
|
|
|
"load_offset": 0,
|
|
|
|
|
"work_end_ckpt_count": 0,
|
2014-09-21 22:15:14 +02:00
|
|
|
"memories": [
|
|
|
|
|
"system.physmem"
|
|
|
|
|
],
|
2014-05-11 04:13:51 +02:00
|
|
|
"work_begin_ckpt_count": 0,
|
|
|
|
|
"clk_domain": {
|
|
|
|
|
"name": "clk_domain",
|
2014-09-21 22:15:14 +02:00
|
|
|
"clock": [
|
|
|
|
|
1000
|
|
|
|
|
],
|
2014-09-01 23:55:52 +02:00
|
|
|
"init_perf_level": 0,
|
2014-09-21 22:15:14 +02:00
|
|
|
"voltage_domain": "system.voltage_domain",
|
2014-05-11 04:13:51 +02:00
|
|
|
"eventq_index": 0,
|
|
|
|
|
"cxx_class": "SrcClockDomain",
|
|
|
|
|
"path": "system.clk_domain",
|
2014-09-01 23:55:52 +02:00
|
|
|
"type": "SrcClockDomain",
|
|
|
|
|
"domain_id": -1
|
2014-05-11 04:13:51 +02:00
|
|
|
},
|
2014-09-21 22:15:14 +02:00
|
|
|
"mem_ranges": [],
|
2014-05-11 04:13:51 +02:00
|
|
|
"eventq_index": 0,
|
2014-09-01 23:55:52 +02:00
|
|
|
"dvfs_handler": {
|
|
|
|
|
"enable": false,
|
|
|
|
|
"name": "dvfs_handler",
|
2014-09-21 22:15:14 +02:00
|
|
|
"sys_clk_domain": "system.clk_domain",
|
|
|
|
|
"transition_latency": 100000000,
|
2014-09-01 23:55:52 +02:00
|
|
|
"eventq_index": 0,
|
|
|
|
|
"cxx_class": "DVFSHandler",
|
2014-09-21 22:15:14 +02:00
|
|
|
"domains": [],
|
2014-09-01 23:55:52 +02:00
|
|
|
"path": "system.dvfs_handler",
|
|
|
|
|
"type": "DVFSHandler"
|
|
|
|
|
},
|
|
|
|
|
"work_end_exit_count": 0,
|
|
|
|
|
"type": "System",
|
|
|
|
|
"voltage_domain": {
|
2014-09-21 22:15:14 +02:00
|
|
|
"name": "voltage_domain",
|
2014-09-01 23:55:52 +02:00
|
|
|
"eventq_index": 0,
|
2014-09-21 22:15:14 +02:00
|
|
|
"voltage": [
|
|
|
|
|
"1.0"
|
|
|
|
|
],
|
|
|
|
|
"cxx_class": "VoltageDomain",
|
2014-09-01 23:55:52 +02:00
|
|
|
"path": "system.voltage_domain",
|
2014-09-21 22:15:14 +02:00
|
|
|
"type": "VoltageDomain"
|
2014-09-01 23:55:52 +02:00
|
|
|
},
|
|
|
|
|
"cache_line_size": 64,
|
2014-09-21 22:15:14 +02:00
|
|
|
"boot_osflags": "a",
|
|
|
|
|
"physmem": {
|
|
|
|
|
"range": "0:134217727",
|
|
|
|
|
"latency": 30000,
|
|
|
|
|
"name": "physmem",
|
|
|
|
|
"eventq_index": 0,
|
|
|
|
|
"clk_domain": "system.clk_domain",
|
|
|
|
|
"latency_var": 0,
|
|
|
|
|
"bandwidth": "73.000000",
|
|
|
|
|
"conf_table_reported": true,
|
|
|
|
|
"cxx_class": "SimpleMemory",
|
|
|
|
|
"path": "system.physmem",
|
|
|
|
|
"null": false,
|
|
|
|
|
"type": "SimpleMemory",
|
|
|
|
|
"port": {
|
|
|
|
|
"peer": "system.membus.master[0]",
|
|
|
|
|
"role": "SLAVE"
|
|
|
|
|
},
|
|
|
|
|
"in_addr_map": true
|
|
|
|
|
},
|
2014-09-01 23:55:52 +02:00
|
|
|
"work_cpus_ckpt_count": 0,
|
|
|
|
|
"work_begin_exit_count": 0,
|
|
|
|
|
"path": "system",
|
|
|
|
|
"cpu_clk_domain": {
|
|
|
|
|
"name": "cpu_clk_domain",
|
2014-09-21 22:15:14 +02:00
|
|
|
"clock": [
|
|
|
|
|
500
|
|
|
|
|
],
|
2014-09-01 23:55:52 +02:00
|
|
|
"init_perf_level": 0,
|
2014-09-21 22:15:14 +02:00
|
|
|
"voltage_domain": "system.voltage_domain",
|
2014-09-01 23:55:52 +02:00
|
|
|
"eventq_index": 0,
|
|
|
|
|
"cxx_class": "SrcClockDomain",
|
|
|
|
|
"path": "system.cpu_clk_domain",
|
|
|
|
|
"type": "SrcClockDomain",
|
|
|
|
|
"domain_id": -1
|
|
|
|
|
},
|
2014-05-11 04:13:51 +02:00
|
|
|
"toL2Bus": {
|
|
|
|
|
"slave": {
|
|
|
|
|
"peer": [
|
|
|
|
|
"system.cpu0.icache.mem_side",
|
|
|
|
|
"system.cpu0.dcache.mem_side",
|
|
|
|
|
"system.cpu1.icache.mem_side",
|
|
|
|
|
"system.cpu1.dcache.mem_side",
|
|
|
|
|
"system.cpu2.icache.mem_side",
|
|
|
|
|
"system.cpu2.dcache.mem_side",
|
|
|
|
|
"system.cpu3.icache.mem_side",
|
|
|
|
|
"system.cpu3.dcache.mem_side"
|
|
|
|
|
],
|
|
|
|
|
"role": "SLAVE"
|
|
|
|
|
},
|
|
|
|
|
"name": "toL2Bus",
|
2014-09-21 22:15:14 +02:00
|
|
|
"snoop_filter": null,
|
|
|
|
|
"clk_domain": "system.cpu_clk_domain",
|
2014-05-11 04:13:51 +02:00
|
|
|
"header_cycles": 1,
|
2014-09-21 22:15:14 +02:00
|
|
|
"system": "system",
|
2014-05-11 04:13:51 +02:00
|
|
|
"width": 8,
|
|
|
|
|
"eventq_index": 0,
|
|
|
|
|
"master": {
|
|
|
|
|
"peer": [
|
|
|
|
|
"system.l2c.cpu_side"
|
|
|
|
|
],
|
|
|
|
|
"role": "MASTER"
|
|
|
|
|
},
|
2014-09-21 22:15:14 +02:00
|
|
|
"cxx_class": "CoherentXBar",
|
2014-05-11 04:13:51 +02:00
|
|
|
"path": "system.toL2Bus",
|
2014-09-21 22:15:14 +02:00
|
|
|
"type": "CoherentXBar",
|
2014-05-11 04:13:51 +02:00
|
|
|
"use_default_range": false
|
|
|
|
|
},
|
|
|
|
|
"mem_mode": "atomic",
|
|
|
|
|
"name": "system",
|
|
|
|
|
"init_param": 0,
|
|
|
|
|
"system_port": {
|
|
|
|
|
"peer": "system.membus.slave[0]",
|
|
|
|
|
"role": "MASTER"
|
|
|
|
|
},
|
|
|
|
|
"load_addr_mask": 1099511627775,
|
|
|
|
|
"cpu": [
|
|
|
|
|
{
|
|
|
|
|
"do_statistics_insts": true,
|
|
|
|
|
"numThreads": 1,
|
|
|
|
|
"itb": {
|
|
|
|
|
"name": "itb",
|
|
|
|
|
"eventq_index": 0,
|
|
|
|
|
"cxx_class": "AlphaISA::TLB",
|
|
|
|
|
"path": "system.cpu0.itb",
|
|
|
|
|
"type": "AlphaTLB",
|
|
|
|
|
"size": 48
|
|
|
|
|
},
|
2014-09-21 22:15:14 +02:00
|
|
|
"simulate_data_stalls": false,
|
2014-05-11 04:13:51 +02:00
|
|
|
"function_trace": false,
|
|
|
|
|
"do_checkpoint_insts": true,
|
|
|
|
|
"cxx_class": "AtomicSimpleCPU",
|
|
|
|
|
"max_loads_all_threads": 0,
|
2014-09-21 22:15:14 +02:00
|
|
|
"system": "system",
|
|
|
|
|
"clk_domain": "system.cpu_clk_domain",
|
2014-05-11 04:13:51 +02:00
|
|
|
"function_trace_start": 0,
|
|
|
|
|
"cpu_id": 0,
|
|
|
|
|
"width": 1,
|
2014-09-21 22:15:14 +02:00
|
|
|
"checker": null,
|
2014-05-11 04:13:51 +02:00
|
|
|
"eventq_index": 0,
|
|
|
|
|
"do_quiesce": true,
|
|
|
|
|
"type": "AtomicSimpleCPU",
|
|
|
|
|
"fastmem": false,
|
2014-09-21 22:15:14 +02:00
|
|
|
"profile": 0,
|
2014-05-11 04:13:51 +02:00
|
|
|
"icache_port": {
|
|
|
|
|
"peer": "system.cpu0.icache.cpu_side",
|
|
|
|
|
"role": "MASTER"
|
|
|
|
|
},
|
|
|
|
|
"icache": {
|
2014-09-21 22:15:14 +02:00
|
|
|
"is_top_level": true,
|
|
|
|
|
"prefetcher": null,
|
|
|
|
|
"clk_domain": "system.cpu_clk_domain",
|
|
|
|
|
"write_buffers": 8,
|
|
|
|
|
"response_latency": 2,
|
|
|
|
|
"cxx_class": "BaseCache",
|
|
|
|
|
"size": 32768,
|
2014-05-11 04:13:51 +02:00
|
|
|
"tags": {
|
|
|
|
|
"name": "tags",
|
|
|
|
|
"eventq_index": 0,
|
|
|
|
|
"hit_latency": 2,
|
2014-09-21 22:15:14 +02:00
|
|
|
"clk_domain": "system.cpu_clk_domain",
|
2014-05-11 04:13:51 +02:00
|
|
|
"sequential_access": false,
|
|
|
|
|
"assoc": 1,
|
|
|
|
|
"cxx_class": "LRU",
|
|
|
|
|
"path": "system.cpu0.icache.tags",
|
|
|
|
|
"block_size": 64,
|
|
|
|
|
"type": "LRU",
|
|
|
|
|
"size": 32768
|
|
|
|
|
},
|
2014-09-21 22:15:14 +02:00
|
|
|
"system": "system",
|
2014-05-11 04:13:51 +02:00
|
|
|
"max_miss_count": 0,
|
|
|
|
|
"eventq_index": 0,
|
2014-09-21 22:15:14 +02:00
|
|
|
"mem_side": {
|
|
|
|
|
"peer": "system.toL2Bus.slave[0]",
|
|
|
|
|
"role": "MASTER"
|
|
|
|
|
},
|
|
|
|
|
"mshrs": 4,
|
|
|
|
|
"forward_snoops": true,
|
|
|
|
|
"hit_latency": 2,
|
|
|
|
|
"tgts_per_mshr": 20,
|
|
|
|
|
"addr_ranges": [
|
|
|
|
|
"0:18446744073709551615"
|
|
|
|
|
],
|
|
|
|
|
"assoc": 1,
|
2014-05-11 04:13:51 +02:00
|
|
|
"prefetch_on_access": false,
|
|
|
|
|
"path": "system.cpu0.icache",
|
2014-09-21 22:15:14 +02:00
|
|
|
"name": "icache",
|
2014-05-11 04:13:51 +02:00
|
|
|
"type": "BaseCache",
|
2014-09-21 22:15:14 +02:00
|
|
|
"sequential_access": false,
|
|
|
|
|
"cpu_side": {
|
|
|
|
|
"peer": "system.cpu0.icache_port",
|
|
|
|
|
"role": "SLAVE"
|
|
|
|
|
},
|
|
|
|
|
"two_queue": false
|
2014-05-11 04:13:51 +02:00
|
|
|
},
|
|
|
|
|
"interrupts": {
|
|
|
|
|
"eventq_index": 0,
|
|
|
|
|
"path": "system.cpu0.interrupts",
|
|
|
|
|
"type": "AlphaInterrupts",
|
|
|
|
|
"name": "interrupts",
|
|
|
|
|
"cxx_class": "AlphaISA::Interrupts"
|
|
|
|
|
},
|
2014-09-21 22:15:14 +02:00
|
|
|
"dcache_port": {
|
|
|
|
|
"peer": "system.cpu0.dcache.cpu_side",
|
|
|
|
|
"role": "MASTER"
|
|
|
|
|
},
|
2014-05-11 04:13:51 +02:00
|
|
|
"socket_id": 0,
|
|
|
|
|
"max_insts_all_threads": 0,
|
|
|
|
|
"path": "system.cpu0",
|
2014-09-21 22:15:14 +02:00
|
|
|
"max_loads_any_thread": 0,
|
2014-05-11 04:13:51 +02:00
|
|
|
"switched_out": false,
|
|
|
|
|
"workload": [
|
|
|
|
|
{
|
|
|
|
|
"name": "workload",
|
2014-09-21 22:15:14 +02:00
|
|
|
"output": "cout",
|
|
|
|
|
"chkpt": "",
|
|
|
|
|
"errout": "cerr",
|
|
|
|
|
"system": "system",
|
|
|
|
|
"useArchPT": false,
|
2014-05-11 04:13:51 +02:00
|
|
|
"eventq_index": 0,
|
2014-09-21 22:15:14 +02:00
|
|
|
"file": "/dist/m5/regression/test-progs/anagram/bin/alpha/eio/anagram-vshort.eio.gz",
|
2014-05-11 04:13:51 +02:00
|
|
|
"cxx_class": "EioProcess",
|
|
|
|
|
"path": "system.cpu0.workload",
|
|
|
|
|
"max_stack_size": 67108864,
|
2014-09-21 22:15:14 +02:00
|
|
|
"type": "EioProcess",
|
|
|
|
|
"input": "None"
|
2014-05-11 04:13:51 +02:00
|
|
|
}
|
|
|
|
|
],
|
|
|
|
|
"name": "cpu0",
|
|
|
|
|
"dtb": {
|
|
|
|
|
"name": "dtb",
|
|
|
|
|
"eventq_index": 0,
|
|
|
|
|
"cxx_class": "AlphaISA::TLB",
|
|
|
|
|
"path": "system.cpu0.dtb",
|
|
|
|
|
"type": "AlphaTLB",
|
|
|
|
|
"size": 64
|
|
|
|
|
},
|
2014-09-21 22:15:14 +02:00
|
|
|
"simpoint_start_insts": [],
|
2014-05-11 04:13:51 +02:00
|
|
|
"max_insts_any_thread": 500000,
|
|
|
|
|
"simulate_inst_stalls": false,
|
2014-09-21 22:15:14 +02:00
|
|
|
"progress_interval": 0,
|
|
|
|
|
"branchPred": null,
|
2014-05-11 04:13:51 +02:00
|
|
|
"dcache": {
|
2014-09-21 22:15:14 +02:00
|
|
|
"is_top_level": true,
|
|
|
|
|
"prefetcher": null,
|
|
|
|
|
"clk_domain": "system.cpu_clk_domain",
|
|
|
|
|
"write_buffers": 8,
|
|
|
|
|
"response_latency": 2,
|
|
|
|
|
"cxx_class": "BaseCache",
|
|
|
|
|
"size": 32768,
|
2014-05-11 04:13:51 +02:00
|
|
|
"tags": {
|
|
|
|
|
"name": "tags",
|
|
|
|
|
"eventq_index": 0,
|
|
|
|
|
"hit_latency": 2,
|
2014-09-21 22:15:14 +02:00
|
|
|
"clk_domain": "system.cpu_clk_domain",
|
2014-05-11 04:13:51 +02:00
|
|
|
"sequential_access": false,
|
|
|
|
|
"assoc": 4,
|
|
|
|
|
"cxx_class": "LRU",
|
|
|
|
|
"path": "system.cpu0.dcache.tags",
|
|
|
|
|
"block_size": 64,
|
|
|
|
|
"type": "LRU",
|
|
|
|
|
"size": 32768
|
|
|
|
|
},
|
2014-09-21 22:15:14 +02:00
|
|
|
"system": "system",
|
2014-05-11 04:13:51 +02:00
|
|
|
"max_miss_count": 0,
|
|
|
|
|
"eventq_index": 0,
|
2014-09-21 22:15:14 +02:00
|
|
|
"mem_side": {
|
|
|
|
|
"peer": "system.toL2Bus.slave[1]",
|
|
|
|
|
"role": "MASTER"
|
|
|
|
|
},
|
|
|
|
|
"mshrs": 4,
|
|
|
|
|
"forward_snoops": true,
|
|
|
|
|
"hit_latency": 2,
|
|
|
|
|
"tgts_per_mshr": 20,
|
|
|
|
|
"addr_ranges": [
|
|
|
|
|
"0:18446744073709551615"
|
|
|
|
|
],
|
|
|
|
|
"assoc": 4,
|
2014-05-11 04:13:51 +02:00
|
|
|
"prefetch_on_access": false,
|
|
|
|
|
"path": "system.cpu0.dcache",
|
2014-09-21 22:15:14 +02:00
|
|
|
"name": "dcache",
|
2014-05-11 04:13:51 +02:00
|
|
|
"type": "BaseCache",
|
2014-09-21 22:15:14 +02:00
|
|
|
"sequential_access": false,
|
|
|
|
|
"cpu_side": {
|
|
|
|
|
"peer": "system.cpu0.dcache_port",
|
|
|
|
|
"role": "SLAVE"
|
|
|
|
|
},
|
|
|
|
|
"two_queue": false
|
2014-05-11 04:13:51 +02:00
|
|
|
},
|
2014-09-21 22:15:14 +02:00
|
|
|
"isa": [
|
|
|
|
|
{
|
|
|
|
|
"name": "isa",
|
|
|
|
|
"system": "system",
|
|
|
|
|
"eventq_index": 0,
|
|
|
|
|
"cxx_class": "AlphaISA::ISA",
|
|
|
|
|
"path": "system.cpu0.isa",
|
|
|
|
|
"type": "AlphaISA"
|
|
|
|
|
}
|
|
|
|
|
],
|
2014-05-11 04:13:51 +02:00
|
|
|
"tracer": {
|
|
|
|
|
"eventq_index": 0,
|
|
|
|
|
"path": "system.cpu0.tracer",
|
|
|
|
|
"type": "ExeTracer",
|
|
|
|
|
"name": "tracer",
|
|
|
|
|
"cxx_class": "Trace::ExeTracer"
|
|
|
|
|
}
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
"do_statistics_insts": true,
|
|
|
|
|
"numThreads": 1,
|
|
|
|
|
"itb": {
|
|
|
|
|
"name": "itb",
|
|
|
|
|
"eventq_index": 0,
|
|
|
|
|
"cxx_class": "AlphaISA::TLB",
|
|
|
|
|
"path": "system.cpu1.itb",
|
|
|
|
|
"type": "AlphaTLB",
|
|
|
|
|
"size": 48
|
|
|
|
|
},
|
2014-09-21 22:15:14 +02:00
|
|
|
"simulate_data_stalls": false,
|
2014-05-11 04:13:51 +02:00
|
|
|
"function_trace": false,
|
|
|
|
|
"do_checkpoint_insts": true,
|
|
|
|
|
"cxx_class": "AtomicSimpleCPU",
|
|
|
|
|
"max_loads_all_threads": 0,
|
2014-09-21 22:15:14 +02:00
|
|
|
"system": "system",
|
|
|
|
|
"clk_domain": "system.cpu_clk_domain",
|
2014-05-11 04:13:51 +02:00
|
|
|
"function_trace_start": 0,
|
|
|
|
|
"cpu_id": 1,
|
|
|
|
|
"width": 1,
|
2014-09-21 22:15:14 +02:00
|
|
|
"checker": null,
|
2014-05-11 04:13:51 +02:00
|
|
|
"eventq_index": 0,
|
|
|
|
|
"do_quiesce": true,
|
|
|
|
|
"type": "AtomicSimpleCPU",
|
|
|
|
|
"fastmem": false,
|
2014-09-21 22:15:14 +02:00
|
|
|
"profile": 0,
|
2014-05-11 04:13:51 +02:00
|
|
|
"icache_port": {
|
|
|
|
|
"peer": "system.cpu1.icache.cpu_side",
|
|
|
|
|
"role": "MASTER"
|
|
|
|
|
},
|
|
|
|
|
"icache": {
|
2014-09-21 22:15:14 +02:00
|
|
|
"is_top_level": true,
|
|
|
|
|
"prefetcher": null,
|
|
|
|
|
"clk_domain": "system.cpu_clk_domain",
|
|
|
|
|
"write_buffers": 8,
|
|
|
|
|
"response_latency": 2,
|
|
|
|
|
"cxx_class": "BaseCache",
|
|
|
|
|
"size": 32768,
|
2014-05-11 04:13:51 +02:00
|
|
|
"tags": {
|
|
|
|
|
"name": "tags",
|
|
|
|
|
"eventq_index": 0,
|
|
|
|
|
"hit_latency": 2,
|
2014-09-21 22:15:14 +02:00
|
|
|
"clk_domain": "system.cpu_clk_domain",
|
2014-05-11 04:13:51 +02:00
|
|
|
"sequential_access": false,
|
|
|
|
|
"assoc": 1,
|
|
|
|
|
"cxx_class": "LRU",
|
|
|
|
|
"path": "system.cpu1.icache.tags",
|
|
|
|
|
"block_size": 64,
|
|
|
|
|
"type": "LRU",
|
|
|
|
|
"size": 32768
|
|
|
|
|
},
|
2014-09-21 22:15:14 +02:00
|
|
|
"system": "system",
|
2014-05-11 04:13:51 +02:00
|
|
|
"max_miss_count": 0,
|
|
|
|
|
"eventq_index": 0,
|
2014-09-21 22:15:14 +02:00
|
|
|
"mem_side": {
|
|
|
|
|
"peer": "system.toL2Bus.slave[2]",
|
|
|
|
|
"role": "MASTER"
|
|
|
|
|
},
|
|
|
|
|
"mshrs": 4,
|
|
|
|
|
"forward_snoops": true,
|
|
|
|
|
"hit_latency": 2,
|
|
|
|
|
"tgts_per_mshr": 20,
|
|
|
|
|
"addr_ranges": [
|
|
|
|
|
"0:18446744073709551615"
|
|
|
|
|
],
|
|
|
|
|
"assoc": 1,
|
2014-05-11 04:13:51 +02:00
|
|
|
"prefetch_on_access": false,
|
|
|
|
|
"path": "system.cpu1.icache",
|
2014-09-21 22:15:14 +02:00
|
|
|
"name": "icache",
|
2014-05-11 04:13:51 +02:00
|
|
|
"type": "BaseCache",
|
2014-09-21 22:15:14 +02:00
|
|
|
"sequential_access": false,
|
|
|
|
|
"cpu_side": {
|
|
|
|
|
"peer": "system.cpu1.icache_port",
|
|
|
|
|
"role": "SLAVE"
|
|
|
|
|
},
|
|
|
|
|
"two_queue": false
|
2014-05-11 04:13:51 +02:00
|
|
|
},
|
|
|
|
|
"interrupts": {
|
|
|
|
|
"eventq_index": 0,
|
|
|
|
|
"path": "system.cpu1.interrupts",
|
|
|
|
|
"type": "AlphaInterrupts",
|
|
|
|
|
"name": "interrupts",
|
|
|
|
|
"cxx_class": "AlphaISA::Interrupts"
|
|
|
|
|
},
|
2014-09-21 22:15:14 +02:00
|
|
|
"dcache_port": {
|
|
|
|
|
"peer": "system.cpu1.dcache.cpu_side",
|
|
|
|
|
"role": "MASTER"
|
|
|
|
|
},
|
2014-05-11 04:13:51 +02:00
|
|
|
"socket_id": 0,
|
|
|
|
|
"max_insts_all_threads": 0,
|
|
|
|
|
"path": "system.cpu1",
|
2014-09-21 22:15:14 +02:00
|
|
|
"max_loads_any_thread": 0,
|
2014-05-11 04:13:51 +02:00
|
|
|
"switched_out": false,
|
|
|
|
|
"workload": [
|
|
|
|
|
{
|
|
|
|
|
"name": "workload",
|
2014-09-21 22:15:14 +02:00
|
|
|
"output": "cout",
|
|
|
|
|
"chkpt": "",
|
|
|
|
|
"errout": "cerr",
|
|
|
|
|
"system": "system",
|
|
|
|
|
"useArchPT": false,
|
2014-05-11 04:13:51 +02:00
|
|
|
"eventq_index": 0,
|
2014-09-21 22:15:14 +02:00
|
|
|
"file": "/dist/m5/regression/test-progs/anagram/bin/alpha/eio/anagram-vshort.eio.gz",
|
2014-05-11 04:13:51 +02:00
|
|
|
"cxx_class": "EioProcess",
|
|
|
|
|
"path": "system.cpu1.workload",
|
|
|
|
|
"max_stack_size": 67108864,
|
2014-09-21 22:15:14 +02:00
|
|
|
"type": "EioProcess",
|
|
|
|
|
"input": "None"
|
2014-05-11 04:13:51 +02:00
|
|
|
}
|
|
|
|
|
],
|
|
|
|
|
"name": "cpu1",
|
|
|
|
|
"dtb": {
|
|
|
|
|
"name": "dtb",
|
|
|
|
|
"eventq_index": 0,
|
|
|
|
|
"cxx_class": "AlphaISA::TLB",
|
|
|
|
|
"path": "system.cpu1.dtb",
|
|
|
|
|
"type": "AlphaTLB",
|
|
|
|
|
"size": 64
|
|
|
|
|
},
|
2014-09-21 22:15:14 +02:00
|
|
|
"simpoint_start_insts": [],
|
2014-05-11 04:13:51 +02:00
|
|
|
"max_insts_any_thread": 500000,
|
|
|
|
|
"simulate_inst_stalls": false,
|
2014-09-21 22:15:14 +02:00
|
|
|
"progress_interval": 0,
|
|
|
|
|
"branchPred": null,
|
2014-05-11 04:13:51 +02:00
|
|
|
"dcache": {
|
2014-09-21 22:15:14 +02:00
|
|
|
"is_top_level": true,
|
|
|
|
|
"prefetcher": null,
|
|
|
|
|
"clk_domain": "system.cpu_clk_domain",
|
|
|
|
|
"write_buffers": 8,
|
|
|
|
|
"response_latency": 2,
|
|
|
|
|
"cxx_class": "BaseCache",
|
|
|
|
|
"size": 32768,
|
2014-05-11 04:13:51 +02:00
|
|
|
"tags": {
|
|
|
|
|
"name": "tags",
|
|
|
|
|
"eventq_index": 0,
|
|
|
|
|
"hit_latency": 2,
|
2014-09-21 22:15:14 +02:00
|
|
|
"clk_domain": "system.cpu_clk_domain",
|
2014-05-11 04:13:51 +02:00
|
|
|
"sequential_access": false,
|
|
|
|
|
"assoc": 4,
|
|
|
|
|
"cxx_class": "LRU",
|
|
|
|
|
"path": "system.cpu1.dcache.tags",
|
|
|
|
|
"block_size": 64,
|
|
|
|
|
"type": "LRU",
|
|
|
|
|
"size": 32768
|
|
|
|
|
},
|
2014-09-21 22:15:14 +02:00
|
|
|
"system": "system",
|
2014-05-11 04:13:51 +02:00
|
|
|
"max_miss_count": 0,
|
|
|
|
|
"eventq_index": 0,
|
2014-09-21 22:15:14 +02:00
|
|
|
"mem_side": {
|
|
|
|
|
"peer": "system.toL2Bus.slave[3]",
|
|
|
|
|
"role": "MASTER"
|
|
|
|
|
},
|
|
|
|
|
"mshrs": 4,
|
|
|
|
|
"forward_snoops": true,
|
|
|
|
|
"hit_latency": 2,
|
|
|
|
|
"tgts_per_mshr": 20,
|
|
|
|
|
"addr_ranges": [
|
|
|
|
|
"0:18446744073709551615"
|
|
|
|
|
],
|
|
|
|
|
"assoc": 4,
|
2014-05-11 04:13:51 +02:00
|
|
|
"prefetch_on_access": false,
|
|
|
|
|
"path": "system.cpu1.dcache",
|
2014-09-21 22:15:14 +02:00
|
|
|
"name": "dcache",
|
2014-05-11 04:13:51 +02:00
|
|
|
"type": "BaseCache",
|
2014-09-21 22:15:14 +02:00
|
|
|
"sequential_access": false,
|
|
|
|
|
"cpu_side": {
|
|
|
|
|
"peer": "system.cpu1.dcache_port",
|
|
|
|
|
"role": "SLAVE"
|
|
|
|
|
},
|
|
|
|
|
"two_queue": false
|
2014-05-11 04:13:51 +02:00
|
|
|
},
|
2014-09-21 22:15:14 +02:00
|
|
|
"isa": [
|
|
|
|
|
{
|
|
|
|
|
"name": "isa",
|
|
|
|
|
"system": "system",
|
|
|
|
|
"eventq_index": 0,
|
|
|
|
|
"cxx_class": "AlphaISA::ISA",
|
|
|
|
|
"path": "system.cpu1.isa",
|
|
|
|
|
"type": "AlphaISA"
|
|
|
|
|
}
|
|
|
|
|
],
|
2014-05-11 04:13:51 +02:00
|
|
|
"tracer": {
|
|
|
|
|
"eventq_index": 0,
|
|
|
|
|
"path": "system.cpu1.tracer",
|
|
|
|
|
"type": "ExeTracer",
|
|
|
|
|
"name": "tracer",
|
|
|
|
|
"cxx_class": "Trace::ExeTracer"
|
|
|
|
|
}
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
"do_statistics_insts": true,
|
|
|
|
|
"numThreads": 1,
|
|
|
|
|
"itb": {
|
|
|
|
|
"name": "itb",
|
|
|
|
|
"eventq_index": 0,
|
|
|
|
|
"cxx_class": "AlphaISA::TLB",
|
|
|
|
|
"path": "system.cpu2.itb",
|
|
|
|
|
"type": "AlphaTLB",
|
|
|
|
|
"size": 48
|
|
|
|
|
},
|
2014-09-21 22:15:14 +02:00
|
|
|
"simulate_data_stalls": false,
|
2014-05-11 04:13:51 +02:00
|
|
|
"function_trace": false,
|
|
|
|
|
"do_checkpoint_insts": true,
|
|
|
|
|
"cxx_class": "AtomicSimpleCPU",
|
|
|
|
|
"max_loads_all_threads": 0,
|
2014-09-21 22:15:14 +02:00
|
|
|
"system": "system",
|
|
|
|
|
"clk_domain": "system.cpu_clk_domain",
|
2014-05-11 04:13:51 +02:00
|
|
|
"function_trace_start": 0,
|
|
|
|
|
"cpu_id": 2,
|
|
|
|
|
"width": 1,
|
2014-09-21 22:15:14 +02:00
|
|
|
"checker": null,
|
2014-05-11 04:13:51 +02:00
|
|
|
"eventq_index": 0,
|
|
|
|
|
"do_quiesce": true,
|
|
|
|
|
"type": "AtomicSimpleCPU",
|
|
|
|
|
"fastmem": false,
|
2014-09-21 22:15:14 +02:00
|
|
|
"profile": 0,
|
2014-05-11 04:13:51 +02:00
|
|
|
"icache_port": {
|
|
|
|
|
"peer": "system.cpu2.icache.cpu_side",
|
|
|
|
|
"role": "MASTER"
|
|
|
|
|
},
|
|
|
|
|
"icache": {
|
2014-09-21 22:15:14 +02:00
|
|
|
"is_top_level": true,
|
|
|
|
|
"prefetcher": null,
|
|
|
|
|
"clk_domain": "system.cpu_clk_domain",
|
|
|
|
|
"write_buffers": 8,
|
|
|
|
|
"response_latency": 2,
|
|
|
|
|
"cxx_class": "BaseCache",
|
|
|
|
|
"size": 32768,
|
2014-05-11 04:13:51 +02:00
|
|
|
"tags": {
|
|
|
|
|
"name": "tags",
|
|
|
|
|
"eventq_index": 0,
|
|
|
|
|
"hit_latency": 2,
|
2014-09-21 22:15:14 +02:00
|
|
|
"clk_domain": "system.cpu_clk_domain",
|
2014-05-11 04:13:51 +02:00
|
|
|
"sequential_access": false,
|
|
|
|
|
"assoc": 1,
|
|
|
|
|
"cxx_class": "LRU",
|
|
|
|
|
"path": "system.cpu2.icache.tags",
|
|
|
|
|
"block_size": 64,
|
|
|
|
|
"type": "LRU",
|
|
|
|
|
"size": 32768
|
|
|
|
|
},
|
2014-09-21 22:15:14 +02:00
|
|
|
"system": "system",
|
2014-05-11 04:13:51 +02:00
|
|
|
"max_miss_count": 0,
|
|
|
|
|
"eventq_index": 0,
|
2014-09-21 22:15:14 +02:00
|
|
|
"mem_side": {
|
|
|
|
|
"peer": "system.toL2Bus.slave[4]",
|
|
|
|
|
"role": "MASTER"
|
|
|
|
|
},
|
|
|
|
|
"mshrs": 4,
|
|
|
|
|
"forward_snoops": true,
|
|
|
|
|
"hit_latency": 2,
|
|
|
|
|
"tgts_per_mshr": 20,
|
|
|
|
|
"addr_ranges": [
|
|
|
|
|
"0:18446744073709551615"
|
|
|
|
|
],
|
|
|
|
|
"assoc": 1,
|
2014-05-11 04:13:51 +02:00
|
|
|
"prefetch_on_access": false,
|
|
|
|
|
"path": "system.cpu2.icache",
|
2014-09-21 22:15:14 +02:00
|
|
|
"name": "icache",
|
2014-05-11 04:13:51 +02:00
|
|
|
"type": "BaseCache",
|
2014-09-21 22:15:14 +02:00
|
|
|
"sequential_access": false,
|
|
|
|
|
"cpu_side": {
|
|
|
|
|
"peer": "system.cpu2.icache_port",
|
|
|
|
|
"role": "SLAVE"
|
|
|
|
|
},
|
|
|
|
|
"two_queue": false
|
2014-05-11 04:13:51 +02:00
|
|
|
},
|
|
|
|
|
"interrupts": {
|
|
|
|
|
"eventq_index": 0,
|
|
|
|
|
"path": "system.cpu2.interrupts",
|
|
|
|
|
"type": "AlphaInterrupts",
|
|
|
|
|
"name": "interrupts",
|
|
|
|
|
"cxx_class": "AlphaISA::Interrupts"
|
|
|
|
|
},
|
2014-09-21 22:15:14 +02:00
|
|
|
"dcache_port": {
|
|
|
|
|
"peer": "system.cpu2.dcache.cpu_side",
|
|
|
|
|
"role": "MASTER"
|
|
|
|
|
},
|
2014-05-11 04:13:51 +02:00
|
|
|
"socket_id": 0,
|
|
|
|
|
"max_insts_all_threads": 0,
|
|
|
|
|
"path": "system.cpu2",
|
2014-09-21 22:15:14 +02:00
|
|
|
"max_loads_any_thread": 0,
|
2014-05-11 04:13:51 +02:00
|
|
|
"switched_out": false,
|
|
|
|
|
"workload": [
|
|
|
|
|
{
|
|
|
|
|
"name": "workload",
|
2014-09-21 22:15:14 +02:00
|
|
|
"output": "cout",
|
|
|
|
|
"chkpt": "",
|
|
|
|
|
"errout": "cerr",
|
|
|
|
|
"system": "system",
|
|
|
|
|
"useArchPT": false,
|
2014-05-11 04:13:51 +02:00
|
|
|
"eventq_index": 0,
|
2014-09-21 22:15:14 +02:00
|
|
|
"file": "/dist/m5/regression/test-progs/anagram/bin/alpha/eio/anagram-vshort.eio.gz",
|
2014-05-11 04:13:51 +02:00
|
|
|
"cxx_class": "EioProcess",
|
|
|
|
|
"path": "system.cpu2.workload",
|
|
|
|
|
"max_stack_size": 67108864,
|
2014-09-21 22:15:14 +02:00
|
|
|
"type": "EioProcess",
|
|
|
|
|
"input": "None"
|
2014-05-11 04:13:51 +02:00
|
|
|
}
|
|
|
|
|
],
|
|
|
|
|
"name": "cpu2",
|
|
|
|
|
"dtb": {
|
|
|
|
|
"name": "dtb",
|
|
|
|
|
"eventq_index": 0,
|
|
|
|
|
"cxx_class": "AlphaISA::TLB",
|
|
|
|
|
"path": "system.cpu2.dtb",
|
|
|
|
|
"type": "AlphaTLB",
|
|
|
|
|
"size": 64
|
|
|
|
|
},
|
2014-09-21 22:15:14 +02:00
|
|
|
"simpoint_start_insts": [],
|
2014-05-11 04:13:51 +02:00
|
|
|
"max_insts_any_thread": 500000,
|
|
|
|
|
"simulate_inst_stalls": false,
|
2014-09-21 22:15:14 +02:00
|
|
|
"progress_interval": 0,
|
|
|
|
|
"branchPred": null,
|
2014-05-11 04:13:51 +02:00
|
|
|
"dcache": {
|
2014-09-21 22:15:14 +02:00
|
|
|
"is_top_level": true,
|
|
|
|
|
"prefetcher": null,
|
|
|
|
|
"clk_domain": "system.cpu_clk_domain",
|
|
|
|
|
"write_buffers": 8,
|
|
|
|
|
"response_latency": 2,
|
|
|
|
|
"cxx_class": "BaseCache",
|
|
|
|
|
"size": 32768,
|
2014-05-11 04:13:51 +02:00
|
|
|
"tags": {
|
|
|
|
|
"name": "tags",
|
|
|
|
|
"eventq_index": 0,
|
|
|
|
|
"hit_latency": 2,
|
2014-09-21 22:15:14 +02:00
|
|
|
"clk_domain": "system.cpu_clk_domain",
|
2014-05-11 04:13:51 +02:00
|
|
|
"sequential_access": false,
|
|
|
|
|
"assoc": 4,
|
|
|
|
|
"cxx_class": "LRU",
|
|
|
|
|
"path": "system.cpu2.dcache.tags",
|
|
|
|
|
"block_size": 64,
|
|
|
|
|
"type": "LRU",
|
|
|
|
|
"size": 32768
|
|
|
|
|
},
|
2014-09-21 22:15:14 +02:00
|
|
|
"system": "system",
|
2014-05-11 04:13:51 +02:00
|
|
|
"max_miss_count": 0,
|
|
|
|
|
"eventq_index": 0,
|
2014-09-21 22:15:14 +02:00
|
|
|
"mem_side": {
|
|
|
|
|
"peer": "system.toL2Bus.slave[5]",
|
|
|
|
|
"role": "MASTER"
|
|
|
|
|
},
|
|
|
|
|
"mshrs": 4,
|
|
|
|
|
"forward_snoops": true,
|
|
|
|
|
"hit_latency": 2,
|
|
|
|
|
"tgts_per_mshr": 20,
|
|
|
|
|
"addr_ranges": [
|
|
|
|
|
"0:18446744073709551615"
|
|
|
|
|
],
|
|
|
|
|
"assoc": 4,
|
2014-05-11 04:13:51 +02:00
|
|
|
"prefetch_on_access": false,
|
|
|
|
|
"path": "system.cpu2.dcache",
|
2014-09-21 22:15:14 +02:00
|
|
|
"name": "dcache",
|
2014-05-11 04:13:51 +02:00
|
|
|
"type": "BaseCache",
|
2014-09-21 22:15:14 +02:00
|
|
|
"sequential_access": false,
|
|
|
|
|
"cpu_side": {
|
|
|
|
|
"peer": "system.cpu2.dcache_port",
|
|
|
|
|
"role": "SLAVE"
|
|
|
|
|
},
|
|
|
|
|
"two_queue": false
|
2014-05-11 04:13:51 +02:00
|
|
|
},
|
2014-09-21 22:15:14 +02:00
|
|
|
"isa": [
|
|
|
|
|
{
|
|
|
|
|
"name": "isa",
|
|
|
|
|
"system": "system",
|
|
|
|
|
"eventq_index": 0,
|
|
|
|
|
"cxx_class": "AlphaISA::ISA",
|
|
|
|
|
"path": "system.cpu2.isa",
|
|
|
|
|
"type": "AlphaISA"
|
|
|
|
|
}
|
|
|
|
|
],
|
2014-05-11 04:13:51 +02:00
|
|
|
"tracer": {
|
|
|
|
|
"eventq_index": 0,
|
|
|
|
|
"path": "system.cpu2.tracer",
|
|
|
|
|
"type": "ExeTracer",
|
|
|
|
|
"name": "tracer",
|
|
|
|
|
"cxx_class": "Trace::ExeTracer"
|
|
|
|
|
}
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
"do_statistics_insts": true,
|
|
|
|
|
"numThreads": 1,
|
|
|
|
|
"itb": {
|
|
|
|
|
"name": "itb",
|
|
|
|
|
"eventq_index": 0,
|
|
|
|
|
"cxx_class": "AlphaISA::TLB",
|
|
|
|
|
"path": "system.cpu3.itb",
|
|
|
|
|
"type": "AlphaTLB",
|
|
|
|
|
"size": 48
|
|
|
|
|
},
|
2014-09-21 22:15:14 +02:00
|
|
|
"simulate_data_stalls": false,
|
2014-05-11 04:13:51 +02:00
|
|
|
"function_trace": false,
|
|
|
|
|
"do_checkpoint_insts": true,
|
|
|
|
|
"cxx_class": "AtomicSimpleCPU",
|
|
|
|
|
"max_loads_all_threads": 0,
|
2014-09-21 22:15:14 +02:00
|
|
|
"system": "system",
|
|
|
|
|
"clk_domain": "system.cpu_clk_domain",
|
2014-05-11 04:13:51 +02:00
|
|
|
"function_trace_start": 0,
|
|
|
|
|
"cpu_id": 3,
|
|
|
|
|
"width": 1,
|
2014-09-21 22:15:14 +02:00
|
|
|
"checker": null,
|
2014-05-11 04:13:51 +02:00
|
|
|
"eventq_index": 0,
|
|
|
|
|
"do_quiesce": true,
|
|
|
|
|
"type": "AtomicSimpleCPU",
|
|
|
|
|
"fastmem": false,
|
2014-09-21 22:15:14 +02:00
|
|
|
"profile": 0,
|
2014-05-11 04:13:51 +02:00
|
|
|
"icache_port": {
|
|
|
|
|
"peer": "system.cpu3.icache.cpu_side",
|
|
|
|
|
"role": "MASTER"
|
|
|
|
|
},
|
|
|
|
|
"icache": {
|
2014-09-21 22:15:14 +02:00
|
|
|
"is_top_level": true,
|
|
|
|
|
"prefetcher": null,
|
|
|
|
|
"clk_domain": "system.cpu_clk_domain",
|
|
|
|
|
"write_buffers": 8,
|
|
|
|
|
"response_latency": 2,
|
|
|
|
|
"cxx_class": "BaseCache",
|
|
|
|
|
"size": 32768,
|
2014-05-11 04:13:51 +02:00
|
|
|
"tags": {
|
|
|
|
|
"name": "tags",
|
|
|
|
|
"eventq_index": 0,
|
|
|
|
|
"hit_latency": 2,
|
2014-09-21 22:15:14 +02:00
|
|
|
"clk_domain": "system.cpu_clk_domain",
|
2014-05-11 04:13:51 +02:00
|
|
|
"sequential_access": false,
|
|
|
|
|
"assoc": 1,
|
|
|
|
|
"cxx_class": "LRU",
|
|
|
|
|
"path": "system.cpu3.icache.tags",
|
|
|
|
|
"block_size": 64,
|
|
|
|
|
"type": "LRU",
|
|
|
|
|
"size": 32768
|
|
|
|
|
},
|
2014-09-21 22:15:14 +02:00
|
|
|
"system": "system",
|
2014-05-11 04:13:51 +02:00
|
|
|
"max_miss_count": 0,
|
|
|
|
|
"eventq_index": 0,
|
2014-09-21 22:15:14 +02:00
|
|
|
"mem_side": {
|
|
|
|
|
"peer": "system.toL2Bus.slave[6]",
|
|
|
|
|
"role": "MASTER"
|
|
|
|
|
},
|
|
|
|
|
"mshrs": 4,
|
|
|
|
|
"forward_snoops": true,
|
|
|
|
|
"hit_latency": 2,
|
|
|
|
|
"tgts_per_mshr": 20,
|
|
|
|
|
"addr_ranges": [
|
|
|
|
|
"0:18446744073709551615"
|
|
|
|
|
],
|
|
|
|
|
"assoc": 1,
|
2014-05-11 04:13:51 +02:00
|
|
|
"prefetch_on_access": false,
|
|
|
|
|
"path": "system.cpu3.icache",
|
2014-09-21 22:15:14 +02:00
|
|
|
"name": "icache",
|
2014-05-11 04:13:51 +02:00
|
|
|
"type": "BaseCache",
|
2014-09-21 22:15:14 +02:00
|
|
|
"sequential_access": false,
|
|
|
|
|
"cpu_side": {
|
|
|
|
|
"peer": "system.cpu3.icache_port",
|
|
|
|
|
"role": "SLAVE"
|
|
|
|
|
},
|
|
|
|
|
"two_queue": false
|
2014-05-11 04:13:51 +02:00
|
|
|
},
|
|
|
|
|
"interrupts": {
|
|
|
|
|
"eventq_index": 0,
|
|
|
|
|
"path": "system.cpu3.interrupts",
|
|
|
|
|
"type": "AlphaInterrupts",
|
|
|
|
|
"name": "interrupts",
|
|
|
|
|
"cxx_class": "AlphaISA::Interrupts"
|
|
|
|
|
},
|
2014-09-21 22:15:14 +02:00
|
|
|
"dcache_port": {
|
|
|
|
|
"peer": "system.cpu3.dcache.cpu_side",
|
|
|
|
|
"role": "MASTER"
|
|
|
|
|
},
|
2014-05-11 04:13:51 +02:00
|
|
|
"socket_id": 0,
|
|
|
|
|
"max_insts_all_threads": 0,
|
|
|
|
|
"path": "system.cpu3",
|
2014-09-21 22:15:14 +02:00
|
|
|
"max_loads_any_thread": 0,
|
2014-05-11 04:13:51 +02:00
|
|
|
"switched_out": false,
|
|
|
|
|
"workload": [
|
|
|
|
|
{
|
|
|
|
|
"name": "workload",
|
2014-09-21 22:15:14 +02:00
|
|
|
"output": "cout",
|
|
|
|
|
"chkpt": "",
|
|
|
|
|
"errout": "cerr",
|
|
|
|
|
"system": "system",
|
|
|
|
|
"useArchPT": false,
|
2014-05-11 04:13:51 +02:00
|
|
|
"eventq_index": 0,
|
2014-09-21 22:15:14 +02:00
|
|
|
"file": "/dist/m5/regression/test-progs/anagram/bin/alpha/eio/anagram-vshort.eio.gz",
|
2014-05-11 04:13:51 +02:00
|
|
|
"cxx_class": "EioProcess",
|
|
|
|
|
"path": "system.cpu3.workload",
|
|
|
|
|
"max_stack_size": 67108864,
|
2014-09-21 22:15:14 +02:00
|
|
|
"type": "EioProcess",
|
|
|
|
|
"input": "None"
|
2014-05-11 04:13:51 +02:00
|
|
|
}
|
|
|
|
|
],
|
|
|
|
|
"name": "cpu3",
|
|
|
|
|
"dtb": {
|
|
|
|
|
"name": "dtb",
|
|
|
|
|
"eventq_index": 0,
|
|
|
|
|
"cxx_class": "AlphaISA::TLB",
|
|
|
|
|
"path": "system.cpu3.dtb",
|
|
|
|
|
"type": "AlphaTLB",
|
|
|
|
|
"size": 64
|
|
|
|
|
},
|
2014-09-21 22:15:14 +02:00
|
|
|
"simpoint_start_insts": [],
|
2014-05-11 04:13:51 +02:00
|
|
|
"max_insts_any_thread": 500000,
|
|
|
|
|
"simulate_inst_stalls": false,
|
2014-09-21 22:15:14 +02:00
|
|
|
"progress_interval": 0,
|
|
|
|
|
"branchPred": null,
|
2014-05-11 04:13:51 +02:00
|
|
|
"dcache": {
|
2014-09-21 22:15:14 +02:00
|
|
|
"is_top_level": true,
|
|
|
|
|
"prefetcher": null,
|
|
|
|
|
"clk_domain": "system.cpu_clk_domain",
|
|
|
|
|
"write_buffers": 8,
|
|
|
|
|
"response_latency": 2,
|
|
|
|
|
"cxx_class": "BaseCache",
|
|
|
|
|
"size": 32768,
|
2014-05-11 04:13:51 +02:00
|
|
|
"tags": {
|
|
|
|
|
"name": "tags",
|
|
|
|
|
"eventq_index": 0,
|
|
|
|
|
"hit_latency": 2,
|
2014-09-21 22:15:14 +02:00
|
|
|
"clk_domain": "system.cpu_clk_domain",
|
2014-05-11 04:13:51 +02:00
|
|
|
"sequential_access": false,
|
|
|
|
|
"assoc": 4,
|
|
|
|
|
"cxx_class": "LRU",
|
|
|
|
|
"path": "system.cpu3.dcache.tags",
|
|
|
|
|
"block_size": 64,
|
|
|
|
|
"type": "LRU",
|
|
|
|
|
"size": 32768
|
|
|
|
|
},
|
2014-09-21 22:15:14 +02:00
|
|
|
"system": "system",
|
2014-05-11 04:13:51 +02:00
|
|
|
"max_miss_count": 0,
|
|
|
|
|
"eventq_index": 0,
|
2014-09-21 22:15:14 +02:00
|
|
|
"mem_side": {
|
|
|
|
|
"peer": "system.toL2Bus.slave[7]",
|
|
|
|
|
"role": "MASTER"
|
|
|
|
|
},
|
|
|
|
|
"mshrs": 4,
|
|
|
|
|
"forward_snoops": true,
|
|
|
|
|
"hit_latency": 2,
|
|
|
|
|
"tgts_per_mshr": 20,
|
|
|
|
|
"addr_ranges": [
|
|
|
|
|
"0:18446744073709551615"
|
|
|
|
|
],
|
|
|
|
|
"assoc": 4,
|
2014-05-11 04:13:51 +02:00
|
|
|
"prefetch_on_access": false,
|
|
|
|
|
"path": "system.cpu3.dcache",
|
2014-09-21 22:15:14 +02:00
|
|
|
"name": "dcache",
|
2014-05-11 04:13:51 +02:00
|
|
|
"type": "BaseCache",
|
2014-09-21 22:15:14 +02:00
|
|
|
"sequential_access": false,
|
|
|
|
|
"cpu_side": {
|
|
|
|
|
"peer": "system.cpu3.dcache_port",
|
|
|
|
|
"role": "SLAVE"
|
|
|
|
|
},
|
|
|
|
|
"two_queue": false
|
2014-05-11 04:13:51 +02:00
|
|
|
},
|
2014-09-21 22:15:14 +02:00
|
|
|
"isa": [
|
|
|
|
|
{
|
|
|
|
|
"name": "isa",
|
|
|
|
|
"system": "system",
|
|
|
|
|
"eventq_index": 0,
|
|
|
|
|
"cxx_class": "AlphaISA::ISA",
|
|
|
|
|
"path": "system.cpu3.isa",
|
|
|
|
|
"type": "AlphaISA"
|
|
|
|
|
}
|
|
|
|
|
],
|
2014-05-11 04:13:51 +02:00
|
|
|
"tracer": {
|
|
|
|
|
"eventq_index": 0,
|
|
|
|
|
"path": "system.cpu3.tracer",
|
|
|
|
|
"type": "ExeTracer",
|
|
|
|
|
"name": "tracer",
|
|
|
|
|
"cxx_class": "Trace::ExeTracer"
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
],
|
2014-09-21 22:15:14 +02:00
|
|
|
"num_work_ids": 16,
|
|
|
|
|
"work_item_id": -1,
|
2014-05-11 04:13:51 +02:00
|
|
|
"work_begin_cpu_id_exit": -1
|
|
|
|
|
},
|
2014-09-21 22:15:14 +02:00
|
|
|
"time_sync_period": 100000000000,
|
2014-05-11 04:13:51 +02:00
|
|
|
"eventq_index": 0,
|
2014-09-21 22:15:14 +02:00
|
|
|
"time_sync_spin_threshold": 100000000,
|
2014-05-11 04:13:51 +02:00
|
|
|
"cxx_class": "Root",
|
|
|
|
|
"path": "root",
|
|
|
|
|
"time_sync_enable": false,
|
|
|
|
|
"type": "Root",
|
|
|
|
|
"full_system": false
|
|
|
|
|
}
|
