gem5/configs/example/memtest.py

# Copyright (c) 2006-2007 The Regents of The University of Michigan
# All rights reserved.
#
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# modification, are permitted provided that the following conditions are
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# redistributions in binary form must reproduce the above copyright
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# this software without specific prior written permission.
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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# Authors: Ron Dreslinski

import m5
from m5.objects import *
import os, optparse, sys
m5.AddToPath('../common')

parser = optparse.OptionParser()

parser.add_option("--caches", action="store_true")
parser.add_option("-t", "--timing", action="store_true")
parser.add_option("-m", "--maxtick", type="int")
parser.add_option("-l", "--maxloads", default = "1000000000000", type="int")
parser.add_option("-n", "--numtesters", default = "8", type="int")
parser.add_option("-p", "--protocol",
                  default="moesi",
                  help="The coherence protocol to use for the L1'a (i.e. MOESI, MOSI)")

(options, args) = parser.parse_args()

if args:
     print "Error: script doesn't take any positional arguments"
     sys.exit(1)

# --------------------
# Base L1 Cache
# ====================

class L1(BaseCache):
    latency = '1ns'
    block_size = 64
    mshrs = 12
    tgts_per_mshr = 8
    protocol = CoherenceProtocol(protocol=options.protocol)

# ----------------------
# Base L2 Cache
# ----------------------

class L2(BaseCache):
    block_size = 64
    latency = '10ns'
    mshrs = 92
    tgts_per_mshr = 16
    write_buffers = 8

#MAX CORES IS 8 with the false sharing method
if options.numtesters > 8:
     print "Error: NUmber of testers limited to 8 because of false sharing"
     sys,exit(1)

cpus = [ MemTest(atomic=not options.timing, max_loads=options.maxloads,
                 percent_functional=50, percent_uncacheable=10,
                 progress_interval=1000)
         for i in xrange(options.numtesters) ]

# system simulated
system = System(cpu = cpus, funcmem = PhysicalMemory(),
                physmem = PhysicalMemory(latency = "50ns"), membus = Bus(clock="500MHz", width=16))

# l2cache & bus
if options.caches:
    system.toL2Bus = Bus(clock="500MHz", width=16)
    system.l2c = L2(size='64kB', assoc=8)
    system.l2c.cpu_side = system.toL2Bus.port

    # connect l2c to membus
    system.l2c.mem_side = system.membus.port

# add L1 caches
for cpu in cpus:
    if options.caches:
         cpu.l1c = L1(size = '32kB', assoc = 4)
         cpu.test = cpu.l1c.cpu_side
         cpu.l1c.mem_side = system.toL2Bus.port
    else:
         cpu.test = system.membus.port
    system.funcmem.port = cpu.functional

# connect memory to membus
system.physmem.port = system.membus.port


# -----------------------
# run simulation
# -----------------------

root = Root( system = system )
if options.timing:
    root.system.mem_mode = 'timing'
else:
    root.system.mem_mode = 'atomic'

# Not much point in this being higher than the L1 latency
m5.ticks.setGlobalFrequency('1ns')

# instantiate configuration
m5.instantiate(root)

# simulate until program terminates
if options.maxtick:
    exit_event = m5.simulate(options.maxtick)
else:
    exit_event = m5.simulate(10000000000000)

print 'Exiting @ tick', m5.curTick(), 'because', exit_event.getCause()