2006-02-21 05:26:39 +01:00
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/*
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* Copyright (c) 2001-2005 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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2006-06-01 01:26:56 +02:00
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*
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* Authors: Ron Dreslinski
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* Steve Reinhardt
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2006-02-21 05:26:39 +01:00
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*/
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#include <string>
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2006-02-21 09:32:42 +01:00
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#include "base/chunk_generator.hh"
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2006-02-21 05:26:39 +01:00
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#include "mem/port.hh"
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#include "mem/translating_port.hh"
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#include "mem/page_table.hh"
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2007-05-09 21:37:46 +02:00
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#include "sim/process.hh"
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2006-02-21 05:26:39 +01:00
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2006-03-10 01:21:35 +01:00
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using namespace TheISA;
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2006-05-26 19:48:35 +02:00
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TranslatingPort::TranslatingPort(const std::string &_name,
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2007-05-09 21:37:46 +02:00
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Process *p, AllocType alloc)
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: FunctionalPort(_name), pTable(p->pTable), process(p),
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allocating(alloc)
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2006-02-21 05:26:39 +01:00
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{ }
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TranslatingPort::~TranslatingPort()
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{ }
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2006-03-12 06:40:29 +01:00
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bool
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2006-03-12 22:38:16 +01:00
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TranslatingPort::tryReadBlob(Addr addr, uint8_t *p, int size)
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2006-02-21 05:26:39 +01:00
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{
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Addr paddr;
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2006-02-21 09:32:42 +01:00
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int prevSize = 0;
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2006-02-21 05:26:39 +01:00
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2006-02-21 09:32:42 +01:00
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for (ChunkGenerator gen(addr, size, VMPageSize); !gen.done(); gen.next()) {
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2006-02-21 05:26:39 +01:00
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2006-03-02 07:01:03 +01:00
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if (!pTable->translate(gen.addr(),paddr))
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2006-03-12 06:40:29 +01:00
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return false;
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2006-02-21 05:26:39 +01:00
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2006-03-30 22:59:49 +02:00
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Port::readBlob(paddr, p + prevSize, gen.size());
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2006-03-02 07:01:03 +01:00
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prevSize += gen.size();
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2006-02-21 09:32:42 +01:00
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}
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2006-02-21 05:26:39 +01:00
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2006-03-12 06:40:29 +01:00
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return true;
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2006-02-21 05:26:39 +01:00
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}
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2006-03-12 06:40:29 +01:00
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void
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2006-03-12 22:38:16 +01:00
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TranslatingPort::readBlob(Addr addr, uint8_t *p, int size)
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2006-03-12 06:40:29 +01:00
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{
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2006-03-12 22:38:16 +01:00
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if (!tryReadBlob(addr, p, size))
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fatal("readBlob(0x%x, ...) failed", addr);
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2006-03-12 06:40:29 +01:00
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}
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bool
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2006-03-30 22:59:49 +02:00
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TranslatingPort::tryWriteBlob(Addr addr, uint8_t *p, int size)
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2006-02-21 05:26:39 +01:00
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{
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2006-03-12 06:40:29 +01:00
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2006-02-21 05:26:39 +01:00
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Addr paddr;
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2006-02-21 09:32:42 +01:00
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int prevSize = 0;
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2006-02-21 05:26:39 +01:00
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2006-02-21 09:32:42 +01:00
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for (ChunkGenerator gen(addr, size, VMPageSize); !gen.done(); gen.next()) {
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2006-02-21 05:26:39 +01:00
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2006-03-02 07:01:03 +01:00
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if (!pTable->translate(gen.addr(), paddr)) {
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2007-05-09 21:37:46 +02:00
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if (allocating == Always) {
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2006-03-02 07:01:03 +01:00
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pTable->allocate(roundDown(gen.addr(), VMPageSize),
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VMPageSize);
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2007-05-09 21:37:46 +02:00
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} else if (allocating == NextPage) {
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// check if we've accessed the next page on the stack
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if (!process->checkAndAllocNextPage(gen.addr()))
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panic("Page table fault when accessing virtual address %#x "
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"during functional write\n", gen.addr());
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2006-03-02 07:01:03 +01:00
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} else {
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2006-03-12 06:40:29 +01:00
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return false;
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2006-03-02 07:01:03 +01:00
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}
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2007-05-09 21:37:46 +02:00
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pTable->translate(gen.addr(), paddr);
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2006-03-02 07:01:03 +01:00
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}
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2006-02-21 09:32:42 +01:00
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2006-03-30 22:59:49 +02:00
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Port::writeBlob(paddr, p + prevSize, gen.size());
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2006-03-02 07:01:03 +01:00
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prevSize += gen.size();
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2006-02-21 09:32:42 +01:00
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}
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2006-02-21 05:26:39 +01:00
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2006-03-12 06:40:29 +01:00
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return true;
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2006-02-21 05:26:39 +01:00
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}
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2006-03-02 16:31:48 +01:00
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2006-03-12 06:40:29 +01:00
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void
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2006-03-30 22:59:49 +02:00
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TranslatingPort::writeBlob(Addr addr, uint8_t *p, int size)
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2006-03-12 06:40:29 +01:00
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{
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2006-03-30 22:59:49 +02:00
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if (!tryWriteBlob(addr, p, size))
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2006-03-12 22:38:16 +01:00
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fatal("writeBlob(0x%x, ...) failed", addr);
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2006-03-12 06:40:29 +01:00
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}
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bool
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2006-03-30 22:59:49 +02:00
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TranslatingPort::tryMemsetBlob(Addr addr, uint8_t val, int size)
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2006-02-21 05:26:39 +01:00
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{
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Addr paddr;
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2006-02-21 09:32:42 +01:00
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for (ChunkGenerator gen(addr, size, VMPageSize); !gen.done(); gen.next()) {
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2006-03-02 16:31:48 +01:00
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if (!pTable->translate(gen.addr(), paddr)) {
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2007-05-09 21:37:46 +02:00
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if (allocating == Always) {
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2006-03-02 16:31:48 +01:00
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pTable->allocate(roundDown(gen.addr(), VMPageSize),
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VMPageSize);
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pTable->translate(gen.addr(), paddr);
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} else {
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2006-03-12 06:40:29 +01:00
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return false;
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2006-03-02 16:31:48 +01:00
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}
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}
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2006-02-21 05:26:39 +01:00
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2006-03-30 22:59:49 +02:00
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Port::memsetBlob(paddr, val, gen.size());
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2006-02-21 09:32:42 +01:00
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}
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2006-02-21 05:26:39 +01:00
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2006-03-12 06:40:29 +01:00
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return true;
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2006-02-21 05:26:39 +01:00
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}
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2006-03-02 16:31:48 +01:00
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2006-03-12 06:40:29 +01:00
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void
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2006-03-30 22:59:49 +02:00
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TranslatingPort::memsetBlob(Addr addr, uint8_t val, int size)
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2006-03-12 06:40:29 +01:00
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{
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2006-03-30 22:59:49 +02:00
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if (!tryMemsetBlob(addr, val, size))
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2006-03-12 22:38:16 +01:00
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fatal("memsetBlob(0x%x, ...) failed", addr);
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2006-03-12 06:40:29 +01:00
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}
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2006-02-21 05:26:39 +01:00
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2006-03-12 06:40:29 +01:00
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bool
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2006-03-12 22:38:16 +01:00
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TranslatingPort::tryWriteString(Addr addr, const char *str)
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2006-02-21 05:26:39 +01:00
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{
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2006-02-21 08:15:02 +01:00
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Addr paddr,vaddr;
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uint8_t c;
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2006-02-21 05:26:39 +01:00
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2006-02-21 08:15:02 +01:00
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vaddr = addr;
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2006-02-21 05:26:39 +01:00
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2006-02-21 08:15:02 +01:00
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do {
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c = *str++;
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if (!pTable->translate(vaddr++,paddr))
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2006-03-12 06:40:29 +01:00
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return false;
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2006-02-21 08:15:02 +01:00
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2006-03-30 22:59:49 +02:00
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Port::writeBlob(paddr, &c, 1);
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2006-02-21 08:15:02 +01:00
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} while (c);
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2006-02-21 05:26:39 +01:00
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2006-03-12 06:40:29 +01:00
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return true;
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2006-02-21 05:26:39 +01:00
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}
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2006-03-12 06:40:29 +01:00
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void
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2006-03-12 22:38:16 +01:00
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TranslatingPort::writeString(Addr addr, const char *str)
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2006-03-12 06:40:29 +01:00
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{
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2006-03-12 22:38:16 +01:00
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if (!tryWriteString(addr, str))
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fatal("writeString(0x%x, ...) failed", addr);
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2006-03-12 06:40:29 +01:00
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}
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bool
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2006-03-12 22:38:16 +01:00
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TranslatingPort::tryReadString(std::string &str, Addr addr)
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2006-02-21 05:26:39 +01:00
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{
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2006-02-21 08:15:02 +01:00
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Addr paddr,vaddr;
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uint8_t c;
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2006-02-21 05:26:39 +01:00
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2006-02-21 08:15:02 +01:00
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vaddr = addr;
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2006-02-21 05:26:39 +01:00
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2006-02-21 08:15:02 +01:00
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do {
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if (!pTable->translate(vaddr++,paddr))
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2006-03-12 06:40:29 +01:00
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return false;
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2006-02-21 08:15:02 +01:00
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2006-03-30 22:59:49 +02:00
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Port::readBlob(paddr, &c, 1);
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2006-02-21 08:15:02 +01:00
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str += c;
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} while (c);
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2006-02-21 05:26:39 +01:00
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2006-03-12 06:40:29 +01:00
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return true;
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}
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void
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2006-03-12 22:38:16 +01:00
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TranslatingPort::readString(std::string &str, Addr addr)
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2006-03-12 06:40:29 +01:00
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{
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2006-03-12 22:38:16 +01:00
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if (!tryReadString(str, addr))
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fatal("readString(0x%x, ...) failed", addr);
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2006-02-21 05:26:39 +01:00
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}
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