2011-02-05 09:16:09 +01:00
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---------- Begin Simulation Statistics ----------
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2011-03-17 05:43:54 +01:00
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host_inst_rate 189714 # Simulator instruction rate (inst/s)
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host_mem_usage 264736 # Number of bytes of host memory used
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host_seconds 8051.48 # Real time elapsed on the host
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host_tick_rate 75880827 # Simulator tick rate (ticks/s)
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2011-02-05 09:16:09 +01:00
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sim_freq 1000000000000 # Frequency of simulated ticks
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2011-02-14 02:46:04 +01:00
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sim_insts 1527476062 # Number of instructions simulated
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sim_seconds 0.610953 # Number of seconds simulated
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sim_ticks 610952992000 # Number of ticks simulated
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2011-02-05 09:16:09 +01:00
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system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
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2011-02-14 02:46:04 +01:00
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system.cpu.BPredUnit.BTBHits 220273443 # Number of BTB hits
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system.cpu.BPredUnit.BTBLookups 239822696 # Number of BTB lookups
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2011-02-05 09:16:09 +01:00
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system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions.
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2011-02-14 02:46:04 +01:00
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system.cpu.BPredUnit.condIncorrect 16691862 # Number of conditional branches incorrect
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system.cpu.BPredUnit.condPredicted 254901320 # Number of conditional branches predicted
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system.cpu.BPredUnit.lookups 254901320 # Number of BP lookups
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2011-02-05 09:16:09 +01:00
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system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target.
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2011-02-14 02:46:04 +01:00
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system.cpu.commit.COM:branches 149616585 # Number of branches committed
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system.cpu.commit.COM:bw_lim_events 33918821 # number cycles where commit BW limit reached
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2011-02-05 09:16:09 +01:00
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system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
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2011-02-14 02:46:04 +01:00
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system.cpu.commit.COM:committed_per_cycle::samples 1083369873 # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::mean 1.409930 # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::stdev 1.877801 # Number of insts commited each cycle
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2011-02-05 09:16:09 +01:00
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system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
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2011-02-14 02:46:04 +01:00
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system.cpu.commit.COM:committed_per_cycle::0 454928288 41.99% 41.99% # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::1 282557908 26.08% 68.07% # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::2 120287774 11.10% 79.18% # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::3 105365409 9.73% 88.90% # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::4 40172301 3.71% 92.61% # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::5 27676804 2.55% 95.16% # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::6 11415389 1.05% 96.22% # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::7 7047179 0.65% 96.87% # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::8 33918821 3.13% 100.00% # Number of insts commited each cycle
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2011-02-05 09:16:09 +01:00
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system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle
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2011-02-14 02:46:04 +01:00
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system.cpu.commit.COM:committed_per_cycle::total 1083369873 # Number of insts commited each cycle
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system.cpu.commit.COM:count 1527476062 # Number of instructions committed
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2011-02-08 04:23:13 +01:00
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system.cpu.commit.COM:fp_insts 0 # Number of committed floating point instructions.
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system.cpu.commit.COM:function_calls 0 # Number of function calls committed.
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2011-02-14 02:46:04 +01:00
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system.cpu.commit.COM:int_insts 1526804920 # Number of committed integer instructions.
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system.cpu.commit.COM:loads 383724495 # Number of loads committed
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2011-02-05 09:16:09 +01:00
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system.cpu.commit.COM:membars 0 # Number of memory barriers committed
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2011-02-14 02:46:04 +01:00
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system.cpu.commit.COM:refs 532790180 # Number of memory references committed
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2011-02-05 09:16:09 +01:00
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system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
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2011-02-14 02:46:04 +01:00
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system.cpu.commit.branchMispredicts 16726957 # The number of times a branch was mispredicted
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system.cpu.commit.commitCommittedInsts 1527476062 # The number of committed instructions
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2011-02-05 09:16:09 +01:00
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system.cpu.commit.commitNonSpecStalls 553 # The number of times commit has been forced to stall to communicate backwards
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2011-02-14 02:46:04 +01:00
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system.cpu.commit.commitSquashedInsts 841443918 # The number of squashed insts skipped by commit
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system.cpu.committedInsts 1527476062 # Number of Instructions Simulated
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system.cpu.committedInsts_total 1527476062 # Number of Instructions Simulated
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system.cpu.cpi 0.799951 # CPI: Cycles Per Instruction
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system.cpu.cpi_total 0.799951 # CPI: Total CPI of All Threads
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system.cpu.dcache.ReadReq_accesses 320046346 # number of ReadReq accesses(hits+misses)
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system.cpu.dcache.ReadReq_avg_miss_latency 15794.070061 # average ReadReq miss latency
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system.cpu.dcache.ReadReq_avg_mshr_miss_latency 8150.695480 # average ReadReq mshr miss latency
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system.cpu.dcache.ReadReq_hits 317137092 # number of ReadReq hits
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system.cpu.dcache.ReadReq_miss_latency 45948961500 # number of ReadReq miss cycles
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system.cpu.dcache.ReadReq_miss_rate 0.009090 # miss rate for ReadReq accesses
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system.cpu.dcache.ReadReq_misses 2909254 # number of ReadReq misses
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system.cpu.dcache.ReadReq_mshr_hits 1183970 # number of ReadReq MSHR hits
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system.cpu.dcache.ReadReq_mshr_miss_latency 14062264500 # number of ReadReq MSHR miss cycles
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system.cpu.dcache.ReadReq_mshr_miss_rate 0.005391 # mshr miss rate for ReadReq accesses
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system.cpu.dcache.ReadReq_mshr_misses 1725284 # number of ReadReq MSHR misses
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system.cpu.dcache.WriteReq_accesses 149065701 # number of WriteReq accesses(hits+misses)
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system.cpu.dcache.WriteReq_avg_miss_latency 23554.108597 # average WriteReq miss latency
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system.cpu.dcache.WriteReq_avg_mshr_miss_latency 18051.470496 # average WriteReq mshr miss latency
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system.cpu.dcache.WriteReq_hits 147419835 # number of WriteReq hits
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system.cpu.dcache.WriteReq_miss_latency 38766906500 # number of WriteReq miss cycles
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system.cpu.dcache.WriteReq_miss_rate 0.011041 # miss rate for WriteReq accesses
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system.cpu.dcache.WriteReq_misses 1645866 # number of WriteReq misses
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system.cpu.dcache.WriteReq_mshr_hits 608291 # number of WriteReq MSHR hits
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system.cpu.dcache.WriteReq_mshr_miss_latency 18729754500 # number of WriteReq MSHR miss cycles
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system.cpu.dcache.WriteReq_mshr_miss_rate 0.006961 # mshr miss rate for WriteReq accesses
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system.cpu.dcache.WriteReq_mshr_misses 1037575 # number of WriteReq MSHR misses
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2011-02-05 09:16:09 +01:00
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system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
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system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
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2011-02-14 02:46:04 +01:00
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system.cpu.dcache.avg_refs 185.704246 # Average number of references to valid blocks.
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2011-02-05 09:16:09 +01:00
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system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
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system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
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system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
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system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
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system.cpu.dcache.cache_copies 0 # number of cache copies performed
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2011-02-14 02:46:04 +01:00
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system.cpu.dcache.demand_accesses 469112047 # number of demand (read+write) accesses
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system.cpu.dcache.demand_avg_miss_latency 18597.944291 # average overall miss latency
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system.cpu.dcache.demand_avg_mshr_miss_latency 11868.871701 # average overall mshr miss latency
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system.cpu.dcache.demand_hits 464556927 # number of demand (read+write) hits
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system.cpu.dcache.demand_miss_latency 84715868000 # number of demand (read+write) miss cycles
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system.cpu.dcache.demand_miss_rate 0.009710 # miss rate for demand accesses
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system.cpu.dcache.demand_misses 4555120 # number of demand (read+write) misses
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system.cpu.dcache.demand_mshr_hits 1792261 # number of demand (read+write) MSHR hits
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system.cpu.dcache.demand_mshr_miss_latency 32792019000 # number of demand (read+write) MSHR miss cycles
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system.cpu.dcache.demand_mshr_miss_rate 0.005890 # mshr miss rate for demand accesses
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system.cpu.dcache.demand_mshr_misses 2762859 # number of demand (read+write) MSHR misses
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2011-02-05 09:16:09 +01:00
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system.cpu.dcache.fast_writes 0 # number of fast writes performed
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system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
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system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
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2011-02-14 02:46:04 +01:00
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system.cpu.dcache.occ_%::0 0.998028 # Average percentage of cache occupancy
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system.cpu.dcache.occ_blocks::0 4087.922333 # Average occupied blocks per context
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system.cpu.dcache.overall_accesses 469112047 # number of overall (read+write) accesses
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system.cpu.dcache.overall_avg_miss_latency 18597.944291 # average overall miss latency
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system.cpu.dcache.overall_avg_mshr_miss_latency 11868.871701 # average overall mshr miss latency
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2011-02-05 09:16:09 +01:00
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system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
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2011-02-14 02:46:04 +01:00
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system.cpu.dcache.overall_hits 464556927 # number of overall hits
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system.cpu.dcache.overall_miss_latency 84715868000 # number of overall miss cycles
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system.cpu.dcache.overall_miss_rate 0.009710 # miss rate for overall accesses
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system.cpu.dcache.overall_misses 4555120 # number of overall misses
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system.cpu.dcache.overall_mshr_hits 1792261 # number of overall MSHR hits
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system.cpu.dcache.overall_mshr_miss_latency 32792019000 # number of overall MSHR miss cycles
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system.cpu.dcache.overall_mshr_miss_rate 0.005890 # mshr miss rate for overall accesses
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system.cpu.dcache.overall_mshr_misses 2762859 # number of overall MSHR misses
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2011-02-05 09:16:09 +01:00
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system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
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system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
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2011-02-14 02:46:04 +01:00
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system.cpu.dcache.replacements 2504740 # number of replacements
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system.cpu.dcache.sampled_refs 2508836 # Sample count of references to valid blocks.
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2011-02-05 09:16:09 +01:00
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system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
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2011-02-14 02:46:04 +01:00
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system.cpu.dcache.tagsinuse 4087.922333 # Cycle average of tags in use
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system.cpu.dcache.total_refs 465901497 # Total number of references to valid blocks.
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system.cpu.dcache.warmup_cycle 2529382000 # Cycle when the warmup percentage was hit.
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system.cpu.dcache.writebacks 2229751 # number of writebacks
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system.cpu.decode.DECODE:BlockedCycles 215366555 # Number of cycles decode is blocked
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system.cpu.decode.DECODE:DecodedInsts 2516935544 # Number of instructions handled by decode
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system.cpu.decode.DECODE:IdleCycles 437043857 # Number of cycles decode is idle
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system.cpu.decode.DECODE:RunCycles 404205746 # Number of cycles decode is running
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system.cpu.decode.DECODE:SquashCycles 113949773 # Number of cycles decode is squashing
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system.cpu.decode.DECODE:UnblockCycles 26753715 # Number of cycles decode is unblocking
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system.cpu.fetch.Branches 254901320 # Number of branches that fetch encountered
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system.cpu.fetch.CacheLines 190461812 # Number of cache lines fetched
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system.cpu.fetch.Cycles 445534669 # Number of cycles fetch has run and was not squashing or blocked
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system.cpu.fetch.IcacheSquashes 3068431 # Number of outstanding Icache misses that were squashed
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system.cpu.fetch.Insts 1374706338 # Number of instructions fetch has processed
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system.cpu.fetch.MiscStallCycles 85274 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
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system.cpu.fetch.SquashCycles 18549281 # Number of cycles fetch has spent squashing
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system.cpu.fetch.branchRate 0.208610 # Number of branch fetches per cycle
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system.cpu.fetch.icacheStallCycles 190461812 # Number of cycles fetch is stalled on an Icache miss
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system.cpu.fetch.predictedBranches 220273443 # Number of branches that fetch has predicted taken
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system.cpu.fetch.rate 1.125051 # Number of inst fetches per cycle
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system.cpu.fetch.rateDist::samples 1197319646 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::mean 2.144693 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::stdev 3.178811 # Number of instructions fetched each cycle (Total)
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2011-02-05 09:16:09 +01:00
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system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
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2011-02-14 02:46:04 +01:00
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system.cpu.fetch.rateDist::0 756027205 63.14% 63.14% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::1 34054494 2.84% 65.99% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::2 36745231 3.07% 69.06% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::3 33767076 2.82% 71.88% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::4 21459245 1.79% 73.67% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::5 40493114 3.38% 77.05% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::6 45860411 3.83% 80.88% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::7 35731624 2.98% 83.87% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::8 193181246 16.13% 100.00% # Number of instructions fetched each cycle (Total)
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2011-02-05 09:16:09 +01:00
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system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
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2011-02-14 02:46:04 +01:00
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system.cpu.fetch.rateDist::total 1197319646 # Number of instructions fetched each cycle (Total)
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system.cpu.fp_regfile_reads 31 # number of floating regfile reads
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system.cpu.icache.ReadReq_accesses 190461812 # number of ReadReq accesses(hits+misses)
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system.cpu.icache.ReadReq_avg_miss_latency 6527.954910 # average ReadReq miss latency
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system.cpu.icache.ReadReq_avg_mshr_miss_latency 3419.281975 # average ReadReq mshr miss latency
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system.cpu.icache.ReadReq_hits 190192396 # number of ReadReq hits
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system.cpu.icache.ReadReq_miss_latency 1758735500 # number of ReadReq miss cycles
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system.cpu.icache.ReadReq_miss_rate 0.001415 # miss rate for ReadReq accesses
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system.cpu.icache.ReadReq_misses 269416 # number of ReadReq misses
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system.cpu.icache.ReadReq_mshr_hits 1570 # number of ReadReq MSHR hits
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system.cpu.icache.ReadReq_mshr_miss_latency 915841000 # number of ReadReq MSHR miss cycles
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system.cpu.icache.ReadReq_mshr_miss_rate 0.001406 # mshr miss rate for ReadReq accesses
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system.cpu.icache.ReadReq_mshr_misses 267846 # number of ReadReq MSHR misses
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2011-02-05 09:16:09 +01:00
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system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
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system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
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2011-02-14 02:46:04 +01:00
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system.cpu.icache.avg_refs 17699.832480 # Average number of references to valid blocks.
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2011-02-05 09:16:09 +01:00
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system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
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system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
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system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
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system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
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system.cpu.icache.cache_copies 0 # number of cache copies performed
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2011-02-14 02:46:04 +01:00
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system.cpu.icache.demand_accesses 190461812 # number of demand (read+write) accesses
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system.cpu.icache.demand_avg_miss_latency 6527.954910 # average overall miss latency
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system.cpu.icache.demand_avg_mshr_miss_latency 3419.281975 # average overall mshr miss latency
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system.cpu.icache.demand_hits 190192396 # number of demand (read+write) hits
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|
|
system.cpu.icache.demand_miss_latency 1758735500 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.icache.demand_miss_rate 0.001415 # miss rate for demand accesses
|
|
|
|
|
system.cpu.icache.demand_misses 269416 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.icache.demand_mshr_hits 1570 # number of demand (read+write) MSHR hits
|
|
|
|
|
system.cpu.icache.demand_mshr_miss_latency 915841000 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.icache.demand_mshr_miss_rate 0.001406 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.icache.demand_mshr_misses 267846 # number of demand (read+write) MSHR misses
|
2011-02-05 09:16:09 +01:00
|
|
|
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
|
|
|
|
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
|
|
|
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
2011-02-14 02:46:04 +01:00
|
|
|
system.cpu.icache.occ_%::0 0.466021 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.icache.occ_blocks::0 954.411836 # Average occupied blocks per context
|
|
|
|
|
system.cpu.icache.overall_accesses 190461812 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.icache.overall_avg_miss_latency 6527.954910 # average overall miss latency
|
|
|
|
|
system.cpu.icache.overall_avg_mshr_miss_latency 3419.281975 # average overall mshr miss latency
|
2011-02-05 09:16:09 +01:00
|
|
|
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
2011-02-14 02:46:04 +01:00
|
|
|
system.cpu.icache.overall_hits 190192396 # number of overall hits
|
|
|
|
|
system.cpu.icache.overall_miss_latency 1758735500 # number of overall miss cycles
|
|
|
|
|
system.cpu.icache.overall_miss_rate 0.001415 # miss rate for overall accesses
|
|
|
|
|
system.cpu.icache.overall_misses 269416 # number of overall misses
|
|
|
|
|
system.cpu.icache.overall_mshr_hits 1570 # number of overall MSHR hits
|
|
|
|
|
system.cpu.icache.overall_mshr_miss_latency 915841000 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu.icache.overall_mshr_miss_rate 0.001406 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.icache.overall_mshr_misses 267846 # number of overall MSHR misses
|
2011-02-05 09:16:09 +01:00
|
|
|
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
|
|
|
|
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
2011-02-14 02:46:04 +01:00
|
|
|
system.cpu.icache.replacements 9298 # number of replacements
|
|
|
|
|
system.cpu.icache.sampled_refs 10745 # Sample count of references to valid blocks.
|
2011-02-05 09:16:09 +01:00
|
|
|
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
2011-02-14 02:46:04 +01:00
|
|
|
system.cpu.icache.tagsinuse 954.411836 # Cycle average of tags in use
|
|
|
|
|
system.cpu.icache.total_refs 190184700 # Total number of references to valid blocks.
|
2011-02-05 09:16:09 +01:00
|
|
|
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
2011-02-14 02:46:04 +01:00
|
|
|
system.cpu.icache.writebacks 3 # number of writebacks
|
|
|
|
|
system.cpu.idleCycles 24586339 # Total number of cycles that the CPU has spent unscheduled due to idling
|
|
|
|
|
system.cpu.iew.EXEC:branches 175611349 # Number of branches executed
|
2011-02-05 09:16:09 +01:00
|
|
|
system.cpu.iew.EXEC:nop 0 # number of nop insts executed
|
2011-02-14 02:46:04 +01:00
|
|
|
system.cpu.iew.EXEC:rate 1.537639 # Inst execution rate
|
|
|
|
|
system.cpu.iew.EXEC:refs 604612823 # number of memory reference insts executed
|
|
|
|
|
system.cpu.iew.EXEC:stores 164362000 # Number of stores executed
|
2011-02-05 09:16:09 +01:00
|
|
|
system.cpu.iew.EXEC:swp 0 # number of swp insts executed
|
2011-03-17 05:43:54 +01:00
|
|
|
system.cpu.iew.WB:consumers 2150204737 # num instructions consuming a value
|
2011-02-14 02:46:04 +01:00
|
|
|
system.cpu.iew.WB:count 1865910107 # cumulative count of insts written-back
|
|
|
|
|
system.cpu.iew.WB:fanout 0.666196 # average fanout of values written-back
|
2011-02-05 09:16:09 +01:00
|
|
|
system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
|
|
|
|
|
system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
2011-03-17 05:43:54 +01:00
|
|
|
system.cpu.iew.WB:producers 1432457554 # num instructions producing a value
|
2011-02-14 02:46:04 +01:00
|
|
|
system.cpu.iew.WB:rate 1.527049 # insts written-back per cycle
|
|
|
|
|
system.cpu.iew.WB:sent 1872952311 # cumulative count of insts sent to commit
|
|
|
|
|
system.cpu.iew.branchMispredicts 18187438 # Number of branch mispredicts detected at execute
|
|
|
|
|
system.cpu.iew.iewBlockCycles 9702727 # Number of cycles IEW is blocking
|
|
|
|
|
system.cpu.iew.iewDispLoadInsts 598780500 # Number of dispatched load instructions
|
2011-03-17 05:43:54 +01:00
|
|
|
system.cpu.iew.iewDispNonSpecInsts 9848 # Number of dispatched non-speculative instructions
|
2011-02-14 02:46:04 +01:00
|
|
|
system.cpu.iew.iewDispSquashedInsts 2427132 # Number of squashed instructions skipped by dispatch
|
|
|
|
|
system.cpu.iew.iewDispStoreInsts 227725972 # Number of dispatched store instructions
|
|
|
|
|
system.cpu.iew.iewDispatchedInsts 2368916953 # Number of instructions dispatched to IQ
|
|
|
|
|
system.cpu.iew.iewExecLoadInsts 440250823 # Number of load instructions executed
|
2011-03-17 05:43:54 +01:00
|
|
|
system.cpu.iew.iewExecSquashedInsts 24902521 # Number of squashed instructions skipped in execute
|
2011-02-14 02:46:04 +01:00
|
|
|
system.cpu.iew.iewExecutedInsts 1878850199 # Number of executed instructions
|
|
|
|
|
system.cpu.iew.iewIQFullEvents 999062 # Number of times the IQ has become full, causing a stall
|
2011-02-05 09:16:09 +01:00
|
|
|
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
2011-02-14 02:46:04 +01:00
|
|
|
system.cpu.iew.iewLSQFullEvents 48995 # Number of times the LSQ has become full, causing a stall
|
|
|
|
|
system.cpu.iew.iewSquashCycles 113949773 # Number of cycles IEW is squashing
|
|
|
|
|
system.cpu.iew.iewUnblockCycles 1501929 # Number of cycles IEW is unblocking
|
2011-02-05 09:16:09 +01:00
|
|
|
system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
|
|
|
|
system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
|
2011-02-14 02:46:04 +01:00
|
|
|
system.cpu.iew.lsq.thread.0.forwLoads 119150872 # Number of loads that had data forwarded from stores
|
|
|
|
|
system.cpu.iew.lsq.thread.0.ignoredResponses 153037 # Number of memory responses ignored because the instruction is squashed
|
2011-02-05 09:16:09 +01:00
|
|
|
system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
|
|
|
|
system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
2011-02-14 02:46:04 +01:00
|
|
|
system.cpu.iew.lsq.thread.0.memOrderViolation 1905759 # Number of memory ordering violations
|
|
|
|
|
system.cpu.iew.lsq.thread.0.rescheduledLoads 1230 # Number of loads that were rescheduled
|
|
|
|
|
system.cpu.iew.lsq.thread.0.squashedLoads 215056005 # Number of loads squashed
|
|
|
|
|
system.cpu.iew.lsq.thread.0.squashedStores 78660287 # Number of stores squashed
|
|
|
|
|
system.cpu.iew.memOrderViolationEvents 1905759 # Number of memory order violations
|
|
|
|
|
system.cpu.iew.predictedNotTakenIncorrect 2718790 # Number of branches that were predicted not taken incorrectly
|
|
|
|
|
system.cpu.iew.predictedTakenIncorrect 15468648 # Number of branches that were predicted taken incorrectly
|
|
|
|
|
system.cpu.int_regfile_reads 3097184079 # number of integer regfile reads
|
|
|
|
|
system.cpu.int_regfile_writes 1741804464 # number of integer regfile writes
|
|
|
|
|
system.cpu.ipc 1.250077 # IPC: Instructions Per Cycle
|
|
|
|
|
system.cpu.ipc_total 1.250077 # IPC: Total IPC of All Threads
|
|
|
|
|
system.cpu.iq.ISSUE:FU_type_0::No_OpClass 2283854 0.12% 0.12% # Type of FU issued
|
|
|
|
|
system.cpu.iq.ISSUE:FU_type_0::IntAlu 1286143659 67.56% 67.68% # Type of FU issued
|
|
|
|
|
system.cpu.iq.ISSUE:FU_type_0::IntMult 0 0.00% 67.68% # Type of FU issued
|
|
|
|
|
system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 67.68% # Type of FU issued
|
|
|
|
|
system.cpu.iq.ISSUE:FU_type_0::FloatAdd 0 0.00% 67.68% # Type of FU issued
|
|
|
|
|
system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 67.68% # Type of FU issued
|
|
|
|
|
system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 67.68% # Type of FU issued
|
|
|
|
|
system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 67.68% # Type of FU issued
|
|
|
|
|
system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 67.68% # Type of FU issued
|
|
|
|
|
system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 67.68% # Type of FU issued
|
|
|
|
|
system.cpu.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 67.68% # Type of FU issued
|
|
|
|
|
system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 67.68% # Type of FU issued
|
|
|
|
|
system.cpu.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 67.68% # Type of FU issued
|
|
|
|
|
system.cpu.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 67.68% # Type of FU issued
|
|
|
|
|
system.cpu.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 67.68% # Type of FU issued
|
|
|
|
|
system.cpu.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 67.68% # Type of FU issued
|
|
|
|
|
system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 67.68% # Type of FU issued
|
|
|
|
|
system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 67.68% # Type of FU issued
|
|
|
|
|
system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 67.68% # Type of FU issued
|
|
|
|
|
system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 67.68% # Type of FU issued
|
|
|
|
|
system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 67.68% # Type of FU issued
|
|
|
|
|
system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 67.68% # Type of FU issued
|
|
|
|
|
system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 67.68% # Type of FU issued
|
|
|
|
|
system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 67.68% # Type of FU issued
|
|
|
|
|
system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 0 0.00% 67.68% # Type of FU issued
|
|
|
|
|
system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 67.68% # Type of FU issued
|
|
|
|
|
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 0 0.00% 67.68% # Type of FU issued
|
|
|
|
|
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 67.68% # Type of FU issued
|
|
|
|
|
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 67.68% # Type of FU issued
|
|
|
|
|
system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 67.68% # Type of FU issued
|
2011-03-17 05:43:54 +01:00
|
|
|
system.cpu.iq.ISSUE:FU_type_0::MemRead 446588314 23.46% 91.14% # Type of FU issued
|
2011-02-14 02:46:04 +01:00
|
|
|
system.cpu.iq.ISSUE:FU_type_0::MemWrite 168736893 8.86% 100.00% # Type of FU issued
|
2011-02-05 09:16:09 +01:00
|
|
|
system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
|
|
|
|
system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
2011-03-17 05:43:54 +01:00
|
|
|
system.cpu.iq.ISSUE:FU_type_0::total 1903752720 # Type of FU issued
|
2011-02-14 02:46:04 +01:00
|
|
|
system.cpu.iq.ISSUE:fu_busy_cnt 12019370 # FU busy when requested
|
|
|
|
|
system.cpu.iq.ISSUE:fu_busy_rate 0.006314 # FU busy rate (busy events/executed inst)
|
2011-02-05 09:16:09 +01:00
|
|
|
system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
2011-02-14 02:46:04 +01:00
|
|
|
system.cpu.iq.ISSUE:fu_full::IntAlu 1063366 8.85% 8.85% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 8.85% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 8.85% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 8.85% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 8.85% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 8.85% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 8.85% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 8.85% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 8.85% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.ISSUE:fu_full::SimdAdd 0 0.00% 8.85% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 8.85% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.ISSUE:fu_full::SimdAlu 0 0.00% 8.85% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.ISSUE:fu_full::SimdCmp 0 0.00% 8.85% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.ISSUE:fu_full::SimdCvt 0 0.00% 8.85% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.ISSUE:fu_full::SimdMisc 0 0.00% 8.85% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.ISSUE:fu_full::SimdMult 0 0.00% 8.85% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 8.85% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.ISSUE:fu_full::SimdShift 0 0.00% 8.85% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 8.85% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 8.85% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 8.85% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 8.85% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 8.85% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 8.85% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 8.85% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 8.85% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 8.85% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 8.85% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 8.85% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.ISSUE:fu_full::MemRead 7508013 62.47% 71.31% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.ISSUE:fu_full::MemWrite 3447991 28.69% 100.00% # attempts to use FU when none available
|
2011-02-05 09:16:09 +01:00
|
|
|
system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
2011-02-14 02:46:04 +01:00
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle::samples 1197319646 # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle::mean 1.590012 # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.576110 # Number of insts issued each cycle
|
2011-02-05 09:16:09 +01:00
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
2011-02-14 02:46:04 +01:00
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle::0 380569061 31.79% 31.79% # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle::1 297509781 24.85% 56.63% # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle::2 210374930 17.57% 74.20% # Number of insts issued each cycle
|
2011-03-17 05:43:54 +01:00
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle::3 147240856 12.30% 86.50% # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle::4 95168175 7.95% 94.45% # Number of insts issued each cycle
|
2011-02-14 02:46:04 +01:00
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle::5 42314918 3.53% 97.98% # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle::6 17818883 1.49% 99.47% # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle::7 5974413 0.50% 99.97% # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle::8 348629 0.03% 100.00% # Number of insts issued each cycle
|
2011-02-05 09:16:09 +01:00
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
2011-02-14 02:46:04 +01:00
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle::total 1197319646 # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.ISSUE:rate 1.558019 # Inst issue rate
|
|
|
|
|
system.cpu.iq.fp_alu_accesses 59 # Number of floating point alu accesses
|
|
|
|
|
system.cpu.iq.fp_inst_queue_reads 119 # Number of floating instruction queue reads
|
|
|
|
|
system.cpu.iq.fp_inst_queue_wakeup_accesses 31 # Number of floating instruction queue wakeup accesses
|
|
|
|
|
system.cpu.iq.fp_inst_queue_writes 7970 # Number of floating instruction queue writes
|
2011-03-17 05:43:54 +01:00
|
|
|
system.cpu.iq.int_alu_accesses 1913488177 # Number of integer alu accesses
|
|
|
|
|
system.cpu.iq.int_inst_queue_reads 5017400187 # Number of integer instruction queue reads
|
2011-02-14 02:46:04 +01:00
|
|
|
system.cpu.iq.int_inst_queue_wakeup_accesses 1865910076 # Number of integer instruction queue wakeup accesses
|
|
|
|
|
system.cpu.iq.int_inst_queue_writes 3209512631 # Number of integer instruction queue writes
|
2011-03-17 05:43:54 +01:00
|
|
|
system.cpu.iq.iqInstsAdded 2368907105 # Number of instructions added to the IQ (excludes non-spec)
|
|
|
|
|
system.cpu.iq.iqInstsIssued 1903752720 # Number of instructions issued
|
|
|
|
|
system.cpu.iq.iqNonSpecInstsAdded 9848 # Number of non-speculative instructions added to the IQ
|
2011-02-14 02:46:04 +01:00
|
|
|
system.cpu.iq.iqSquashedInstsExamined 838752495 # Number of squashed instructions iterated over during squash; mainly for profiling
|
|
|
|
|
system.cpu.iq.iqSquashedInstsIssued 555850 # Number of squashed instructions issued
|
2011-03-17 05:43:54 +01:00
|
|
|
system.cpu.iq.iqSquashedNonSpecRemoved 9295 # Number of squashed non-spec instructions that were removed
|
|
|
|
|
system.cpu.iq.iqSquashedOperandsExamined 1472780543 # Number of squashed operands that are examined and possibly removed from graph
|
2011-02-14 02:46:04 +01:00
|
|
|
system.cpu.l2cache.ReadExReq_accesses 786848 # number of ReadExReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency 34255.494728 # average ReadExReq miss latency
|
|
|
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31001.453653 # average ReadExReq mshr miss latency
|
|
|
|
|
system.cpu.l2cache.ReadExReq_hits 539884 # number of ReadExReq hits
|
|
|
|
|
system.cpu.l2cache.ReadExReq_miss_latency 8459874000 # number of ReadExReq miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadExReq_miss_rate 0.313865 # miss rate for ReadExReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_misses 246964 # number of ReadExReq misses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency 7656243000 # number of ReadExReq MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.313865 # mshr miss rate for ReadExReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_mshr_misses 246964 # number of ReadExReq MSHR misses
|
|
|
|
|
system.cpu.l2cache.ReadReq_accesses 1732679 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency 34171.480760 # average ReadReq miss latency
|
|
|
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31002.917505 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.l2cache.ReadReq_hits 1415970 # number of ReadReq hits
|
|
|
|
|
system.cpu.l2cache.ReadReq_miss_latency 10822415500 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadReq_miss_rate 0.182786 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_misses 316709 # number of ReadReq misses
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency 9818903000 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.182786 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_misses 316709 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_accesses 256943 # number of UpgradeReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_avg_miss_latency 40.077896 # average UpgradeReq miss latency
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31003.030576 # average UpgradeReq mshr miss latency
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_hits 1216 # number of UpgradeReq hits
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_miss_latency 10249000 # number of UpgradeReq miss cycles
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_miss_rate 0.995267 # miss rate for UpgradeReq accesses
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_misses 255727 # number of UpgradeReq misses
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 7928312000 # number of UpgradeReq MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 0.995267 # mshr miss rate for UpgradeReq accesses
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_mshr_misses 255727 # number of UpgradeReq MSHR misses
|
|
|
|
|
system.cpu.l2cache.Writeback_accesses 2229754 # number of Writeback accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.Writeback_hits 2229754 # number of Writeback hits
|
2011-02-05 09:16:09 +01:00
|
|
|
system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
2011-02-14 02:46:04 +01:00
|
|
|
system.cpu.l2cache.avg_refs 5.404070 # Average number of references to valid blocks.
|
2011-02-05 09:16:09 +01:00
|
|
|
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
2011-02-14 02:46:04 +01:00
|
|
|
system.cpu.l2cache.demand_accesses 2519527 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.demand_avg_miss_latency 34208.290090 # average overall miss latency
|
|
|
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency 31002.276142 # average overall mshr miss latency
|
|
|
|
|
system.cpu.l2cache.demand_hits 1955854 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.l2cache.demand_miss_latency 19282289500 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_miss_rate 0.223722 # miss rate for demand accesses
|
|
|
|
|
system.cpu.l2cache.demand_misses 563673 # number of demand (read+write) misses
|
2011-02-05 09:16:09 +01:00
|
|
|
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
2011-02-14 02:46:04 +01:00
|
|
|
system.cpu.l2cache.demand_mshr_miss_latency 17475146000 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_mshr_miss_rate 0.223722 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.l2cache.demand_mshr_misses 563673 # number of demand (read+write) MSHR misses
|
2011-02-05 09:16:09 +01:00
|
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
|
|
|
|
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
|
|
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
2011-02-14 02:46:04 +01:00
|
|
|
system.cpu.l2cache.occ_%::0 0.213694 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.l2cache.occ_%::1 0.433705 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.l2cache.occ_blocks::0 7002.339473 # Average occupied blocks per context
|
|
|
|
|
system.cpu.l2cache.occ_blocks::1 14211.631717 # Average occupied blocks per context
|
|
|
|
|
system.cpu.l2cache.overall_accesses 2519527 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.overall_avg_miss_latency 34208.290090 # average overall miss latency
|
|
|
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency 31002.276142 # average overall mshr miss latency
|
2011-02-05 09:16:09 +01:00
|
|
|
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
2011-02-14 02:46:04 +01:00
|
|
|
system.cpu.l2cache.overall_hits 1955854 # number of overall hits
|
|
|
|
|
system.cpu.l2cache.overall_miss_latency 19282289500 # number of overall miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_miss_rate 0.223722 # miss rate for overall accesses
|
|
|
|
|
system.cpu.l2cache.overall_misses 563673 # number of overall misses
|
2011-02-05 09:16:09 +01:00
|
|
|
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
2011-02-14 02:46:04 +01:00
|
|
|
system.cpu.l2cache.overall_mshr_miss_latency 17475146000 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_mshr_miss_rate 0.223722 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.l2cache.overall_mshr_misses 563673 # number of overall MSHR misses
|
2011-02-05 09:16:09 +01:00
|
|
|
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
|
|
|
|
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
2011-02-14 02:46:04 +01:00
|
|
|
system.cpu.l2cache.replacements 553099 # number of replacements
|
|
|
|
|
system.cpu.l2cache.sampled_refs 571950 # Sample count of references to valid blocks.
|
2011-02-05 09:16:09 +01:00
|
|
|
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
2011-02-14 02:46:04 +01:00
|
|
|
system.cpu.l2cache.tagsinuse 21213.971190 # Cycle average of tags in use
|
|
|
|
|
system.cpu.l2cache.total_refs 3090858 # Total number of references to valid blocks.
|
|
|
|
|
system.cpu.l2cache.warmup_cycle 329890014000 # Cycle when the warmup percentage was hit.
|
|
|
|
|
system.cpu.l2cache.writebacks 404346 # number of writebacks
|
2011-03-17 05:43:54 +01:00
|
|
|
system.cpu.memDep0.conflictingLoads 432038121 # Number of conflicting loads.
|
|
|
|
|
system.cpu.memDep0.conflictingStores 167866970 # Number of conflicting stores.
|
2011-02-14 02:46:04 +01:00
|
|
|
system.cpu.memDep0.insertedLoads 598780500 # Number of loads inserted to the mem dependence unit.
|
|
|
|
|
system.cpu.memDep0.insertedStores 227724252 # Number of stores inserted to the mem dependence unit.
|
|
|
|
|
system.cpu.misc_regfile_reads 1024928879 # number of misc regfile reads
|
|
|
|
|
system.cpu.numCycles 1221905985 # number of cpu cycles simulated
|
2011-02-08 04:23:13 +01:00
|
|
|
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
|
|
|
|
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
2011-02-14 02:46:04 +01:00
|
|
|
system.cpu.rename.RENAME:BlockCycles 64472267 # Number of cycles rename is blocking
|
|
|
|
|
system.cpu.rename.RENAME:CommittedMaps 1425688721 # Number of HB maps that are committed
|
|
|
|
|
system.cpu.rename.RENAME:IQFullEvents 52544368 # Number of times rename has blocked due to IQ full
|
|
|
|
|
system.cpu.rename.RENAME:IdleCycles 479786184 # Number of cycles rename is idle
|
|
|
|
|
system.cpu.rename.RENAME:LSQFullEvents 82632603 # Number of times rename has blocked due to LSQ full
|
|
|
|
|
system.cpu.rename.RENAME:ROBFullEvents 8428 # Number of times rename has blocked due to ROB full
|
|
|
|
|
system.cpu.rename.RENAME:RenameLookups 5772028874 # Number of register rename lookups that rename has made
|
|
|
|
|
system.cpu.rename.RENAME:RenamedInsts 2456264739 # Number of instructions processed by rename
|
|
|
|
|
system.cpu.rename.RENAME:RenamedOperands 2290118455 # Number of destination operands rename has renamed
|
|
|
|
|
system.cpu.rename.RENAME:RunCycles 385614091 # Number of cycles rename is running
|
|
|
|
|
system.cpu.rename.RENAME:SquashCycles 113949773 # Number of cycles rename is squashing
|
|
|
|
|
system.cpu.rename.RENAME:UnblockCycles 153477395 # Number of cycles rename is unblocking
|
|
|
|
|
system.cpu.rename.RENAME:UndoneMaps 864429734 # Number of HB maps that are undone due to squashing
|
|
|
|
|
system.cpu.rename.RENAME:fp_rename_lookups 19762 # Number of floating rename lookups
|
|
|
|
|
system.cpu.rename.RENAME:int_rename_lookups 5772009112 # Number of integer rename lookups
|
|
|
|
|
system.cpu.rename.RENAME:serializeStallCycles 19936 # count of cycles rename stalled for serializing inst
|
|
|
|
|
system.cpu.rename.RENAME:serializingInsts 2550 # count of serializing insts renamed
|
|
|
|
|
system.cpu.rename.RENAME:skidInsts 360051799 # count of insts added to the skid buffer
|
|
|
|
|
system.cpu.rename.RENAME:tempSerializingInsts 2561 # count of temporary serializing insts renamed
|
|
|
|
|
system.cpu.rob.rob_reads 3418371032 # The number of ROB reads
|
|
|
|
|
system.cpu.rob.rob_writes 4851844016 # The number of ROB writes
|
|
|
|
|
system.cpu.timesIdled 625791 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
2011-02-05 09:16:09 +01:00
|
|
|
system.cpu.workload.PROG:num_syscalls 551 # Number of system calls
|
|
|
|
|
|
|
|
|
|
---------- End Simulation Statistics ----------
|
