2010-08-23 18:18:40 +02:00
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/*
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* Copyright (c) 2010 ARM Limited
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* All rights reserved
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Copyright (c) 2005 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Ali Saidi
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*/
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/** @file
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* Implementiation of a PL011 UART
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*/
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#ifndef __DEV_ARM_PL011_H__
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#define __DEV_ARM_PL011_H__
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#include "base/range.hh"
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#include "dev/io_device.hh"
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#include "dev/uart.hh"
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#include "params/Pl011.hh"
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class Gic;
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class Pl011 : public Uart
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{
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protected:
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2010-08-23 18:18:40 +02:00
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static const uint64_t AMBA_ID = ULL(0xb105f00d00341011);
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2010-08-23 18:18:40 +02:00
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static const int UART_DR = 0x000;
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static const int UART_FR = 0x018;
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static const int UART_FR_CTS = 0x001;
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static const int UART_FR_TXFE = 0x080;
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static const int UART_FR_RXFE = 0x010;
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static const int UART_IBRD = 0x024;
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static const int UART_FBRD = 0x028;
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static const int UART_LCRH = 0x02C;
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static const int UART_CR = 0x030;
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static const int UART_IFLS = 0x034;
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static const int UART_IMSC = 0x038;
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static const int UART_RIS = 0x03C;
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static const int UART_MIS = 0x040;
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static const int UART_ICR = 0x044;
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uint16_t control;
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/** fractional baud rate divisor. Not used for anything but reporting
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* written value */
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uint16_t fbrd;
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/** integer baud rate divisor. Not used for anything but reporting
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* written value */
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uint16_t ibrd;
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/** Line control register. Not used for anything but reporting
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* written value */
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uint16_t lcrh;
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/** interrupt fifo level register. Not used for anything but reporting
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* written value */
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uint16_t ifls;
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BitUnion16(INTREG)
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Bitfield<0> rimim;
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Bitfield<1> ctsmim;
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Bitfield<2> dcdmim;
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Bitfield<3> dsrmim;
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Bitfield<4> rxim;
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Bitfield<5> txim;
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Bitfield<6> rtim;
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Bitfield<7> feim;
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Bitfield<8> peim;
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Bitfield<9> beim;
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Bitfield<10> oeim;
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Bitfield<15,11> rsvd;
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EndBitUnion(INTREG)
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/** interrupt mask register. */
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INTREG imsc;
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/** raw interrupt status register */
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INTREG rawInt;
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/** Masked interrupt status register */
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INTREG maskInt;
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/** Interrupt number to generate */
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int intNum;
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/** Gic to use for interrupting */
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Gic *gic;
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/** Should the simulation end on an EOT */
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bool endOnEOT;
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/** Delay before interrupting */
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Tick intDelay;
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/** Function to generate interrupt */
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void generateInterrupt();
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/** Wrapper to create an event out of the thing */
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EventWrapper<Pl011, &Pl011::generateInterrupt> intEvent;
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public:
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typedef Pl011Params Params;
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const Params *
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params() const
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{
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return dynamic_cast<const Params *>(_params);
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}
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Pl011(const Params *p);
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virtual Tick read(PacketPtr pkt);
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virtual Tick write(PacketPtr pkt);
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/**
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* Inform the uart that there is data available.
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*/
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virtual void dataAvailable();
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/**
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* Return if we have an interrupt pending
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* @return interrupt status
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* @todo fix me when implementation improves
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*/
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virtual bool intStatus() { return false; }
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virtual void serialize(std::ostream &os);
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virtual void unserialize(Checkpoint *cp, const std::string §ion);
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};
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#endif //__DEV_ARM_PL011_H__
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