2009-04-18 16:42:29 +02:00
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---------- Begin Simulation Statistics ----------
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2009-09-24 18:30:53 +02:00
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host_inst_rate 59567 # Simulator instruction rate (inst/s)
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host_mem_usage 155776 # Number of bytes of host memory used
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host_seconds 0.09 # Real time elapsed on the host
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host_tick_rate 163592222 # Simulator tick rate (ticks/s)
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2009-04-18 16:42:29 +02:00
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sim_freq 1000000000000 # Frequency of simulated ticks
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2009-09-24 18:30:53 +02:00
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sim_insts 5049 # Number of instructions simulated
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2009-04-18 16:42:29 +02:00
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sim_seconds 0.000014 # Number of seconds simulated
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2009-09-24 18:30:53 +02:00
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sim_ticks 13914500 # Number of ticks simulated
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2009-04-18 16:42:29 +02:00
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system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
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2009-09-24 18:30:53 +02:00
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system.cpu.BPredUnit.BTBHits 552 # Number of BTB hits
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system.cpu.BPredUnit.BTBLookups 1939 # Number of BTB lookups
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2009-04-18 16:42:29 +02:00
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system.cpu.BPredUnit.RASInCorrect 53 # Number of incorrect RAS predictions.
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2009-09-24 18:30:53 +02:00
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system.cpu.BPredUnit.condIncorrect 722 # Number of conditional branches incorrect
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system.cpu.BPredUnit.condPredicted 1555 # Number of conditional branches predicted
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system.cpu.BPredUnit.lookups 2357 # Number of BP lookups
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system.cpu.BPredUnit.usedRAS 387 # Number of times the RAS was used to get a target.
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system.cpu.commit.COM:branches 885 # Number of branches committed
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2009-04-18 16:42:29 +02:00
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system.cpu.commit.COM:bw_lim_events 63 # number cycles where commit BW limit reached
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system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
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2009-09-24 18:30:53 +02:00
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system.cpu.commit.COM:committed_per_cycle::samples 14230 # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::mean 0.399438 # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::stdev 1.125719 # Number of insts commited each cycle
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2009-07-07 00:49:48 +02:00
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system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
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2009-09-24 18:30:53 +02:00
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system.cpu.commit.COM:committed_per_cycle::0-1 11753 82.59% 82.59% # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::1-2 1168 8.21% 90.80% # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::2-3 499 3.51% 94.31% # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::3-4 284 2.00% 96.30% # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::4-5 291 2.04% 98.35% # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::5-6 72 0.51% 98.85% # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::6-7 62 0.44% 99.29% # Number of insts commited each cycle
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2009-07-07 00:49:48 +02:00
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system.cpu.commit.COM:committed_per_cycle::7-8 38 0.27% 99.56% # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::8 63 0.44% 100.00% # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle
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2009-09-24 18:30:53 +02:00
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system.cpu.commit.COM:committed_per_cycle::total 14230 # Number of insts commited each cycle
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system.cpu.commit.COM:count 5684 # Number of instructions committed
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system.cpu.commit.COM:loads 1133 # Number of loads committed
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2009-04-18 16:42:29 +02:00
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system.cpu.commit.COM:membars 0 # Number of memory barriers committed
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2009-09-24 18:30:53 +02:00
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system.cpu.commit.COM:refs 2057 # Number of memory references committed
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2009-04-18 16:42:29 +02:00
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system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
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2009-09-24 18:30:53 +02:00
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system.cpu.commit.branchMispredicts 605 # The number of times a branch was mispredicted
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system.cpu.commit.commitCommittedInsts 5684 # The number of committed instructions
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2009-04-18 16:42:29 +02:00
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system.cpu.commit.commitNonSpecStalls 15 # The number of times commit has been forced to stall to communicate backwards
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2009-09-24 18:30:53 +02:00
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system.cpu.commit.commitSquashedInsts 5973 # The number of squashed insts skipped by commit
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system.cpu.committedInsts 5049 # Number of Instructions Simulated
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system.cpu.committedInsts_total 5049 # Number of Instructions Simulated
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system.cpu.cpi 5.511983 # CPI: Cycles Per Instruction
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system.cpu.cpi_total 5.511983 # CPI: Total CPI of All Threads
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system.cpu.dcache.ReadReq_accesses 2297 # number of ReadReq accesses(hits+misses)
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system.cpu.dcache.ReadReq_avg_miss_latency 34007.812500 # average ReadReq miss latency
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system.cpu.dcache.ReadReq_avg_mshr_miss_latency 36022.988506 # average ReadReq mshr miss latency
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system.cpu.dcache.ReadReq_hits 2169 # number of ReadReq hits
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system.cpu.dcache.ReadReq_miss_latency 4353000 # number of ReadReq miss cycles
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system.cpu.dcache.ReadReq_miss_rate 0.055725 # miss rate for ReadReq accesses
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system.cpu.dcache.ReadReq_misses 128 # number of ReadReq misses
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2009-04-18 16:42:29 +02:00
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system.cpu.dcache.ReadReq_mshr_hits 41 # number of ReadReq MSHR hits
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2009-09-24 18:30:53 +02:00
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system.cpu.dcache.ReadReq_mshr_miss_latency 3134000 # number of ReadReq MSHR miss cycles
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system.cpu.dcache.ReadReq_mshr_miss_rate 0.037875 # mshr miss rate for ReadReq accesses
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system.cpu.dcache.ReadReq_mshr_misses 87 # number of ReadReq MSHR misses
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2009-04-18 16:42:29 +02:00
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system.cpu.dcache.WriteReq_accesses 924 # number of WriteReq accesses(hits+misses)
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system.cpu.dcache.WriteReq_avg_miss_latency 27701.724138 # average WriteReq miss latency
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system.cpu.dcache.WriteReq_avg_mshr_miss_latency 36093.750000 # average WriteReq mshr miss latency
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system.cpu.dcache.WriteReq_hits 634 # number of WriteReq hits
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system.cpu.dcache.WriteReq_miss_latency 8033500 # number of WriteReq miss cycles
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system.cpu.dcache.WriteReq_miss_rate 0.313853 # miss rate for WriteReq accesses
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system.cpu.dcache.WriteReq_misses 290 # number of WriteReq misses
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system.cpu.dcache.WriteReq_mshr_hits 226 # number of WriteReq MSHR hits
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system.cpu.dcache.WriteReq_mshr_miss_latency 2310000 # number of WriteReq MSHR miss cycles
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system.cpu.dcache.WriteReq_mshr_miss_rate 0.069264 # mshr miss rate for WriteReq accesses
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system.cpu.dcache.WriteReq_mshr_misses 64 # number of WriteReq MSHR misses
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2009-04-22 19:25:17 +02:00
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system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
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system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
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2009-09-24 18:30:53 +02:00
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system.cpu.dcache.avg_refs 20.889706 # Average number of references to valid blocks.
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2009-04-22 19:25:17 +02:00
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system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
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system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
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system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
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system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
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2009-04-18 16:42:29 +02:00
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system.cpu.dcache.cache_copies 0 # number of cache copies performed
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2009-09-24 18:30:53 +02:00
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system.cpu.dcache.demand_accesses 3221 # number of demand (read+write) accesses
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system.cpu.dcache.demand_avg_miss_latency 29632.775120 # average overall miss latency
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system.cpu.dcache.demand_avg_mshr_miss_latency 36052.980132 # average overall mshr miss latency
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system.cpu.dcache.demand_hits 2803 # number of demand (read+write) hits
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system.cpu.dcache.demand_miss_latency 12386500 # number of demand (read+write) miss cycles
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system.cpu.dcache.demand_miss_rate 0.129773 # miss rate for demand accesses
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system.cpu.dcache.demand_misses 418 # number of demand (read+write) misses
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2009-04-18 16:42:29 +02:00
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system.cpu.dcache.demand_mshr_hits 267 # number of demand (read+write) MSHR hits
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2009-09-24 18:30:53 +02:00
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system.cpu.dcache.demand_mshr_miss_latency 5444000 # number of demand (read+write) MSHR miss cycles
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system.cpu.dcache.demand_mshr_miss_rate 0.046880 # mshr miss rate for demand accesses
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system.cpu.dcache.demand_mshr_misses 151 # number of demand (read+write) MSHR misses
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2009-04-18 16:42:29 +02:00
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system.cpu.dcache.fast_writes 0 # number of fast writes performed
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system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
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system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
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2009-09-24 18:30:53 +02:00
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system.cpu.dcache.overall_accesses 3221 # number of overall (read+write) accesses
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system.cpu.dcache.overall_avg_miss_latency 29632.775120 # average overall miss latency
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system.cpu.dcache.overall_avg_mshr_miss_latency 36052.980132 # average overall mshr miss latency
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2009-04-22 19:25:17 +02:00
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system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
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2009-09-24 18:30:53 +02:00
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system.cpu.dcache.overall_hits 2803 # number of overall hits
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system.cpu.dcache.overall_miss_latency 12386500 # number of overall miss cycles
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system.cpu.dcache.overall_miss_rate 0.129773 # miss rate for overall accesses
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system.cpu.dcache.overall_misses 418 # number of overall misses
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2009-04-18 16:42:29 +02:00
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system.cpu.dcache.overall_mshr_hits 267 # number of overall MSHR hits
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2009-09-24 18:30:53 +02:00
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system.cpu.dcache.overall_mshr_miss_latency 5444000 # number of overall MSHR miss cycles
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system.cpu.dcache.overall_mshr_miss_rate 0.046880 # mshr miss rate for overall accesses
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system.cpu.dcache.overall_mshr_misses 151 # number of overall MSHR misses
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2009-04-18 16:42:29 +02:00
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system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
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system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
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system.cpu.dcache.replacements 0 # number of replacements
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2009-09-24 18:30:53 +02:00
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system.cpu.dcache.sampled_refs 136 # Sample count of references to valid blocks.
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2009-04-18 16:42:29 +02:00
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system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
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2009-09-24 18:30:53 +02:00
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system.cpu.dcache.tagsinuse 87.690614 # Cycle average of tags in use
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system.cpu.dcache.total_refs 2841 # Total number of references to valid blocks.
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2009-04-18 16:42:29 +02:00
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system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu.dcache.writebacks 0 # number of writebacks
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system.cpu.decode.DECODE:BlockedCycles 479 # Number of cycles decode is blocked
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system.cpu.decode.DECODE:BranchMispred 128 # Number of times decode detected a branch misprediction
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system.cpu.decode.DECODE:BranchResolved 128 # Number of times decode resolved a branch
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2009-09-24 18:30:53 +02:00
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system.cpu.decode.DECODE:DecodedInsts 14211 # Number of instructions handled by decode
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system.cpu.decode.DECODE:IdleCycles 9912 # Number of cycles decode is idle
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system.cpu.decode.DECODE:RunCycles 3839 # Number of cycles decode is running
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system.cpu.decode.DECODE:SquashCycles 1056 # Number of cycles decode is squashing
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2009-04-18 16:42:29 +02:00
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system.cpu.decode.DECODE:SquashedInsts 251 # Number of squashed instructions handled by decode
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system.cpu.dtb.accesses 0 # DTB accesses
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system.cpu.dtb.hits 0 # DTB hits
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system.cpu.dtb.misses 0 # DTB misses
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system.cpu.dtb.read_accesses 0 # DTB read accesses
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system.cpu.dtb.read_hits 0 # DTB read hits
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system.cpu.dtb.read_misses 0 # DTB read misses
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system.cpu.dtb.write_accesses 0 # DTB write accesses
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system.cpu.dtb.write_hits 0 # DTB write hits
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system.cpu.dtb.write_misses 0 # DTB write misses
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2009-09-24 18:30:53 +02:00
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system.cpu.fetch.Branches 2357 # Number of branches that fetch encountered
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system.cpu.fetch.CacheLines 2171 # Number of cache lines fetched
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system.cpu.fetch.Cycles 6187 # Number of cycles fetch has run and was not squashing or blocked
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2009-04-18 16:42:29 +02:00
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system.cpu.fetch.IcacheSquashes 360 # Number of outstanding Icache misses that were squashed
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2009-09-24 18:30:53 +02:00
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system.cpu.fetch.Insts 15337 # Number of instructions fetch has processed
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system.cpu.fetch.SquashCycles 738 # Number of cycles fetch has spent squashing
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system.cpu.fetch.branchRate 0.084693 # Number of branch fetches per cycle
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system.cpu.fetch.icacheStallCycles 2171 # Number of cycles fetch is stalled on an Icache miss
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system.cpu.fetch.predictedBranches 939 # Number of branches that fetch has predicted taken
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system.cpu.fetch.rate 0.551096 # Number of inst fetches per cycle
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system.cpu.fetch.rateDist::samples 15286 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::mean 1.003336 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::stdev 2.263199 # Number of instructions fetched each cycle (Total)
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2009-07-07 00:49:48 +02:00
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system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
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2009-09-24 18:30:53 +02:00
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system.cpu.fetch.rateDist::0-1 11277 73.77% 73.77% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::1-2 1770 11.58% 85.35% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::2-3 198 1.30% 86.65% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::3-4 138 0.90% 87.55% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::4-5 316 2.07% 89.62% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::5-6 114 0.75% 90.36% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::6-7 306 2.00% 92.37% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::7-8 249 1.63% 93.99% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::8 918 6.01% 100.00% # Number of instructions fetched each cycle (Total)
|
2009-07-07 00:49:48 +02:00
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system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
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2009-09-24 18:30:53 +02:00
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system.cpu.fetch.rateDist::total 15286 # Number of instructions fetched each cycle (Total)
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system.cpu.icache.ReadReq_accesses 2171 # number of ReadReq accesses(hits+misses)
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system.cpu.icache.ReadReq_avg_miss_latency 35436.489607 # average ReadReq miss latency
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2009-04-18 16:42:29 +02:00
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system.cpu.icache.ReadReq_avg_mshr_miss_latency 34915.151515 # average ReadReq mshr miss latency
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2009-09-24 18:30:53 +02:00
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system.cpu.icache.ReadReq_hits 1738 # number of ReadReq hits
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system.cpu.icache.ReadReq_miss_latency 15344000 # number of ReadReq miss cycles
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system.cpu.icache.ReadReq_miss_rate 0.199447 # miss rate for ReadReq accesses
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system.cpu.icache.ReadReq_misses 433 # number of ReadReq misses
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system.cpu.icache.ReadReq_mshr_hits 103 # number of ReadReq MSHR hits
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2009-04-18 16:42:29 +02:00
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system.cpu.icache.ReadReq_mshr_miss_latency 11522000 # number of ReadReq MSHR miss cycles
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2009-09-24 18:30:53 +02:00
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system.cpu.icache.ReadReq_mshr_miss_rate 0.152004 # mshr miss rate for ReadReq accesses
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2009-04-18 16:42:29 +02:00
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|
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system.cpu.icache.ReadReq_mshr_misses 330 # number of ReadReq MSHR misses
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2009-04-22 19:25:17 +02:00
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system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
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system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
2009-09-24 18:30:53 +02:00
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system.cpu.icache.avg_refs 5.266667 # Average number of references to valid blocks.
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2009-04-22 19:25:17 +02:00
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system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
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system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
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system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
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system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
2009-04-18 16:42:29 +02:00
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system.cpu.icache.cache_copies 0 # number of cache copies performed
|
2009-09-24 18:30:53 +02:00
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|
|
system.cpu.icache.demand_accesses 2171 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.icache.demand_avg_miss_latency 35436.489607 # average overall miss latency
|
2009-04-18 16:42:29 +02:00
|
|
|
system.cpu.icache.demand_avg_mshr_miss_latency 34915.151515 # average overall mshr miss latency
|
2009-09-24 18:30:53 +02:00
|
|
|
system.cpu.icache.demand_hits 1738 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.icache.demand_miss_latency 15344000 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.icache.demand_miss_rate 0.199447 # miss rate for demand accesses
|
|
|
|
|
system.cpu.icache.demand_misses 433 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.icache.demand_mshr_hits 103 # number of demand (read+write) MSHR hits
|
2009-04-18 16:42:29 +02:00
|
|
|
system.cpu.icache.demand_mshr_miss_latency 11522000 # number of demand (read+write) MSHR miss cycles
|
2009-09-24 18:30:53 +02:00
|
|
|
system.cpu.icache.demand_mshr_miss_rate 0.152004 # mshr miss rate for demand accesses
|
2009-04-18 16:42:29 +02:00
|
|
|
system.cpu.icache.demand_mshr_misses 330 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
|
|
|
|
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
|
|
|
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
2009-09-24 18:30:53 +02:00
|
|
|
system.cpu.icache.overall_accesses 2171 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.icache.overall_avg_miss_latency 35436.489607 # average overall miss latency
|
2009-04-18 16:42:29 +02:00
|
|
|
system.cpu.icache.overall_avg_mshr_miss_latency 34915.151515 # average overall mshr miss latency
|
2009-04-22 19:25:17 +02:00
|
|
|
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
2009-09-24 18:30:53 +02:00
|
|
|
system.cpu.icache.overall_hits 1738 # number of overall hits
|
|
|
|
|
system.cpu.icache.overall_miss_latency 15344000 # number of overall miss cycles
|
|
|
|
|
system.cpu.icache.overall_miss_rate 0.199447 # miss rate for overall accesses
|
|
|
|
|
system.cpu.icache.overall_misses 433 # number of overall misses
|
|
|
|
|
system.cpu.icache.overall_mshr_hits 103 # number of overall MSHR hits
|
2009-04-18 16:42:29 +02:00
|
|
|
system.cpu.icache.overall_mshr_miss_latency 11522000 # number of overall MSHR miss cycles
|
2009-09-24 18:30:53 +02:00
|
|
|
system.cpu.icache.overall_mshr_miss_rate 0.152004 # mshr miss rate for overall accesses
|
2009-04-18 16:42:29 +02:00
|
|
|
system.cpu.icache.overall_mshr_misses 330 # number of overall MSHR misses
|
|
|
|
|
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
|
|
|
|
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
|
|
|
|
system.cpu.icache.replacements 16 # number of replacements
|
|
|
|
|
system.cpu.icache.sampled_refs 330 # Sample count of references to valid blocks.
|
|
|
|
|
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
2009-09-24 18:30:53 +02:00
|
|
|
system.cpu.icache.tagsinuse 159.086288 # Cycle average of tags in use
|
|
|
|
|
system.cpu.icache.total_refs 1738 # Total number of references to valid blocks.
|
2009-04-18 16:42:29 +02:00
|
|
|
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
|
|
|
system.cpu.icache.writebacks 0 # number of writebacks
|
2009-09-24 18:30:53 +02:00
|
|
|
system.cpu.idleCycles 12544 # Total number of cycles that the CPU has spent unscheduled due to idling
|
|
|
|
|
system.cpu.iew.EXEC:branches 1216 # Number of branches executed
|
|
|
|
|
system.cpu.iew.EXEC:nop 1820 # number of nop insts executed
|
|
|
|
|
system.cpu.iew.EXEC:rate 0.292239 # Inst execution rate
|
|
|
|
|
system.cpu.iew.EXEC:refs 3432 # number of memory reference insts executed
|
2009-04-18 16:42:29 +02:00
|
|
|
system.cpu.iew.EXEC:stores 1048 # Number of stores executed
|
|
|
|
|
system.cpu.iew.EXEC:swp 0 # number of swp insts executed
|
2009-09-24 18:30:53 +02:00
|
|
|
system.cpu.iew.WB:consumers 4040 # num instructions consuming a value
|
|
|
|
|
system.cpu.iew.WB:count 7355 # cumulative count of insts written-back
|
|
|
|
|
system.cpu.iew.WB:fanout 0.694802 # average fanout of values written-back
|
2009-04-18 16:42:29 +02:00
|
|
|
system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
|
|
|
|
|
system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
2009-09-24 18:30:53 +02:00
|
|
|
system.cpu.iew.WB:producers 2807 # num instructions producing a value
|
|
|
|
|
system.cpu.iew.WB:rate 0.264283 # insts written-back per cycle
|
|
|
|
|
system.cpu.iew.WB:sent 7444 # cumulative count of insts sent to commit
|
|
|
|
|
system.cpu.iew.branchMispredicts 663 # Number of branch mispredicts detected at execute
|
2009-04-18 16:42:29 +02:00
|
|
|
system.cpu.iew.iewBlockCycles 8 # Number of cycles IEW is blocking
|
2009-09-24 18:30:53 +02:00
|
|
|
system.cpu.iew.iewDispLoadInsts 2795 # Number of dispatched load instructions
|
2009-04-18 16:42:29 +02:00
|
|
|
system.cpu.iew.iewDispNonSpecInsts 15 # Number of dispatched non-speculative instructions
|
|
|
|
|
system.cpu.iew.iewDispSquashedInsts 968 # Number of squashed instructions skipped by dispatch
|
|
|
|
|
system.cpu.iew.iewDispStoreInsts 1158 # Number of dispatched store instructions
|
2009-09-24 18:30:53 +02:00
|
|
|
system.cpu.iew.iewDispatchedInsts 11660 # Number of instructions dispatched to IQ
|
|
|
|
|
system.cpu.iew.iewExecLoadInsts 2384 # Number of load instructions executed
|
2009-04-18 16:42:29 +02:00
|
|
|
system.cpu.iew.iewExecSquashedInsts 531 # Number of squashed instructions skipped in execute
|
2009-09-24 18:30:53 +02:00
|
|
|
system.cpu.iew.iewExecutedInsts 8133 # Number of executed instructions
|
2009-04-18 16:42:29 +02:00
|
|
|
system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall
|
|
|
|
|
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
|
|
|
|
system.cpu.iew.iewLSQFullEvents 1 # Number of times the LSQ has become full, causing a stall
|
2009-09-24 18:30:53 +02:00
|
|
|
system.cpu.iew.iewSquashCycles 1056 # Number of cycles IEW is squashing
|
2009-04-18 16:42:29 +02:00
|
|
|
system.cpu.iew.iewUnblockCycles 0 # Number of cycles IEW is unblocking
|
|
|
|
|
system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
|
|
|
|
system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
|
|
|
|
|
system.cpu.iew.lsq.thread.0.forwLoads 68 # Number of loads that had data forwarded from stores
|
|
|
|
|
system.cpu.iew.lsq.thread.0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed
|
|
|
|
|
system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
|
|
|
|
system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
|
|
|
|
system.cpu.iew.lsq.thread.0.memOrderViolation 22 # Number of memory ordering violations
|
|
|
|
|
system.cpu.iew.lsq.thread.0.rescheduledLoads 0 # Number of loads that were rescheduled
|
2009-09-24 18:30:53 +02:00
|
|
|
system.cpu.iew.lsq.thread.0.squashedLoads 1662 # Number of loads squashed
|
2009-04-18 16:42:29 +02:00
|
|
|
system.cpu.iew.lsq.thread.0.squashedStores 234 # Number of stores squashed
|
|
|
|
|
system.cpu.iew.memOrderViolationEvents 22 # Number of memory order violations
|
2009-09-24 18:30:53 +02:00
|
|
|
system.cpu.iew.predictedNotTakenIncorrect 277 # Number of branches that were predicted not taken incorrectly
|
|
|
|
|
system.cpu.iew.predictedTakenIncorrect 386 # Number of branches that were predicted taken incorrectly
|
|
|
|
|
system.cpu.ipc 0.181423 # IPC: Instructions Per Cycle
|
|
|
|
|
system.cpu.ipc_total 0.181423 # IPC: Total IPC of All Threads
|
2009-07-07 00:49:48 +02:00
|
|
|
system.cpu.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
|
2009-09-24 18:30:53 +02:00
|
|
|
system.cpu.iq.ISSUE:FU_type_0::IntAlu 5020 57.94% 57.94% # Type of FU issued
|
|
|
|
|
system.cpu.iq.ISSUE:FU_type_0::IntMult 5 0.06% 58.00% # Type of FU issued
|
|
|
|
|
system.cpu.iq.ISSUE:FU_type_0::IntDiv 2 0.02% 58.02% # Type of FU issued
|
|
|
|
|
system.cpu.iq.ISSUE:FU_type_0::FloatAdd 2 0.02% 58.04% # Type of FU issued
|
|
|
|
|
system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 58.04% # Type of FU issued
|
|
|
|
|
system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 58.04% # Type of FU issued
|
|
|
|
|
system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 58.04% # Type of FU issued
|
|
|
|
|
system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 58.04% # Type of FU issued
|
|
|
|
|
system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 58.04% # Type of FU issued
|
|
|
|
|
system.cpu.iq.ISSUE:FU_type_0::MemRead 2572 29.69% 87.73% # Type of FU issued
|
|
|
|
|
system.cpu.iq.ISSUE:FU_type_0::MemWrite 1063 12.27% 100.00% # Type of FU issued
|
2009-07-07 00:49:48 +02:00
|
|
|
system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
|
|
|
|
system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
2009-09-24 18:30:53 +02:00
|
|
|
system.cpu.iq.ISSUE:FU_type_0::total 8664 # Type of FU issued
|
2009-04-18 16:42:29 +02:00
|
|
|
system.cpu.iq.ISSUE:fu_busy_cnt 162 # FU busy when requested
|
2009-09-24 18:30:53 +02:00
|
|
|
system.cpu.iq.ISSUE:fu_busy_rate 0.018698 # FU busy rate (busy events/executed inst)
|
2009-07-07 00:49:48 +02:00
|
|
|
system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.ISSUE:fu_full::IntAlu 10 6.17% 6.17% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 6.17% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 6.17% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 6.17% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 6.17% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 6.17% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 6.17% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 6.17% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 6.17% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.ISSUE:fu_full::MemRead 98 60.49% 66.67% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.ISSUE:fu_full::MemWrite 54 33.33% 100.00% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
2009-09-24 18:30:53 +02:00
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle::samples 15286 # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle::mean 0.566793 # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.217668 # Number of insts issued each cycle
|
2009-07-07 00:49:48 +02:00
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
2009-09-24 18:30:53 +02:00
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle::0-1 11421 74.72% 74.72% # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle::1-2 1678 10.98% 85.69% # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle::2-3 792 5.18% 90.87% # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle::3-4 722 4.72% 95.60% # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle::4-5 333 2.18% 97.78% # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle::5-6 200 1.31% 99.08% # Number of insts issued each cycle
|
2009-07-07 00:49:48 +02:00
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle::6-7 91 0.60% 99.68% # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle::7-8 34 0.22% 99.90% # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle::8 15 0.10% 100.00% # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
2009-09-24 18:30:53 +02:00
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle::total 15286 # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.ISSUE:rate 0.311319 # Inst issue rate
|
|
|
|
|
system.cpu.iq.iqInstsAdded 9825 # Number of instructions added to the IQ (excludes non-spec)
|
|
|
|
|
system.cpu.iq.iqInstsIssued 8664 # Number of instructions issued
|
2009-04-18 16:42:29 +02:00
|
|
|
system.cpu.iq.iqNonSpecInstsAdded 15 # Number of non-speculative instructions added to the IQ
|
2009-09-24 18:30:53 +02:00
|
|
|
system.cpu.iq.iqSquashedInstsExamined 4207 # Number of squashed instructions iterated over during squash; mainly for profiling
|
2009-04-18 16:42:29 +02:00
|
|
|
system.cpu.iq.iqSquashedInstsIssued 30 # Number of squashed instructions issued
|
2009-09-24 18:30:53 +02:00
|
|
|
system.cpu.iq.iqSquashedOperandsExamined 2761 # Number of squashed operands that are examined and possibly removed from graph
|
2009-04-18 16:42:29 +02:00
|
|
|
system.cpu.itb.accesses 0 # DTB accesses
|
|
|
|
|
system.cpu.itb.hits 0 # DTB hits
|
|
|
|
|
system.cpu.itb.misses 0 # DTB misses
|
|
|
|
|
system.cpu.itb.read_accesses 0 # DTB read accesses
|
|
|
|
|
system.cpu.itb.read_hits 0 # DTB read hits
|
|
|
|
|
system.cpu.itb.read_misses 0 # DTB read misses
|
|
|
|
|
system.cpu.itb.write_accesses 0 # DTB write accesses
|
|
|
|
|
system.cpu.itb.write_hits 0 # DTB write hits
|
|
|
|
|
system.cpu.itb.write_misses 0 # DTB write misses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_accesses 49 # number of ReadExReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency 34704.081633 # average ReadExReq miss latency
|
|
|
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31408.163265 # average ReadExReq mshr miss latency
|
|
|
|
|
system.cpu.l2cache.ReadExReq_miss_latency 1700500 # number of ReadExReq miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_misses 49 # number of ReadExReq misses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency 1539000 # number of ReadExReq MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_mshr_misses 49 # number of ReadExReq MSHR misses
|
2009-09-24 18:30:53 +02:00
|
|
|
system.cpu.l2cache.ReadReq_accesses 417 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency 34307.506053 # average ReadReq miss latency
|
|
|
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31130.750605 # average ReadReq mshr miss latency
|
2009-04-18 16:42:29 +02:00
|
|
|
system.cpu.l2cache.ReadReq_hits 4 # number of ReadReq hits
|
2009-09-24 18:30:53 +02:00
|
|
|
system.cpu.l2cache.ReadReq_miss_latency 14169000 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadReq_miss_rate 0.990408 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_misses 413 # number of ReadReq misses
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency 12857000 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.990408 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_misses 413 # number of ReadReq MSHR misses
|
2009-04-18 16:42:29 +02:00
|
|
|
system.cpu.l2cache.UpgradeReq_accesses 15 # number of UpgradeReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_avg_miss_latency 34400 # average UpgradeReq miss latency
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31166.666667 # average UpgradeReq mshr miss latency
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_miss_latency 516000 # number of UpgradeReq miss cycles
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_misses 15 # number of UpgradeReq misses
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 467500 # number of UpgradeReq MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_mshr_misses 15 # number of UpgradeReq MSHR misses
|
2009-04-22 19:25:17 +02:00
|
|
|
system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
2009-09-24 18:30:53 +02:00
|
|
|
system.cpu.l2cache.avg_refs 0.010050 # Average number of references to valid blocks.
|
2009-04-22 19:25:17 +02:00
|
|
|
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
2009-04-18 16:42:29 +02:00
|
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
2009-09-24 18:30:53 +02:00
|
|
|
system.cpu.l2cache.demand_accesses 466 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.demand_avg_miss_latency 34349.567100 # average overall miss latency
|
|
|
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency 31160.173160 # average overall mshr miss latency
|
2009-04-18 16:42:29 +02:00
|
|
|
system.cpu.l2cache.demand_hits 4 # number of demand (read+write) hits
|
2009-09-24 18:30:53 +02:00
|
|
|
system.cpu.l2cache.demand_miss_latency 15869500 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_miss_rate 0.991416 # miss rate for demand accesses
|
|
|
|
|
system.cpu.l2cache.demand_misses 462 # number of demand (read+write) misses
|
2009-04-18 16:42:29 +02:00
|
|
|
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
2009-09-24 18:30:53 +02:00
|
|
|
system.cpu.l2cache.demand_mshr_miss_latency 14396000 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_mshr_miss_rate 0.991416 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.l2cache.demand_mshr_misses 462 # number of demand (read+write) MSHR misses
|
2009-04-18 16:42:29 +02:00
|
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
|
|
|
|
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
|
|
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
2009-09-24 18:30:53 +02:00
|
|
|
system.cpu.l2cache.overall_accesses 466 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.overall_avg_miss_latency 34349.567100 # average overall miss latency
|
|
|
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency 31160.173160 # average overall mshr miss latency
|
2009-04-22 19:25:17 +02:00
|
|
|
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
2009-04-18 16:42:29 +02:00
|
|
|
system.cpu.l2cache.overall_hits 4 # number of overall hits
|
2009-09-24 18:30:53 +02:00
|
|
|
system.cpu.l2cache.overall_miss_latency 15869500 # number of overall miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_miss_rate 0.991416 # miss rate for overall accesses
|
|
|
|
|
system.cpu.l2cache.overall_misses 462 # number of overall misses
|
2009-04-18 16:42:29 +02:00
|
|
|
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
2009-09-24 18:30:53 +02:00
|
|
|
system.cpu.l2cache.overall_mshr_miss_latency 14396000 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_mshr_miss_rate 0.991416 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.l2cache.overall_mshr_misses 462 # number of overall MSHR misses
|
2009-04-18 16:42:29 +02:00
|
|
|
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
|
|
|
|
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
|
|
|
|
system.cpu.l2cache.replacements 0 # number of replacements
|
2009-09-24 18:30:53 +02:00
|
|
|
system.cpu.l2cache.sampled_refs 398 # Sample count of references to valid blocks.
|
2009-04-18 16:42:29 +02:00
|
|
|
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
2009-09-24 18:30:53 +02:00
|
|
|
system.cpu.l2cache.tagsinuse 209.158769 # Cycle average of tags in use
|
2009-04-18 16:42:29 +02:00
|
|
|
system.cpu.l2cache.total_refs 4 # Total number of references to valid blocks.
|
|
|
|
|
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
|
|
|
system.cpu.l2cache.writebacks 0 # number of writebacks
|
|
|
|
|
system.cpu.memDep0.conflictingLoads 5 # Number of conflicting loads.
|
|
|
|
|
system.cpu.memDep0.conflictingStores 2 # Number of conflicting stores.
|
2009-09-24 18:30:53 +02:00
|
|
|
system.cpu.memDep0.insertedLoads 2795 # Number of loads inserted to the mem dependence unit.
|
2009-04-18 16:42:29 +02:00
|
|
|
system.cpu.memDep0.insertedStores 1158 # Number of stores inserted to the mem dependence unit.
|
2009-09-24 18:30:53 +02:00
|
|
|
system.cpu.numCycles 27830 # number of cpu cycles simulated
|
2009-04-18 16:42:29 +02:00
|
|
|
system.cpu.rename.RENAME:BlockCycles 20 # Number of cycles rename is blocking
|
2009-09-24 18:30:53 +02:00
|
|
|
system.cpu.rename.RENAME:CommittedMaps 3323 # Number of HB maps that are committed
|
|
|
|
|
system.cpu.rename.RENAME:IdleCycles 10291 # Number of cycles rename is idle
|
2009-04-18 16:42:29 +02:00
|
|
|
system.cpu.rename.RENAME:LSQFullEvents 16 # Number of times rename has blocked due to LSQ full
|
2009-09-24 18:30:53 +02:00
|
|
|
system.cpu.rename.RENAME:RenameLookups 15666 # Number of register rename lookups that rename has made
|
|
|
|
|
system.cpu.rename.RENAME:RenamedInsts 13454 # Number of instructions processed by rename
|
|
|
|
|
system.cpu.rename.RENAME:RenamedOperands 8251 # Number of destination operands rename has renamed
|
|
|
|
|
system.cpu.rename.RENAME:RunCycles 3462 # Number of cycles rename is running
|
|
|
|
|
system.cpu.rename.RENAME:SquashCycles 1056 # Number of cycles rename is squashing
|
2009-04-18 16:42:29 +02:00
|
|
|
system.cpu.rename.RENAME:UnblockCycles 29 # Number of cycles rename is unblocking
|
2009-09-24 18:30:53 +02:00
|
|
|
system.cpu.rename.RENAME:UndoneMaps 4928 # Number of HB maps that are undone due to squashing
|
2009-04-18 16:42:29 +02:00
|
|
|
system.cpu.rename.RENAME:serializeStallCycles 428 # count of cycles rename stalled for serializing inst
|
|
|
|
|
system.cpu.rename.RENAME:serializingInsts 20 # count of serializing insts renamed
|
|
|
|
|
system.cpu.rename.RENAME:skidInsts 125 # count of insts added to the skid buffer
|
|
|
|
|
system.cpu.rename.RENAME:tempSerializingInsts 14 # count of temporary serializing insts renamed
|
2009-09-24 18:30:53 +02:00
|
|
|
system.cpu.timesIdled 250 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
2009-04-18 16:42:29 +02:00
|
|
|
system.cpu.workload.PROG:num_syscalls 13 # Number of system calls
|
|
|
|
|
|
|
|
|
|
---------- End Simulation Statistics ----------
|
