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gem5/tests/quick/50.memtest/ref/alpha/linux/memtest/config.out

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Add short memtest run to quick regressions. Caveats: - Even though memtest is ISA-independent, it will only run for the Alpha builds, since there's no way to specify ISA-independent reference files and I didn't want to commit 3 copies since I'm not sure we want to run it for all the different ISAs anyway. - Reference outputs were generated on my laptop, so performance numbers will be low compared to zizzer. --HG-- extra : convert_revision : 210fe4abecc19fbab0b15402c6cb4863650bab66
2007-02-07 06:16:33 +01:00
[root]
type=Root
Update refs for new CPU frequency changes. tests/quick/00.hello/ref/alpha/linux/o3-timing/config.ini: tests/quick/00.hello/ref/alpha/linux/o3-timing/config.out: tests/quick/00.hello/ref/alpha/linux/o3-timing/m5stats.txt: tests/quick/00.hello/ref/alpha/linux/o3-timing/stderr: tests/quick/00.hello/ref/alpha/linux/o3-timing/stdout: tests/quick/00.hello/ref/alpha/linux/simple-atomic/config.ini: tests/quick/00.hello/ref/alpha/linux/simple-atomic/config.out: tests/quick/00.hello/ref/alpha/linux/simple-atomic/m5stats.txt: tests/quick/00.hello/ref/alpha/linux/simple-atomic/stderr: tests/quick/00.hello/ref/alpha/linux/simple-atomic/stdout: tests/quick/00.hello/ref/alpha/linux/simple-timing/config.ini: tests/quick/00.hello/ref/alpha/linux/simple-timing/config.out: tests/quick/00.hello/ref/alpha/linux/simple-timing/m5stats.txt: tests/quick/00.hello/ref/alpha/linux/simple-timing/stderr: tests/quick/00.hello/ref/alpha/linux/simple-timing/stdout: tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.ini: tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.out: tests/quick/00.hello/ref/alpha/tru64/o3-timing/m5stats.txt: tests/quick/00.hello/ref/alpha/tru64/o3-timing/stdout: tests/quick/00.hello/ref/alpha/tru64/simple-atomic/config.ini: tests/quick/00.hello/ref/alpha/tru64/simple-atomic/config.out: tests/quick/00.hello/ref/alpha/tru64/simple-atomic/m5stats.txt: tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stderr: tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stdout: tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.ini: tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.out: tests/quick/00.hello/ref/alpha/tru64/simple-timing/m5stats.txt: tests/quick/00.hello/ref/alpha/tru64/simple-timing/stderr: tests/quick/00.hello/ref/alpha/tru64/simple-timing/stdout: tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini: tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.out: tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/m5stats.txt: tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stderr: tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stdout: tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/config.ini: tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/config.out: tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/m5stats.txt: tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/stdout: tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.ini: tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.out: tests/quick/20.eio-short/ref/alpha/eio/simple-timing/m5stats.txt: tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stdout: tests/quick/50.memtest/ref/alpha/linux/memtest/config.ini: tests/quick/50.memtest/ref/alpha/linux/memtest/config.out: tests/quick/50.memtest/ref/alpha/linux/memtest/m5stats.txt: tests/quick/50.memtest/ref/alpha/linux/memtest/stdout: Update refs --HG-- extra : convert_revision : 8d9deb2b907843064b40e46207d9c9361941f022
2007-04-22 20:50:37 +02:00
dummy=0
Add short memtest run to quick regressions. Caveats: - Even though memtest is ISA-independent, it will only run for the Alpha builds, since there's no way to specify ISA-independent reference files and I didn't want to commit 3 copies since I'm not sure we want to run it for all the different ISAs anyway. - Reference outputs were generated on my laptop, so performance numbers will be low compared to zizzer. --HG-- extra : convert_revision : 210fe4abecc19fbab0b15402c6cb4863650bab66
2007-02-07 06:16:33 +01:00
[system.physmem]
type=PhysicalMemory
file=
range=[0,134217727]
latency=1
zero=false
[system]
type=System
physmem=system.physmem
mem_mode=timing
[system.membus]
type=Bus
bus_id=0
clock=2
width=16
responder_set=false
[system.l2c]
type=BaseCache
size=65536
assoc=8
block_size=64
latency=10
mshrs=92
tgts_per_mshr=16
write_buffers=8
prioritizeRequests=false
protocol=null
trace_addr=0
hash_delay=1
repl=null
compressed_bus=false
store_compressed=false
adaptive_compression=false
compression_latency=0
block_size=64
max_miss_count=0
addr_range=[0,18446744073709551615]
split=false
split_size=0
lifo=false
two_queue=false
prefetch_miss=false
prefetch_access=false
prefetcher_size=100
prefetch_past_page=false
prefetch_serial_squash=false
prefetch_latency=10
prefetch_degree=1
prefetch_policy=none
prefetch_cache_check_push=true
prefetch_use_cpu_id=true
prefetch_data_accesses_only=false
hit_latency=1
[system.cpu6]
type=MemTest
memory_size=65536
percent_reads=65
percent_functional=50
percent_uncacheable=10
progress_interval=10000
percent_source_unaligned=50
percent_dest_unaligned=50
trace_addr=0
max_loads=100000
atomic=false
[system.cpu6.l1c.protocol]
type=CoherenceProtocol
protocol=moesi
do_upgrades=true
[system.cpu6.l1c]
type=BaseCache
size=32768
assoc=4
block_size=64
latency=1
mshrs=12
tgts_per_mshr=8
write_buffers=8
prioritizeRequests=false
protocol=system.cpu6.l1c.protocol
trace_addr=0
hash_delay=1
repl=null
compressed_bus=false
store_compressed=false
adaptive_compression=false
compression_latency=0
block_size=64
max_miss_count=0
addr_range=[0,18446744073709551615]
split=false
split_size=0
lifo=false
two_queue=false
prefetch_miss=false
prefetch_access=false
prefetcher_size=100
prefetch_past_page=false
prefetch_serial_squash=false
prefetch_latency=10
prefetch_degree=1
prefetch_policy=none
prefetch_cache_check_push=true
prefetch_use_cpu_id=true
prefetch_data_accesses_only=false
hit_latency=1
[system.cpu4]
type=MemTest
memory_size=65536
percent_reads=65
percent_functional=50
percent_uncacheable=10
progress_interval=10000
percent_source_unaligned=50
percent_dest_unaligned=50
trace_addr=0
max_loads=100000
atomic=false
[system.cpu4.l1c.protocol]
type=CoherenceProtocol
protocol=moesi
do_upgrades=true
[system.cpu4.l1c]
type=BaseCache
size=32768
assoc=4
block_size=64
latency=1
mshrs=12
tgts_per_mshr=8
write_buffers=8
prioritizeRequests=false
protocol=system.cpu4.l1c.protocol
trace_addr=0
hash_delay=1
repl=null
compressed_bus=false
store_compressed=false
adaptive_compression=false
compression_latency=0
block_size=64
max_miss_count=0
addr_range=[0,18446744073709551615]
split=false
split_size=0
lifo=false
two_queue=false
prefetch_miss=false
prefetch_access=false
prefetcher_size=100
prefetch_past_page=false
prefetch_serial_squash=false
prefetch_latency=10
prefetch_degree=1
prefetch_policy=none
prefetch_cache_check_push=true
prefetch_use_cpu_id=true
prefetch_data_accesses_only=false
hit_latency=1
[system.cpu5]
type=MemTest
memory_size=65536
percent_reads=65
percent_functional=50
percent_uncacheable=10
progress_interval=10000
percent_source_unaligned=50
percent_dest_unaligned=50
trace_addr=0
max_loads=100000
atomic=false
[system.cpu5.l1c.protocol]
type=CoherenceProtocol
protocol=moesi
do_upgrades=true
[system.cpu5.l1c]
type=BaseCache
size=32768
assoc=4
block_size=64
latency=1
mshrs=12
tgts_per_mshr=8
write_buffers=8
prioritizeRequests=false
protocol=system.cpu5.l1c.protocol
trace_addr=0
hash_delay=1
repl=null
compressed_bus=false
store_compressed=false
adaptive_compression=false
compression_latency=0
block_size=64
max_miss_count=0
addr_range=[0,18446744073709551615]
split=false
split_size=0
lifo=false
two_queue=false
prefetch_miss=false
prefetch_access=false
prefetcher_size=100
prefetch_past_page=false
prefetch_serial_squash=false
prefetch_latency=10
prefetch_degree=1
prefetch_policy=none
prefetch_cache_check_push=true
prefetch_use_cpu_id=true
prefetch_data_accesses_only=false
hit_latency=1
[system.cpu2]
type=MemTest
memory_size=65536
percent_reads=65
percent_functional=50
percent_uncacheable=10
progress_interval=10000
percent_source_unaligned=50
percent_dest_unaligned=50
trace_addr=0
max_loads=100000
atomic=false
[system.cpu2.l1c.protocol]
type=CoherenceProtocol
protocol=moesi
do_upgrades=true
[system.cpu2.l1c]
type=BaseCache
size=32768
assoc=4
block_size=64
latency=1
mshrs=12
tgts_per_mshr=8
write_buffers=8
prioritizeRequests=false
protocol=system.cpu2.l1c.protocol
trace_addr=0
hash_delay=1
repl=null
compressed_bus=false
store_compressed=false
adaptive_compression=false
compression_latency=0
block_size=64
max_miss_count=0
addr_range=[0,18446744073709551615]
split=false
split_size=0
lifo=false
two_queue=false
prefetch_miss=false
prefetch_access=false
prefetcher_size=100
prefetch_past_page=false
prefetch_serial_squash=false
prefetch_latency=10
prefetch_degree=1
prefetch_policy=none
prefetch_cache_check_push=true
prefetch_use_cpu_id=true
prefetch_data_accesses_only=false
hit_latency=1
[system.cpu3]
type=MemTest
memory_size=65536
percent_reads=65
percent_functional=50
percent_uncacheable=10
progress_interval=10000
percent_source_unaligned=50
percent_dest_unaligned=50
trace_addr=0
max_loads=100000
atomic=false
[system.cpu3.l1c.protocol]
type=CoherenceProtocol
protocol=moesi
do_upgrades=true
[system.cpu3.l1c]
type=BaseCache
size=32768
assoc=4
block_size=64
latency=1
mshrs=12
tgts_per_mshr=8
write_buffers=8
prioritizeRequests=false
protocol=system.cpu3.l1c.protocol
trace_addr=0
hash_delay=1
repl=null
compressed_bus=false
store_compressed=false
adaptive_compression=false
compression_latency=0
block_size=64
max_miss_count=0
addr_range=[0,18446744073709551615]
split=false
split_size=0
lifo=false
two_queue=false
prefetch_miss=false
prefetch_access=false
prefetcher_size=100
prefetch_past_page=false
prefetch_serial_squash=false
prefetch_latency=10
prefetch_degree=1
prefetch_policy=none
prefetch_cache_check_push=true
prefetch_use_cpu_id=true
prefetch_data_accesses_only=false
hit_latency=1
[system.cpu0]
type=MemTest
memory_size=65536
percent_reads=65
percent_functional=50
percent_uncacheable=10
progress_interval=10000
percent_source_unaligned=50
percent_dest_unaligned=50
trace_addr=0
max_loads=100000
atomic=false
[system.cpu0.l1c.protocol]
type=CoherenceProtocol
protocol=moesi
do_upgrades=true
[system.cpu0.l1c]
type=BaseCache
size=32768
assoc=4
block_size=64
latency=1
mshrs=12
tgts_per_mshr=8
write_buffers=8
prioritizeRequests=false
protocol=system.cpu0.l1c.protocol
trace_addr=0
hash_delay=1
repl=null
compressed_bus=false
store_compressed=false
adaptive_compression=false
compression_latency=0
block_size=64
max_miss_count=0
addr_range=[0,18446744073709551615]
split=false
split_size=0
lifo=false
two_queue=false
prefetch_miss=false
prefetch_access=false
prefetcher_size=100
prefetch_past_page=false
prefetch_serial_squash=false
prefetch_latency=10
prefetch_degree=1
prefetch_policy=none
prefetch_cache_check_push=true
prefetch_use_cpu_id=true
prefetch_data_accesses_only=false
hit_latency=1
[system.cpu1]
type=MemTest
memory_size=65536
percent_reads=65
percent_functional=50
percent_uncacheable=10
progress_interval=10000
percent_source_unaligned=50
percent_dest_unaligned=50
trace_addr=0
max_loads=100000
atomic=false
[system.cpu1.l1c.protocol]
type=CoherenceProtocol
protocol=moesi
do_upgrades=true
[system.cpu1.l1c]
type=BaseCache
size=32768
assoc=4
block_size=64
latency=1
mshrs=12
tgts_per_mshr=8
write_buffers=8
prioritizeRequests=false
protocol=system.cpu1.l1c.protocol
trace_addr=0
hash_delay=1
repl=null
compressed_bus=false
store_compressed=false
adaptive_compression=false
compression_latency=0
block_size=64
max_miss_count=0
addr_range=[0,18446744073709551615]
split=false
split_size=0
lifo=false
two_queue=false
prefetch_miss=false
prefetch_access=false
prefetcher_size=100
prefetch_past_page=false
prefetch_serial_squash=false
prefetch_latency=10
prefetch_degree=1
prefetch_policy=none
prefetch_cache_check_push=true
prefetch_use_cpu_id=true
prefetch_data_accesses_only=false
hit_latency=1
[system.funcmem]
type=PhysicalMemory
file=
range=[0,134217727]
latency=1
zero=false
[system.cpu7]
type=MemTest
memory_size=65536
percent_reads=65
percent_functional=50
percent_uncacheable=10
progress_interval=10000
percent_source_unaligned=50
percent_dest_unaligned=50
trace_addr=0
max_loads=100000
atomic=false
[system.cpu7.l1c.protocol]
type=CoherenceProtocol
protocol=moesi
do_upgrades=true
[system.cpu7.l1c]
type=BaseCache
size=32768
assoc=4
block_size=64
latency=1
mshrs=12
tgts_per_mshr=8
write_buffers=8
prioritizeRequests=false
protocol=system.cpu7.l1c.protocol
trace_addr=0
hash_delay=1
repl=null
compressed_bus=false
store_compressed=false
adaptive_compression=false
compression_latency=0
block_size=64
max_miss_count=0
addr_range=[0,18446744073709551615]
split=false
split_size=0
lifo=false
two_queue=false
prefetch_miss=false
prefetch_access=false
prefetcher_size=100
prefetch_past_page=false
prefetch_serial_squash=false
prefetch_latency=10
prefetch_degree=1
prefetch_policy=none
prefetch_cache_check_push=true
prefetch_use_cpu_id=true
prefetch_data_accesses_only=false
hit_latency=1
[system.toL2Bus]
type=Bus
bus_id=0
clock=2
width=16
responder_set=false
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