39 lines
1.4 KiB
Text
39 lines
1.4 KiB
Text
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simobj BaseCPU(SimObject):
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abstract = True
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icache = Param.BaseMem(NULL, "L1 instruction cache object")
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dcache = Param.BaseMem(NULL, "L1 data cache object")
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dtb = Param.AlphaDTB("Data TLB")
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itb = Param.AlphaITB("Instruction TLB")
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mem = Param.FunctionalMemory("memory")
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system = Param.BaseSystem(Super, "system object")
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workload = VectorParam.Process("processes to run")
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max_insts_all_threads = Param.Counter(0,
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"terminate when all threads have reached this inst count")
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max_insts_any_thread = Param.Counter(0,
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"terminate when any thread reaches this inst count")
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max_loads_all_threads = Param.Counter(0,
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"terminate when all threads have reached this load count")
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max_loads_any_thread = Param.Counter(0,
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"terminate when any thread reaches this load count")
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defer_registration = Param.Bool(false,
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"defer registration with system (for sampling)")
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def check(self):
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has_workload = self._hasvalue('workload')
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has_dtb = self._hasvalue('dtb')
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has_itb = self._hasvalue('itb')
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has_mem = self._hasvalue('mem')
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has_system = self._hasvalue('system')
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if has_workload:
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self.dtb.disable = True
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self.itb.disable = True
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self.mem.disable = True
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self.system.disable = True
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if has_dtb or has_itb or has_mem or has_system:
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self.workload.disable = True
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