2007-03-05 18:56:26 +01:00
|
|
|
/*
|
arm: remote GDB: rationalize structure of register offsets
Currently, the wire format of register values in g- and G-packets is
modelled using a union of uint8/16/32/64 arrays. The offset positions
of each register are expressed as a "register count" scaled according
to the width of the register in question. This results in counter-
intuitive and error-prone "register count arithmetic", and some
formats would even be altogether unrepresentable in such model, e.g.
a 64-bit register following a 32-bit one would have a fractional index
in the regs64 array.
Another difficulty is that the array is allocated before the actual
architecture of the workload is known (and therefore before the correct
size for the array can be calculated).
With this patch I propose a simpler mechanism for expressing the
register set structure. In the new code, GdbRegCache is an abstract
class; its subclasses contain straightforward structs reflecting the
register representation. The determination whether to use e.g. the
AArch32 vs. AArch64 register set (or SPARCv8 vs SPARCv9, etc.) is made
by polymorphically dispatching getregs() to the concrete subclass.
The subclass is not instantiated until it is needed for actual
g-/G-packet processing, when the mode is already known.
This patch is not meant to be merged in on its own, because it changes
the contract between src/base/remote_gdb.* and src/arch/*/remote_gdb.*,
so as it stands right now, it would break the other architectures.
In this patch only the base and the ARM code are provided for review;
once we agree on the structure, I will provide src/arch/*/remote_gdb.*
for the other architectures; those patches could then be merged in
together.
Review Request: http://reviews.gem5.org/r/3207/
Pushed by Joel Hestness <jthestness@gmail.com>
2015-12-18 22:12:07 +01:00
|
|
|
* Copyright 2015 LabWare
|
2014-12-06 07:36:16 +01:00
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* Copyright 2014 Google, Inc.
|
2007-03-05 18:56:26 +01:00
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* Copyright (c) 2007 The Hewlett-Packard Development Company
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* All rights reserved.
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*
|
2010-05-24 07:44:15 +02:00
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
|
2007-03-05 18:56:26 +01:00
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*
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2010-05-24 07:44:15 +02:00
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
|
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
|
2007-03-05 18:56:26 +01:00
|
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|
* contributors may be used to endorse or promote products derived from
|
2010-05-24 07:44:15 +02:00
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* this software without specific prior written permission.
|
2007-03-05 18:56:26 +01:00
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Gabe Black
|
arm: remote GDB: rationalize structure of register offsets
Currently, the wire format of register values in g- and G-packets is
modelled using a union of uint8/16/32/64 arrays. The offset positions
of each register are expressed as a "register count" scaled according
to the width of the register in question. This results in counter-
intuitive and error-prone "register count arithmetic", and some
formats would even be altogether unrepresentable in such model, e.g.
a 64-bit register following a 32-bit one would have a fractional index
in the regs64 array.
Another difficulty is that the array is allocated before the actual
architecture of the workload is known (and therefore before the correct
size for the array can be calculated).
With this patch I propose a simpler mechanism for expressing the
register set structure. In the new code, GdbRegCache is an abstract
class; its subclasses contain straightforward structs reflecting the
register representation. The determination whether to use e.g. the
AArch32 vs. AArch64 register set (or SPARCv8 vs SPARCv9, etc.) is made
by polymorphically dispatching getregs() to the concrete subclass.
The subclass is not instantiated until it is needed for actual
g-/G-packet processing, when the mode is already known.
This patch is not meant to be merged in on its own, because it changes
the contract between src/base/remote_gdb.* and src/arch/*/remote_gdb.*,
so as it stands right now, it would break the other architectures.
In this patch only the base and the ARM code are provided for review;
once we agree on the structure, I will provide src/arch/*/remote_gdb.*
for the other architectures; those patches could then be merged in
together.
Review Request: http://reviews.gem5.org/r/3207/
Pushed by Joel Hestness <jthestness@gmail.com>
2015-12-18 22:12:07 +01:00
|
|
|
* Boris Shingarov
|
2007-03-05 18:56:26 +01:00
|
|
|
*/
|
|
|
|
|
|
2016-11-09 21:27:37 +01:00
|
|
|
#include "arch/x86/remote_gdb.hh"
|
|
|
|
|
|
2007-03-05 18:56:26 +01:00
|
|
|
#include <sys/signal.h>
|
2011-04-15 19:44:06 +02:00
|
|
|
#include <unistd.h>
|
2007-03-05 18:56:26 +01:00
|
|
|
|
|
|
|
|
#include <string>
|
|
|
|
|
|
2016-11-09 21:27:37 +01:00
|
|
|
#include "arch/vtophys.hh"
|
2014-12-06 07:36:16 +01:00
|
|
|
#include "arch/x86/pagetable_walker.hh"
|
|
|
|
|
#include "arch/x86/process.hh"
|
2016-11-09 21:27:37 +01:00
|
|
|
#include "arch/x86/regs/int.hh"
|
|
|
|
|
#include "arch/x86/regs/misc.hh"
|
2007-03-05 18:56:26 +01:00
|
|
|
#include "base/remote_gdb.hh"
|
|
|
|
|
#include "base/socket.hh"
|
|
|
|
|
#include "base/trace.hh"
|
2014-12-06 07:36:16 +01:00
|
|
|
#include "cpu/base.hh"
|
2007-03-05 18:56:26 +01:00
|
|
|
#include "cpu/thread_context.hh"
|
arm: remote GDB: rationalize structure of register offsets
Currently, the wire format of register values in g- and G-packets is
modelled using a union of uint8/16/32/64 arrays. The offset positions
of each register are expressed as a "register count" scaled according
to the width of the register in question. This results in counter-
intuitive and error-prone "register count arithmetic", and some
formats would even be altogether unrepresentable in such model, e.g.
a 64-bit register following a 32-bit one would have a fractional index
in the regs64 array.
Another difficulty is that the array is allocated before the actual
architecture of the workload is known (and therefore before the correct
size for the array can be calculated).
With this patch I propose a simpler mechanism for expressing the
register set structure. In the new code, GdbRegCache is an abstract
class; its subclasses contain straightforward structs reflecting the
register representation. The determination whether to use e.g. the
AArch32 vs. AArch64 register set (or SPARCv8 vs SPARCv9, etc.) is made
by polymorphically dispatching getregs() to the concrete subclass.
The subclass is not instantiated until it is needed for actual
g-/G-packet processing, when the mode is already known.
This patch is not meant to be merged in on its own, because it changes
the contract between src/base/remote_gdb.* and src/arch/*/remote_gdb.*,
so as it stands right now, it would break the other architectures.
In this patch only the base and the ARM code are provided for review;
once we agree on the structure, I will provide src/arch/*/remote_gdb.*
for the other architectures; those patches could then be merged in
together.
Review Request: http://reviews.gem5.org/r/3207/
Pushed by Joel Hestness <jthestness@gmail.com>
2015-12-18 22:12:07 +01:00
|
|
|
#include "debug/GDBAcc.hh"
|
2014-12-06 07:36:16 +01:00
|
|
|
#include "mem/page_table.hh"
|
|
|
|
|
#include "sim/full_system.hh"
|
2007-03-05 18:56:26 +01:00
|
|
|
|
|
|
|
|
using namespace std;
|
2008-09-28 06:03:46 +02:00
|
|
|
using namespace X86ISA;
|
2007-03-05 18:56:26 +01:00
|
|
|
|
2014-12-06 07:36:16 +01:00
|
|
|
RemoteGDB::RemoteGDB(System *_system, ThreadContext *c) :
|
arm: remote GDB: rationalize structure of register offsets
Currently, the wire format of register values in g- and G-packets is
modelled using a union of uint8/16/32/64 arrays. The offset positions
of each register are expressed as a "register count" scaled according
to the width of the register in question. This results in counter-
intuitive and error-prone "register count arithmetic", and some
formats would even be altogether unrepresentable in such model, e.g.
a 64-bit register following a 32-bit one would have a fractional index
in the regs64 array.
Another difficulty is that the array is allocated before the actual
architecture of the workload is known (and therefore before the correct
size for the array can be calculated).
With this patch I propose a simpler mechanism for expressing the
register set structure. In the new code, GdbRegCache is an abstract
class; its subclasses contain straightforward structs reflecting the
register representation. The determination whether to use e.g. the
AArch32 vs. AArch64 register set (or SPARCv8 vs SPARCv9, etc.) is made
by polymorphically dispatching getregs() to the concrete subclass.
The subclass is not instantiated until it is needed for actual
g-/G-packet processing, when the mode is already known.
This patch is not meant to be merged in on its own, because it changes
the contract between src/base/remote_gdb.* and src/arch/*/remote_gdb.*,
so as it stands right now, it would break the other architectures.
In this patch only the base and the ARM code are provided for review;
once we agree on the structure, I will provide src/arch/*/remote_gdb.*
for the other architectures; those patches could then be merged in
together.
Review Request: http://reviews.gem5.org/r/3207/
Pushed by Joel Hestness <jthestness@gmail.com>
2015-12-18 22:12:07 +01:00
|
|
|
BaseRemoteGDB(_system, c)
|
2007-03-05 18:56:26 +01:00
|
|
|
{}
|
|
|
|
|
|
2014-12-06 07:36:16 +01:00
|
|
|
bool
|
|
|
|
|
RemoteGDB::acc(Addr va, size_t len)
|
2007-03-05 18:56:26 +01:00
|
|
|
{
|
2014-12-06 07:36:16 +01:00
|
|
|
if (FullSystem) {
|
|
|
|
|
Walker *walker = context->getDTBPtr()->getWalker();
|
|
|
|
|
unsigned logBytes;
|
|
|
|
|
Fault fault = walker->startFunctional(context, va, logBytes,
|
|
|
|
|
BaseTLB::Read);
|
|
|
|
|
if (fault != NoFault)
|
|
|
|
|
return false;
|
|
|
|
|
|
|
|
|
|
Addr endVa = va + len - 1;
|
|
|
|
|
if ((va & ~mask(logBytes)) == (endVa & ~mask(logBytes)))
|
|
|
|
|
return true;
|
|
|
|
|
|
|
|
|
|
fault = walker->startFunctional(context, endVa, logBytes,
|
|
|
|
|
BaseTLB::Read);
|
|
|
|
|
return fault == NoFault;
|
|
|
|
|
} else {
|
|
|
|
|
TlbEntry entry;
|
|
|
|
|
return context->getProcessPtr()->pTable->lookup(va, entry);
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
arm: remote GDB: rationalize structure of register offsets
Currently, the wire format of register values in g- and G-packets is
modelled using a union of uint8/16/32/64 arrays. The offset positions
of each register are expressed as a "register count" scaled according
to the width of the register in question. This results in counter-
intuitive and error-prone "register count arithmetic", and some
formats would even be altogether unrepresentable in such model, e.g.
a 64-bit register following a 32-bit one would have a fractional index
in the regs64 array.
Another difficulty is that the array is allocated before the actual
architecture of the workload is known (and therefore before the correct
size for the array can be calculated).
With this patch I propose a simpler mechanism for expressing the
register set structure. In the new code, GdbRegCache is an abstract
class; its subclasses contain straightforward structs reflecting the
register representation. The determination whether to use e.g. the
AArch32 vs. AArch64 register set (or SPARCv8 vs SPARCv9, etc.) is made
by polymorphically dispatching getregs() to the concrete subclass.
The subclass is not instantiated until it is needed for actual
g-/G-packet processing, when the mode is already known.
This patch is not meant to be merged in on its own, because it changes
the contract between src/base/remote_gdb.* and src/arch/*/remote_gdb.*,
so as it stands right now, it would break the other architectures.
In this patch only the base and the ARM code are provided for review;
once we agree on the structure, I will provide src/arch/*/remote_gdb.*
for the other architectures; those patches could then be merged in
together.
Review Request: http://reviews.gem5.org/r/3207/
Pushed by Joel Hestness <jthestness@gmail.com>
2015-12-18 22:12:07 +01:00
|
|
|
RemoteGDB::BaseGdbRegCache*
|
|
|
|
|
RemoteGDB::gdbRegs()
|
2007-03-05 18:56:26 +01:00
|
|
|
{
|
2014-12-06 07:36:16 +01:00
|
|
|
HandyM5Reg m5reg = context->readMiscRegNoEffect(MISCREG_M5_REG);
|
arm: remote GDB: rationalize structure of register offsets
Currently, the wire format of register values in g- and G-packets is
modelled using a union of uint8/16/32/64 arrays. The offset positions
of each register are expressed as a "register count" scaled according
to the width of the register in question. This results in counter-
intuitive and error-prone "register count arithmetic", and some
formats would even be altogether unrepresentable in such model, e.g.
a 64-bit register following a 32-bit one would have a fractional index
in the regs64 array.
Another difficulty is that the array is allocated before the actual
architecture of the workload is known (and therefore before the correct
size for the array can be calculated).
With this patch I propose a simpler mechanism for expressing the
register set structure. In the new code, GdbRegCache is an abstract
class; its subclasses contain straightforward structs reflecting the
register representation. The determination whether to use e.g. the
AArch32 vs. AArch64 register set (or SPARCv8 vs SPARCv9, etc.) is made
by polymorphically dispatching getregs() to the concrete subclass.
The subclass is not instantiated until it is needed for actual
g-/G-packet processing, when the mode is already known.
This patch is not meant to be merged in on its own, because it changes
the contract between src/base/remote_gdb.* and src/arch/*/remote_gdb.*,
so as it stands right now, it would break the other architectures.
In this patch only the base and the ARM code are provided for review;
once we agree on the structure, I will provide src/arch/*/remote_gdb.*
for the other architectures; those patches could then be merged in
together.
Review Request: http://reviews.gem5.org/r/3207/
Pushed by Joel Hestness <jthestness@gmail.com>
2015-12-18 22:12:07 +01:00
|
|
|
if (m5reg.submode == SixtyFourBitMode)
|
|
|
|
|
return new AMD64GdbRegCache(this);
|
|
|
|
|
else
|
|
|
|
|
return new X86GdbRegCache(this);
|
2007-03-05 18:56:26 +01:00
|
|
|
}
|
|
|
|
|
|
arm: remote GDB: rationalize structure of register offsets
Currently, the wire format of register values in g- and G-packets is
modelled using a union of uint8/16/32/64 arrays. The offset positions
of each register are expressed as a "register count" scaled according
to the width of the register in question. This results in counter-
intuitive and error-prone "register count arithmetic", and some
formats would even be altogether unrepresentable in such model, e.g.
a 64-bit register following a 32-bit one would have a fractional index
in the regs64 array.
Another difficulty is that the array is allocated before the actual
architecture of the workload is known (and therefore before the correct
size for the array can be calculated).
With this patch I propose a simpler mechanism for expressing the
register set structure. In the new code, GdbRegCache is an abstract
class; its subclasses contain straightforward structs reflecting the
register representation. The determination whether to use e.g. the
AArch32 vs. AArch64 register set (or SPARCv8 vs SPARCv9, etc.) is made
by polymorphically dispatching getregs() to the concrete subclass.
The subclass is not instantiated until it is needed for actual
g-/G-packet processing, when the mode is already known.
This patch is not meant to be merged in on its own, because it changes
the contract between src/base/remote_gdb.* and src/arch/*/remote_gdb.*,
so as it stands right now, it would break the other architectures.
In this patch only the base and the ARM code are provided for review;
once we agree on the structure, I will provide src/arch/*/remote_gdb.*
for the other architectures; those patches could then be merged in
together.
Review Request: http://reviews.gem5.org/r/3207/
Pushed by Joel Hestness <jthestness@gmail.com>
2015-12-18 22:12:07 +01:00
|
|
|
|
|
|
|
|
|
2014-12-06 07:36:16 +01:00
|
|
|
void
|
arm: remote GDB: rationalize structure of register offsets
Currently, the wire format of register values in g- and G-packets is
modelled using a union of uint8/16/32/64 arrays. The offset positions
of each register are expressed as a "register count" scaled according
to the width of the register in question. This results in counter-
intuitive and error-prone "register count arithmetic", and some
formats would even be altogether unrepresentable in such model, e.g.
a 64-bit register following a 32-bit one would have a fractional index
in the regs64 array.
Another difficulty is that the array is allocated before the actual
architecture of the workload is known (and therefore before the correct
size for the array can be calculated).
With this patch I propose a simpler mechanism for expressing the
register set structure. In the new code, GdbRegCache is an abstract
class; its subclasses contain straightforward structs reflecting the
register representation. The determination whether to use e.g. the
AArch32 vs. AArch64 register set (or SPARCv8 vs SPARCv9, etc.) is made
by polymorphically dispatching getregs() to the concrete subclass.
The subclass is not instantiated until it is needed for actual
g-/G-packet processing, when the mode is already known.
This patch is not meant to be merged in on its own, because it changes
the contract between src/base/remote_gdb.* and src/arch/*/remote_gdb.*,
so as it stands right now, it would break the other architectures.
In this patch only the base and the ARM code are provided for review;
once we agree on the structure, I will provide src/arch/*/remote_gdb.*
for the other architectures; those patches could then be merged in
together.
Review Request: http://reviews.gem5.org/r/3207/
Pushed by Joel Hestness <jthestness@gmail.com>
2015-12-18 22:12:07 +01:00
|
|
|
RemoteGDB::AMD64GdbRegCache::getRegs(ThreadContext *context)
|
2007-03-05 18:56:26 +01:00
|
|
|
{
|
arm: remote GDB: rationalize structure of register offsets
Currently, the wire format of register values in g- and G-packets is
modelled using a union of uint8/16/32/64 arrays. The offset positions
of each register are expressed as a "register count" scaled according
to the width of the register in question. This results in counter-
intuitive and error-prone "register count arithmetic", and some
formats would even be altogether unrepresentable in such model, e.g.
a 64-bit register following a 32-bit one would have a fractional index
in the regs64 array.
Another difficulty is that the array is allocated before the actual
architecture of the workload is known (and therefore before the correct
size for the array can be calculated).
With this patch I propose a simpler mechanism for expressing the
register set structure. In the new code, GdbRegCache is an abstract
class; its subclasses contain straightforward structs reflecting the
register representation. The determination whether to use e.g. the
AArch32 vs. AArch64 register set (or SPARCv8 vs SPARCv9, etc.) is made
by polymorphically dispatching getregs() to the concrete subclass.
The subclass is not instantiated until it is needed for actual
g-/G-packet processing, when the mode is already known.
This patch is not meant to be merged in on its own, because it changes
the contract between src/base/remote_gdb.* and src/arch/*/remote_gdb.*,
so as it stands right now, it would break the other architectures.
In this patch only the base and the ARM code are provided for review;
once we agree on the structure, I will provide src/arch/*/remote_gdb.*
for the other architectures; those patches could then be merged in
together.
Review Request: http://reviews.gem5.org/r/3207/
Pushed by Joel Hestness <jthestness@gmail.com>
2015-12-18 22:12:07 +01:00
|
|
|
DPRINTF(GDBAcc, "getRegs in remotegdb \n");
|
|
|
|
|
r.rax = context->readIntReg(INTREG_RAX);
|
|
|
|
|
r.rbx = context->readIntReg(INTREG_RBX);
|
|
|
|
|
r.rcx = context->readIntReg(INTREG_RCX);
|
|
|
|
|
r.rdx = context->readIntReg(INTREG_RDX);
|
|
|
|
|
r.rsi = context->readIntReg(INTREG_RSI);
|
|
|
|
|
r.rdi = context->readIntReg(INTREG_RDI);
|
|
|
|
|
r.rbp = context->readIntReg(INTREG_RBP);
|
|
|
|
|
r.rsp = context->readIntReg(INTREG_RSP);
|
|
|
|
|
r.r8 = context->readIntReg(INTREG_R8);
|
|
|
|
|
r.r9 = context->readIntReg(INTREG_R9);
|
|
|
|
|
r.r10 = context->readIntReg(INTREG_R10);
|
|
|
|
|
r.r11 = context->readIntReg(INTREG_R11);
|
|
|
|
|
r.r12 = context->readIntReg(INTREG_R12);
|
|
|
|
|
r.r13 = context->readIntReg(INTREG_R13);
|
|
|
|
|
r.r14 = context->readIntReg(INTREG_R14);
|
|
|
|
|
r.r15 = context->readIntReg(INTREG_R15);
|
|
|
|
|
r.rip = context->pcState().pc();
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r.eflags = context->readMiscRegNoEffect(MISCREG_RFLAGS);
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r.cs = context->readMiscRegNoEffect(MISCREG_CS);
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r.ss = context->readMiscRegNoEffect(MISCREG_SS);
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r.ds = context->readMiscRegNoEffect(MISCREG_DS);
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r.es = context->readMiscRegNoEffect(MISCREG_ES);
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r.fs = context->readMiscRegNoEffect(MISCREG_FS);
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r.gs = context->readMiscRegNoEffect(MISCREG_GS);
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|
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}
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void
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RemoteGDB::X86GdbRegCache::getRegs(ThreadContext *context)
|
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|
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|
{
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|
|
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|
DPRINTF(GDBAcc, "getRegs in remotegdb \n");
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|
|
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|
r.eax = context->readIntReg(INTREG_RAX);
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r.ecx = context->readIntReg(INTREG_RCX);
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|
r.edx = context->readIntReg(INTREG_RDX);
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|
r.ebx = context->readIntReg(INTREG_RBX);
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|
|
|
|
r.esp = context->readIntReg(INTREG_RSP);
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|
|
|
|
r.ebp = context->readIntReg(INTREG_RBP);
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|
|
|
|
r.esi = context->readIntReg(INTREG_RSI);
|
|
|
|
|
r.edi = context->readIntReg(INTREG_RDI);
|
|
|
|
|
r.eip = context->pcState().pc();
|
|
|
|
|
r.eflags = context->readMiscRegNoEffect(MISCREG_RFLAGS);
|
|
|
|
|
r.cs = context->readMiscRegNoEffect(MISCREG_CS);
|
|
|
|
|
r.ss = context->readMiscRegNoEffect(MISCREG_SS);
|
|
|
|
|
r.ds = context->readMiscRegNoEffect(MISCREG_DS);
|
|
|
|
|
r.es = context->readMiscRegNoEffect(MISCREG_ES);
|
|
|
|
|
r.fs = context->readMiscRegNoEffect(MISCREG_FS);
|
|
|
|
|
r.gs = context->readMiscRegNoEffect(MISCREG_GS);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
void
|
|
|
|
|
RemoteGDB::AMD64GdbRegCache::setRegs(ThreadContext *context) const
|
|
|
|
|
{
|
|
|
|
|
DPRINTF(GDBAcc, "setRegs in remotegdb \n");
|
|
|
|
|
context->setIntReg(INTREG_RAX, r.rax);
|
|
|
|
|
context->setIntReg(INTREG_RBX, r.rbx);
|
|
|
|
|
context->setIntReg(INTREG_RCX, r.rcx);
|
|
|
|
|
context->setIntReg(INTREG_RDX, r.rdx);
|
|
|
|
|
context->setIntReg(INTREG_RSI, r.rsi);
|
|
|
|
|
context->setIntReg(INTREG_RDI, r.rdi);
|
|
|
|
|
context->setIntReg(INTREG_RBP, r.rbp);
|
|
|
|
|
context->setIntReg(INTREG_RSP, r.rsp);
|
|
|
|
|
context->setIntReg(INTREG_R8, r.r8);
|
|
|
|
|
context->setIntReg(INTREG_R9, r.r9);
|
|
|
|
|
context->setIntReg(INTREG_R10, r.r10);
|
|
|
|
|
context->setIntReg(INTREG_R11, r.r11);
|
|
|
|
|
context->setIntReg(INTREG_R12, r.r12);
|
|
|
|
|
context->setIntReg(INTREG_R13, r.r13);
|
|
|
|
|
context->setIntReg(INTREG_R14, r.r14);
|
|
|
|
|
context->setIntReg(INTREG_R15, r.r15);
|
|
|
|
|
context->pcState(r.rip);
|
|
|
|
|
context->setMiscReg(MISCREG_RFLAGS, r.eflags);
|
|
|
|
|
if (r.cs != context->readMiscRegNoEffect(MISCREG_CS))
|
|
|
|
|
warn("Remote gdb: Ignoring update to CS.\n");
|
|
|
|
|
if (r.ss != context->readMiscRegNoEffect(MISCREG_SS))
|
|
|
|
|
warn("Remote gdb: Ignoring update to SS.\n");
|
|
|
|
|
if (r.ds != context->readMiscRegNoEffect(MISCREG_DS))
|
|
|
|
|
warn("Remote gdb: Ignoring update to DS.\n");
|
|
|
|
|
if (r.es != context->readMiscRegNoEffect(MISCREG_ES))
|
|
|
|
|
warn("Remote gdb: Ignoring update to ES.\n");
|
|
|
|
|
if (r.fs != context->readMiscRegNoEffect(MISCREG_FS))
|
|
|
|
|
warn("Remote gdb: Ignoring update to FS.\n");
|
|
|
|
|
if (r.gs != context->readMiscRegNoEffect(MISCREG_GS))
|
|
|
|
|
warn("Remote gdb: Ignoring update to GS.\n");
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
void
|
|
|
|
|
RemoteGDB::X86GdbRegCache::setRegs(ThreadContext *context) const
|
|
|
|
|
{
|
|
|
|
|
DPRINTF(GDBAcc, "setRegs in remotegdb \n");
|
|
|
|
|
context->setIntReg(INTREG_RAX, r.eax);
|
|
|
|
|
context->setIntReg(INTREG_RCX, r.ecx);
|
|
|
|
|
context->setIntReg(INTREG_RDX, r.edx);
|
|
|
|
|
context->setIntReg(INTREG_RBX, r.ebx);
|
|
|
|
|
context->setIntReg(INTREG_RSP, r.esp);
|
|
|
|
|
context->setIntReg(INTREG_RBP, r.ebp);
|
|
|
|
|
context->setIntReg(INTREG_RSI, r.esi);
|
|
|
|
|
context->setIntReg(INTREG_RDI, r.edi);
|
|
|
|
|
context->pcState(r.eip);
|
|
|
|
|
context->setMiscReg(MISCREG_RFLAGS, r.eflags);
|
|
|
|
|
if (r.cs != context->readMiscRegNoEffect(MISCREG_CS))
|
|
|
|
|
warn("Remote gdb: Ignoring update to CS.\n");
|
|
|
|
|
if (r.ss != context->readMiscRegNoEffect(MISCREG_SS))
|
|
|
|
|
warn("Remote gdb: Ignoring update to SS.\n");
|
|
|
|
|
if (r.ds != context->readMiscRegNoEffect(MISCREG_DS))
|
|
|
|
|
warn("Remote gdb: Ignoring update to DS.\n");
|
|
|
|
|
if (r.es != context->readMiscRegNoEffect(MISCREG_ES))
|
|
|
|
|
warn("Remote gdb: Ignoring update to ES.\n");
|
|
|
|
|
if (r.fs != context->readMiscRegNoEffect(MISCREG_FS))
|
|
|
|
|
warn("Remote gdb: Ignoring update to FS.\n");
|
|
|
|
|
if (r.gs != context->readMiscRegNoEffect(MISCREG_GS))
|
|
|
|
|
warn("Remote gdb: Ignoring update to GS.\n");
|
2007-03-05 18:56:26 +01:00
|
|
|
}
|
