2006-08-17 00:48:15 +02:00
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[root]
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type=Root
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children=system
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2007-04-22 20:50:37 +02:00
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dummy=0
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2006-08-17 00:48:15 +02:00
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[system]
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type=System
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children=cpu membus physmem
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mem_mode=atomic
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physmem=system.physmem
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[system.cpu]
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type=TimingSimpleCPU
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2006-08-18 06:17:21 +02:00
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children=dcache icache l2cache toL2Bus workload
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2007-04-22 20:50:37 +02:00
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clock=500
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2006-10-08 23:07:23 +02:00
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cpu_id=0
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2006-08-17 00:48:15 +02:00
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defer_registration=false
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function_trace=false
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function_trace_start=0
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max_insts_all_threads=0
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max_insts_any_thread=0
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max_loads_all_threads=0
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max_loads_any_thread=0
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2007-04-22 20:50:37 +02:00
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phase=0
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2006-10-07 17:32:10 +02:00
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progress_interval=0
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2006-08-17 00:48:15 +02:00
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system=system
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workload=system.cpu.workload
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2006-09-05 22:24:47 +02:00
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dcache_port=system.cpu.dcache.cpu_side
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icache_port=system.cpu.icache.cpu_side
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2006-08-17 00:48:15 +02:00
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2006-08-18 06:17:21 +02:00
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[system.cpu.dcache]
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type=BaseCache
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adaptive_compression=false
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assoc=2
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block_size=64
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compressed_bus=false
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compression_latency=0
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hash_delay=1
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hit_latency=1
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latency=1
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lifo=false
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max_miss_count=0
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mshrs=10
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prefetch_access=false
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prefetch_cache_check_push=true
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prefetch_data_accesses_only=false
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prefetch_degree=1
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prefetch_latency=10
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prefetch_miss=false
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prefetch_past_page=false
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prefetch_policy=none
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prefetch_serial_squash=false
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prefetch_use_cpu_id=true
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prefetcher_size=100
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prioritizeRequests=false
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protocol=Null
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repl=Null
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size=262144
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split=false
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split_size=0
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store_compressed=false
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subblock_size=0
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tgts_per_mshr=5
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trace_addr=0
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two_queue=false
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write_buffers=8
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2006-09-05 22:24:47 +02:00
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cpu_side=system.cpu.dcache_port
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mem_side=system.cpu.toL2Bus.port[1]
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2006-08-18 06:17:21 +02:00
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[system.cpu.icache]
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type=BaseCache
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adaptive_compression=false
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assoc=2
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block_size=64
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compressed_bus=false
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compression_latency=0
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hash_delay=1
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hit_latency=1
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latency=1
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lifo=false
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max_miss_count=0
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mshrs=10
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prefetch_access=false
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prefetch_cache_check_push=true
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prefetch_data_accesses_only=false
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prefetch_degree=1
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prefetch_latency=10
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prefetch_miss=false
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prefetch_past_page=false
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prefetch_policy=none
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prefetch_serial_squash=false
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prefetch_use_cpu_id=true
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prefetcher_size=100
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prioritizeRequests=false
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protocol=Null
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repl=Null
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size=131072
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split=false
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split_size=0
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store_compressed=false
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subblock_size=0
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tgts_per_mshr=5
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trace_addr=0
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two_queue=false
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write_buffers=8
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2006-09-05 22:24:47 +02:00
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cpu_side=system.cpu.icache_port
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mem_side=system.cpu.toL2Bus.port[0]
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2006-08-18 06:17:21 +02:00
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[system.cpu.l2cache]
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type=BaseCache
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adaptive_compression=false
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assoc=2
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block_size=64
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compressed_bus=false
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compression_latency=0
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hash_delay=1
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hit_latency=1
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latency=1
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lifo=false
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max_miss_count=0
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mshrs=10
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prefetch_access=false
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prefetch_cache_check_push=true
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prefetch_data_accesses_only=false
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prefetch_degree=1
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prefetch_latency=10
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prefetch_miss=false
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prefetch_past_page=false
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prefetch_policy=none
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prefetch_serial_squash=false
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prefetch_use_cpu_id=true
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prefetcher_size=100
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prioritizeRequests=false
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protocol=Null
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repl=Null
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size=2097152
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split=false
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split_size=0
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store_compressed=false
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subblock_size=0
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tgts_per_mshr=5
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trace_addr=0
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two_queue=false
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write_buffers=8
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2006-09-05 22:24:47 +02:00
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cpu_side=system.cpu.toL2Bus.port[2]
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mem_side=system.membus.port[1]
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2006-08-18 06:17:21 +02:00
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[system.cpu.toL2Bus]
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type=Bus
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bus_id=0
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2006-10-10 17:04:05 +02:00
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clock=1000
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2006-11-06 02:42:05 +01:00
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responder_set=false
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2006-10-10 17:04:05 +02:00
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width=64
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2006-09-05 22:24:47 +02:00
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port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
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2006-08-18 06:17:21 +02:00
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2006-08-17 00:48:15 +02:00
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[system.cpu.workload]
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type=LiveProcess
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cmd=hello
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2007-04-22 20:50:37 +02:00
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cwd=
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2006-10-07 17:32:10 +02:00
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egid=100
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2006-08-17 00:48:15 +02:00
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env=
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2006-10-07 17:32:10 +02:00
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euid=100
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2006-08-22 17:08:02 +02:00
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executable=tests/test-progs/hello/bin/alpha/tru64/hello
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2006-10-07 17:32:10 +02:00
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gid=100
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2006-08-17 00:48:15 +02:00
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input=cin
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output=cout
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2006-10-07 17:32:10 +02:00
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pid=100
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ppid=99
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2006-08-17 00:48:15 +02:00
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system=system
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2006-10-07 17:32:10 +02:00
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uid=100
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2006-08-17 00:48:15 +02:00
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[system.membus]
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type=Bus
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bus_id=0
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2006-10-10 17:04:05 +02:00
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clock=1000
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2006-11-06 02:42:05 +01:00
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responder_set=false
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2006-10-10 17:04:05 +02:00
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width=64
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2006-09-05 22:24:47 +02:00
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port=system.physmem.port system.cpu.l2cache.mem_side
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2006-08-17 00:48:15 +02:00
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[system.physmem]
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type=PhysicalMemory
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file=
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latency=1
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2006-08-18 06:17:21 +02:00
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range=0:134217727
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2007-04-22 20:50:37 +02:00
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zero=false
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2006-09-05 22:24:47 +02:00
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port=system.membus.port[0]
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2006-08-17 00:48:15 +02:00
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