gem5/src/arch/x86/isa/insts/data_transfer/conditional_move.py

# Copyright (c) 2007 The Hewlett-Packard Development Company
# All rights reserved.
#
# Redistribution and use of this software in source and binary forms,
# with or without modification, are permitted provided that the
# following conditions are met:
#
# The software must be used only for Non-Commercial Use which means any
# use which is NOT directed to receiving any direct monetary
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# commercial advantage.
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# If you wish to use this software or functionality therein that may be
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#
# Redistributions of source code must retain the above copyright notice,
# this list of conditions and the following disclaimer.  Redistributions
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# this software without specific prior written permission.  No right of
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# notice to acknowledge the contribution from this software where
# applicable, this list of conditions and the disclaimer below.
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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# Authors: Gabe Black

microcode = '''
def macroop CMOVZ_R_R
{
    mov reg, reg, regm, flags=(CZF,)
};

def macroop CMOVZ_R_M
{
    ld t1, ds, [scale, index, base], disp
    mov reg, reg, t1, flags=(CZF,)
};

def macroop CMOVZ_R_P
{
    rdip t7
    ld t1, ds, [0, t0, t7], disp
    mov reg, reg, t1, flags=(CZF,)
};

def macroop CMOVNZ_R_R
{
    mov reg, reg, regm, flags=(nCZF,)
};

def macroop CMOVNZ_R_M
{
    ld t1, ds, [scale, index, base], disp
    mov reg, reg, t1, flags=(nCZF,)
};

def macroop CMOVNZ_R_P
{
    rdip t7
    ld t1, ds, [0, t0, t7], disp
    mov reg, reg, t1, flags=(nCZF,)
};

def macroop CMOVB_R_R
{
    mov reg, reg, regm, flags=(CCF,)
};

def macroop CMOVB_R_M
{
    ld t1, ds, [scale, index, base], disp
    mov reg, reg, t1, flags=(CCF,)
};

def macroop CMOVB_R_P
{
    rdip t7
    ld t1, ds, [0, t0, t7], disp
    mov reg, reg, t1, flags=(CCF,)
};

def macroop CMOVNB_R_R
{
    mov reg, reg, regm, flags=(nCCF,)
};

def macroop CMOVNB_R_M
{
    ld t1, ds, [scale, index, base], disp
    mov reg, reg, t1, flags=(nCCF,)
};

def macroop CMOVNB_R_P
{
    rdip t7
    ld t1, ds, [0, t0, t7], disp
    mov reg, reg, t1, flags=(nCCF,)
};

def macroop CMOVBE_R_R
{
    mov reg, reg, regm, flags=(CCvZF,)
};

def macroop CMOVBE_R_M
{
    ld t1, ds, [scale, index, base], disp
    mov reg, reg, t1, flags=(CCvZF,)
};

def macroop CMOVBE_R_P
{
    rdip t7
    ld t1, ds, [0, t0, t7], disp
    mov reg, reg, t1, flags=(CCvZF,)
};

def macroop CMOVNBE_R_R
{
    mov reg, reg, regm, flags=(nCCvZF,)
};

def macroop CMOVNBE_R_M
{
    ld t1, ds, [scale, index, base], disp
    mov reg, reg, t1, flags=(nCCvZF,)
};

def macroop CMOVNBE_R_P
{
    rdip t7
    ld t1, ds, [0, t0, t7], disp
    mov reg, reg, t1, flags=(nCCvZF,)
};

def macroop CMOVS_R_R
{
    mov reg, reg, regm, flags=(CSF,)
};

def macroop CMOVS_R_M
{
    ld t1, ds, [scale, index, base], disp
    mov reg, reg, t1, flags=(CSF,)
};

def macroop CMOVS_R_P
{
    rdip t7
    ld t1, ds, [0, t0, t7], disp
    mov reg, reg, t1, flags=(CSF,)
};

def macroop CMOVNS_R_R
{
    mov reg, reg, regm, flags=(nCSF,)
};

def macroop CMOVNS_R_M
{
    ld t1, ds, [scale, index, base], disp
    mov reg, reg, t1, flags=(nCSF,)
};

def macroop CMOVNS_R_P
{
    rdip t7
    ld t1, ds, [0, t0, t7], disp
    mov reg, reg, t1, flags=(nCSF,)
};

def macroop CMOVP_R_R
{
    mov reg, reg, regm, flags=(CPF,)
};

def macroop CMOVP_R_M
{
    ld t1, ds, [scale, index, base], disp
    mov reg, reg, t1, flags=(CPF,)
};

def macroop CMOVP_R_P
{
    rdip t7
    ld t1, ds, [0, t0, t7], disp
    mov reg, reg, t1, flags=(CPF,)
};

def macroop CMOVNP_R_R
{
    mov reg, reg, regm, flags=(nCPF,)
};

def macroop CMOVNP_R_M
{
    ld t1, ds, [scale, index, base], disp
    mov reg, reg, regm, flags=(nCPF,)
};

def macroop CMOVNP_R_P
{
    rdip t7
    ld t1, ds, [0, t0, t7], disp
    mov reg, reg, regm, flags=(nCPF,)
};

def macroop CMOVL_R_R
{
    mov reg, reg, regm, flags=(CSxOF,)
};

def macroop CMOVL_R_M
{
    ld t1, ds, [scale, index, base], disp
    mov reg, reg, t1, flags=(CSxOF,)
};

def macroop CMOVL_R_P
{
    rdip t7
    ld t1, ds, [0, t0, t7], disp
    mov reg, reg, t1, flags=(CSxOF,)
};

def macroop CMOVNL_R_R
{
    mov reg, reg, regm, flags=(nCSxOF,)
};

def macroop CMOVNL_R_M
{
    ld t1, ds, [scale, index, base], disp
    mov reg, reg, t1, flags=(nCSxOF,)
};

def macroop CMOVNL_R_P
{
    rdip t7
    ld t1, ds, [0, t0, t7], disp
    mov reg, reg, t1, flags=(nCSxOF,)
};

def macroop CMOVLE_R_R
{
    mov reg, reg, regm, flags=(CSxOvZF,)
};

def macroop CMOVLE_R_M
{
    ld t1, ds, [scale, index, base], disp
    mov reg, reg, t1, flags=(CSxOvZF,)
};

def macroop CMOVLE_R_P
{
    rdip t7
    ld t1, ds, [0, t0, t7], disp
    mov reg, reg, t1, flags=(CSxOvZF,)
};

def macroop CMOVNLE_R_R
{
    mov reg, reg, regm, flags=(nCSxOvZF,)
};

def macroop CMOVNLE_R_M
{
    ld t1, ds, [scale, index, base], disp
    mov reg, reg, t1, flags=(nCSxOvZF,)
};

def macroop CMOVNLE_R_P
{
    rdip t7
    ld t1, ds, [0, t0, t7], disp
    mov reg, reg, t1, flags=(nCSxOvZF,)
};

def macroop CMOVO_R_R
{
    mov reg, reg, regm, flags=(COF,)
};

def macroop CMOVO_R_M
{
    ld t1, ds, [scale, index, base], disp
    mov reg, reg, t1, flags=(COF,)
};

def macroop CMOVO_R_P
{
    rdip t7
    ld t1, ds, [0, t0, t7], disp
    mov reg, reg, t1, flags=(COF,)
};

def macroop CMOVNO_R_R
{
    mov reg, reg, regm, flags=(nCOF,)
};

def macroop CMOVNO_R_M
{
    ld t1, ds, [scale, index, base], disp
    mov reg, reg, t1, flags=(nCOF,)
};

def macroop CMOVNO_R_P
{
    rdip t7
    ld t1, ds, [0, t0, t7], disp
    mov reg, reg, t1, flags=(nCOF,)
};
'''