509 lines
9.5 KiB
INI
509 lines
9.5 KiB
INI
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[root]
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type=Root
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children=system
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dummy=0
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[system]
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type=System
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children=cpu0 cpu1 cpu2 cpu3 l2c membus physmem toL2Bus
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mem_mode=atomic
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physmem=system.physmem
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[system.cpu0]
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type=AtomicSimpleCPU
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children=dcache dtb icache itb tracer workload
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checker=Null
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clock=500
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cpu_id=0
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defer_registration=false
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do_checkpoint_insts=true
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do_statistics_insts=true
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dtb=system.cpu0.dtb
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function_trace=false
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function_trace_start=0
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itb=system.cpu0.itb
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max_insts_all_threads=0
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max_insts_any_thread=0
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max_loads_all_threads=0
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max_loads_any_thread=0
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numThreads=1
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phase=0
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progress_interval=0
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simulate_data_stalls=false
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simulate_inst_stalls=false
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system=system
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tracer=system.cpu0.tracer
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width=1
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workload=system.cpu0.workload
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dcache_port=system.cpu0.dcache.cpu_side
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icache_port=system.cpu0.icache.cpu_side
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[system.cpu0.dcache]
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type=BaseCache
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addr_range=0:18446744073709551615
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assoc=4
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block_size=64
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cpu_side_filter_ranges=
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hash_delay=1
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latency=1000
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max_miss_count=0
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mem_side_filter_ranges=
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mshrs=4
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prefetch_cache_check_push=true
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prefetch_data_accesses_only=false
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prefetch_degree=1
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prefetch_latency=10000
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prefetch_on_access=false
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prefetch_past_page=false
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prefetch_policy=none
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prefetch_serial_squash=false
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prefetch_use_cpu_id=true
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prefetcher_size=100
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prioritizeRequests=false
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repl=Null
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size=32768
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subblock_size=0
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tgts_per_mshr=8
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trace_addr=0
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two_queue=false
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write_buffers=8
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cpu_side=system.cpu0.dcache_port
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mem_side=system.toL2Bus.port[2]
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[system.cpu0.dtb]
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type=SparcTLB
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size=64
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[system.cpu0.icache]
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type=BaseCache
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addr_range=0:18446744073709551615
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assoc=1
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block_size=64
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cpu_side_filter_ranges=
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hash_delay=1
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latency=1000
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max_miss_count=0
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mem_side_filter_ranges=
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mshrs=4
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prefetch_cache_check_push=true
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prefetch_data_accesses_only=false
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prefetch_degree=1
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prefetch_latency=10000
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prefetch_on_access=false
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prefetch_past_page=false
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prefetch_policy=none
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prefetch_serial_squash=false
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prefetch_use_cpu_id=true
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prefetcher_size=100
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prioritizeRequests=false
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repl=Null
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size=32768
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subblock_size=0
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tgts_per_mshr=8
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trace_addr=0
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two_queue=false
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write_buffers=8
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cpu_side=system.cpu0.icache_port
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mem_side=system.toL2Bus.port[1]
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[system.cpu0.itb]
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type=SparcTLB
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size=64
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[system.cpu0.tracer]
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type=ExeTracer
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[system.cpu0.workload]
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type=LiveProcess
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cmd=test_atomic 4
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cwd=
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egid=100
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env=
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errout=cerr
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euid=100
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executable=/dist/m5/regression/test-progs/m5threads/bin/sparc/linux/test_atomic
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gid=100
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input=cin
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max_stack_size=67108864
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output=cout
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pid=100
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ppid=99
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simpoint=0
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system=system
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uid=100
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[system.cpu1]
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type=AtomicSimpleCPU
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children=dcache dtb icache itb tracer
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checker=Null
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clock=500
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cpu_id=1
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defer_registration=false
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do_checkpoint_insts=true
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do_statistics_insts=true
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dtb=system.cpu1.dtb
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function_trace=false
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function_trace_start=0
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itb=system.cpu1.itb
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max_insts_all_threads=0
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max_insts_any_thread=0
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max_loads_all_threads=0
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max_loads_any_thread=0
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numThreads=1
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phase=0
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progress_interval=0
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simulate_data_stalls=false
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simulate_inst_stalls=false
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system=system
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tracer=system.cpu1.tracer
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width=1
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workload=system.cpu0.workload
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dcache_port=system.cpu1.dcache.cpu_side
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icache_port=system.cpu1.icache.cpu_side
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[system.cpu1.dcache]
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type=BaseCache
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addr_range=0:18446744073709551615
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assoc=4
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block_size=64
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cpu_side_filter_ranges=
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hash_delay=1
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latency=1000
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max_miss_count=0
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mem_side_filter_ranges=
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mshrs=4
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prefetch_cache_check_push=true
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prefetch_data_accesses_only=false
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prefetch_degree=1
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prefetch_latency=10000
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prefetch_on_access=false
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prefetch_past_page=false
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prefetch_policy=none
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prefetch_serial_squash=false
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prefetch_use_cpu_id=true
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prefetcher_size=100
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prioritizeRequests=false
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repl=Null
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size=32768
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subblock_size=0
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tgts_per_mshr=8
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trace_addr=0
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two_queue=false
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write_buffers=8
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cpu_side=system.cpu1.dcache_port
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mem_side=system.toL2Bus.port[4]
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[system.cpu1.dtb]
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type=SparcTLB
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size=64
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[system.cpu1.icache]
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type=BaseCache
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addr_range=0:18446744073709551615
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assoc=1
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block_size=64
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cpu_side_filter_ranges=
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hash_delay=1
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latency=1000
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max_miss_count=0
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mem_side_filter_ranges=
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mshrs=4
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prefetch_cache_check_push=true
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prefetch_data_accesses_only=false
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prefetch_degree=1
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prefetch_latency=10000
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prefetch_on_access=false
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prefetch_past_page=false
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prefetch_policy=none
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prefetch_serial_squash=false
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prefetch_use_cpu_id=true
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prefetcher_size=100
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prioritizeRequests=false
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repl=Null
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size=32768
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subblock_size=0
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tgts_per_mshr=8
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trace_addr=0
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two_queue=false
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write_buffers=8
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cpu_side=system.cpu1.icache_port
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mem_side=system.toL2Bus.port[3]
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[system.cpu1.itb]
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type=SparcTLB
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size=64
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[system.cpu1.tracer]
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type=ExeTracer
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[system.cpu2]
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type=AtomicSimpleCPU
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children=dcache dtb icache itb tracer
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checker=Null
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clock=500
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cpu_id=2
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defer_registration=false
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do_checkpoint_insts=true
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do_statistics_insts=true
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dtb=system.cpu2.dtb
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function_trace=false
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function_trace_start=0
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itb=system.cpu2.itb
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max_insts_all_threads=0
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max_insts_any_thread=0
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max_loads_all_threads=0
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max_loads_any_thread=0
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numThreads=1
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phase=0
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progress_interval=0
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simulate_data_stalls=false
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simulate_inst_stalls=false
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system=system
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tracer=system.cpu2.tracer
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width=1
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workload=system.cpu0.workload
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dcache_port=system.cpu2.dcache.cpu_side
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icache_port=system.cpu2.icache.cpu_side
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[system.cpu2.dcache]
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type=BaseCache
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addr_range=0:18446744073709551615
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assoc=4
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block_size=64
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cpu_side_filter_ranges=
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hash_delay=1
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latency=1000
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max_miss_count=0
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mem_side_filter_ranges=
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mshrs=4
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prefetch_cache_check_push=true
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prefetch_data_accesses_only=false
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prefetch_degree=1
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prefetch_latency=10000
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prefetch_on_access=false
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prefetch_past_page=false
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prefetch_policy=none
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prefetch_serial_squash=false
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prefetch_use_cpu_id=true
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prefetcher_size=100
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prioritizeRequests=false
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repl=Null
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size=32768
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subblock_size=0
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tgts_per_mshr=8
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trace_addr=0
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two_queue=false
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write_buffers=8
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cpu_side=system.cpu2.dcache_port
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mem_side=system.toL2Bus.port[6]
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[system.cpu2.dtb]
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type=SparcTLB
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size=64
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[system.cpu2.icache]
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type=BaseCache
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addr_range=0:18446744073709551615
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assoc=1
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block_size=64
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cpu_side_filter_ranges=
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hash_delay=1
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latency=1000
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max_miss_count=0
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mem_side_filter_ranges=
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mshrs=4
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prefetch_cache_check_push=true
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prefetch_data_accesses_only=false
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prefetch_degree=1
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prefetch_latency=10000
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prefetch_on_access=false
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prefetch_past_page=false
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prefetch_policy=none
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prefetch_serial_squash=false
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prefetch_use_cpu_id=true
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prefetcher_size=100
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prioritizeRequests=false
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repl=Null
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size=32768
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subblock_size=0
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tgts_per_mshr=8
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trace_addr=0
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two_queue=false
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write_buffers=8
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cpu_side=system.cpu2.icache_port
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mem_side=system.toL2Bus.port[5]
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[system.cpu2.itb]
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type=SparcTLB
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size=64
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[system.cpu2.tracer]
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type=ExeTracer
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[system.cpu3]
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type=AtomicSimpleCPU
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children=dcache dtb icache itb tracer
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checker=Null
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clock=500
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cpu_id=3
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defer_registration=false
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do_checkpoint_insts=true
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do_statistics_insts=true
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dtb=system.cpu3.dtb
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function_trace=false
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function_trace_start=0
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itb=system.cpu3.itb
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max_insts_all_threads=0
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||
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max_insts_any_thread=0
|
||
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max_loads_all_threads=0
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||
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max_loads_any_thread=0
|
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numThreads=1
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phase=0
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||
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progress_interval=0
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||
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simulate_data_stalls=false
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simulate_inst_stalls=false
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system=system
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tracer=system.cpu3.tracer
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width=1
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workload=system.cpu0.workload
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dcache_port=system.cpu3.dcache.cpu_side
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icache_port=system.cpu3.icache.cpu_side
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[system.cpu3.dcache]
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type=BaseCache
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addr_range=0:18446744073709551615
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assoc=4
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|
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block_size=64
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||
|
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cpu_side_filter_ranges=
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|
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hash_delay=1
|
||
|
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latency=1000
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||
|
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max_miss_count=0
|
||
|
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mem_side_filter_ranges=
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||
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mshrs=4
|
||
|
|
prefetch_cache_check_push=true
|
||
|
|
prefetch_data_accesses_only=false
|
||
|
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prefetch_degree=1
|
||
|
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prefetch_latency=10000
|
||
|
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prefetch_on_access=false
|
||
|
|
prefetch_past_page=false
|
||
|
|
prefetch_policy=none
|
||
|
|
prefetch_serial_squash=false
|
||
|
|
prefetch_use_cpu_id=true
|
||
|
|
prefetcher_size=100
|
||
|
|
prioritizeRequests=false
|
||
|
|
repl=Null
|
||
|
|
size=32768
|
||
|
|
subblock_size=0
|
||
|
|
tgts_per_mshr=8
|
||
|
|
trace_addr=0
|
||
|
|
two_queue=false
|
||
|
|
write_buffers=8
|
||
|
|
cpu_side=system.cpu3.dcache_port
|
||
|
|
mem_side=system.toL2Bus.port[8]
|
||
|
|
|
||
|
|
[system.cpu3.dtb]
|
||
|
|
type=SparcTLB
|
||
|
|
size=64
|
||
|
|
|
||
|
|
[system.cpu3.icache]
|
||
|
|
type=BaseCache
|
||
|
|
addr_range=0:18446744073709551615
|
||
|
|
assoc=1
|
||
|
|
block_size=64
|
||
|
|
cpu_side_filter_ranges=
|
||
|
|
hash_delay=1
|
||
|
|
latency=1000
|
||
|
|
max_miss_count=0
|
||
|
|
mem_side_filter_ranges=
|
||
|
|
mshrs=4
|
||
|
|
prefetch_cache_check_push=true
|
||
|
|
prefetch_data_accesses_only=false
|
||
|
|
prefetch_degree=1
|
||
|
|
prefetch_latency=10000
|
||
|
|
prefetch_on_access=false
|
||
|
|
prefetch_past_page=false
|
||
|
|
prefetch_policy=none
|
||
|
|
prefetch_serial_squash=false
|
||
|
|
prefetch_use_cpu_id=true
|
||
|
|
prefetcher_size=100
|
||
|
|
prioritizeRequests=false
|
||
|
|
repl=Null
|
||
|
|
size=32768
|
||
|
|
subblock_size=0
|
||
|
|
tgts_per_mshr=8
|
||
|
|
trace_addr=0
|
||
|
|
two_queue=false
|
||
|
|
write_buffers=8
|
||
|
|
cpu_side=system.cpu3.icache_port
|
||
|
|
mem_side=system.toL2Bus.port[7]
|
||
|
|
|
||
|
|
[system.cpu3.itb]
|
||
|
|
type=SparcTLB
|
||
|
|
size=64
|
||
|
|
|
||
|
|
[system.cpu3.tracer]
|
||
|
|
type=ExeTracer
|
||
|
|
|
||
|
|
[system.l2c]
|
||
|
|
type=BaseCache
|
||
|
|
addr_range=0:18446744073709551615
|
||
|
|
assoc=8
|
||
|
|
block_size=64
|
||
|
|
cpu_side_filter_ranges=
|
||
|
|
hash_delay=1
|
||
|
|
latency=10000
|
||
|
|
max_miss_count=0
|
||
|
|
mem_side_filter_ranges=
|
||
|
|
mshrs=92
|
||
|
|
prefetch_cache_check_push=true
|
||
|
|
prefetch_data_accesses_only=false
|
||
|
|
prefetch_degree=1
|
||
|
|
prefetch_latency=100000
|
||
|
|
prefetch_on_access=false
|
||
|
|
prefetch_past_page=false
|
||
|
|
prefetch_policy=none
|
||
|
|
prefetch_serial_squash=false
|
||
|
|
prefetch_use_cpu_id=true
|
||
|
|
prefetcher_size=100
|
||
|
|
prioritizeRequests=false
|
||
|
|
repl=Null
|
||
|
|
size=4194304
|
||
|
|
subblock_size=0
|
||
|
|
tgts_per_mshr=16
|
||
|
|
trace_addr=0
|
||
|
|
two_queue=false
|
||
|
|
write_buffers=8
|
||
|
|
cpu_side=system.toL2Bus.port[0]
|
||
|
|
mem_side=system.membus.port[0]
|
||
|
|
|
||
|
|
[system.membus]
|
||
|
|
type=Bus
|
||
|
|
block_size=64
|
||
|
|
bus_id=0
|
||
|
|
clock=1000
|
||
|
|
header_cycles=1
|
||
|
|
responder_set=false
|
||
|
|
width=64
|
||
|
|
port=system.l2c.mem_side system.physmem.port[0]
|
||
|
|
|
||
|
|
[system.physmem]
|
||
|
|
type=PhysicalMemory
|
||
|
|
file=
|
||
|
|
latency=30000
|
||
|
|
latency_var=0
|
||
|
|
null=false
|
||
|
|
range=0:1073741823
|
||
|
|
zero=false
|
||
|
|
port=system.membus.port[1]
|
||
|
|
|
||
|
|
[system.toL2Bus]
|
||
|
|
type=Bus
|
||
|
|
block_size=64
|
||
|
|
bus_id=0
|
||
|
|
clock=1000
|
||
|
|
header_cycles=1
|
||
|
|
responder_set=false
|
||
|
|
width=64
|
||
|
|
port=system.l2c.cpu_side system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu2.icache.mem_side system.cpu2.dcache.mem_side system.cpu3.icache.mem_side system.cpu3.dcache.mem_side
|
||
|
|
|