system.cpu.iew.wb_sent 1808754463 # cumulative count of insts sent to commit
system.cpu.iew.wb_count 1805719795 # cumulative count of insts written-back
system.cpu.iew.wb_producers 1169207800 # num instructions producing a value
system.cpu.iew.wb_consumers 1689618799 # num instructions consuming a value
system.cpu.iew.wb_rate 1.175899 # insts written-back per cycle
system.cpu.iew.wb_fanout 0.691995 # average fanout of values written-back
system.cpu.commit.commitSquashedInsts 258113026 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 170 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts 14630522 # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples 1496036001 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 1.112294 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 2.028030 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0 915722932 61.21% 61.21% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 250663462 16.76% 77.97% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 110062832 7.36% 85.32% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 55282207 3.70% 89.02% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4 29306686 1.96% 90.98% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5 34079757 2.28% 93.25% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6 24721963 1.65% 94.91% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7 18129916 1.21% 96.12% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8 58066246 3.88% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total 1496036001 # Number of insts commited each cycle
system.cpu.commit.committedInsts 1544563042 # Number of instructions committed
system.cpu.commit.committedOps 1664032434 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.refs 633153379 # Number of memory references committed
system.cpu.commit.loads 458306334 # Number of loads committed
system.cpu.commit.membars 62 # Number of memory barriers committed
system.cpu.commit.branches 213462427 # Number of branches committed
system.cpu.commit.fp_insts 36 # Number of committed floating point instructions.
system.cpu.commit.int_insts 1477900421 # Number of committed integer instructions.
system.cpu.commit.function_calls 13665177 # Number of function calls committed.
system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
system.cpu.commit.op_class_0::IntAlu 1030178730 61.91% 61.91% # Class of committed instruction
system.cpu.commit.op_class_0::IntMult 700322 0.04% 61.95% # Class of committed instruction
system.cpu.commit.op_class_0::IntDiv 0 0.00% 61.95% # Class of committed instruction
system.cpu.commit.op_class_0::FloatAdd 0 0.00% 61.95% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCmp 0 0.00% 61.95% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCvt 0 0.00% 61.95% # Class of committed instruction
system.cpu.commit.op_class_0::FloatMult 0 0.00% 61.95% # Class of committed instruction
system.cpu.commit.op_class_0::FloatDiv 0 0.00% 61.95% # Class of committed instruction
system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 61.95% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAdd 0 0.00% 61.95% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 61.95% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAlu 0 0.00% 61.95% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCmp 0 0.00% 61.95% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCvt 0 0.00% 61.95% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMisc 0 0.00% 61.95% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMult 0 0.00% 61.95% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 61.95% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShift 0 0.00% 61.95% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 61.95% # Class of committed instruction
system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 61.95% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 61.95% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 61.95% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 61.95% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 61.95% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 61.95% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMisc 3 0.00% 61.95% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 61.95% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 61.95% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 61.95% # Class of committed instruction
system.cpu.commit.op_class_0::MemRead 458306334 27.54% 89.49% # Class of committed instruction
system.cpu.commit.op_class_0::MemWrite 174847045 10.51% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::total 1664032434 # Class of committed instruction
system.cpu.commit.bw_lim_events 58066246 # number cycles where commit BW limit reached
system.cpu.rob.rob_reads 3360114616 # The number of ROB reads
system.cpu.rob.rob_writes 3883791528 # The number of ROB writes
system.cpu.timesIdled 840 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 76214 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 1544563024 # Number of Instructions Simulated
system.cpu.committedOps 1664032416 # Number of Ops (including micro ops) Simulated
system.cpu.cpi 0.994202 # CPI: Cycles Per Instruction
system.cpu.cpi_total 0.994202 # CPI: Total CPI of All Threads
system.cpu.ipc 1.005832 # IPC: Instructions Per Cycle
system.cpu.ipc_total 1.005832 # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads 2175815840 # number of integer regfile reads
system.cpu.int_regfile_writes 1261595611 # number of integer regfile writes
system.cpu.fp_regfile_reads 42 # number of floating regfile reads
system.cpu.fp_regfile_writes 54 # number of floating regfile writes
system.cpu.cc_regfile_reads 6965778765 # number of cc regfile reads
system.cpu.cc_regfile_writes 551854660 # number of cc regfile writes
system.cpu.misc_regfile_reads 675853693 # number of misc regfile reads
system.cpu.misc_regfile_writes 124 # number of misc regfile writes
system.cpu.dcache.tags.replacements 17003710 # number of replacements
system.cpu.dcache.tags.tagsinuse 511.964650 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 638076364 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 17004222 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 37.524584 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 78426500 # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data 511.964650 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.999931 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.999931 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0 395 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1 117 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 1335728390 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 1335728390 # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data 469357603 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 469357603 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 168718615 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 168718615 # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data 57 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total 57 # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data 61 # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total 61 # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data 638076218 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 638076218 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 638076218 # number of overall hits
system.cpu.dcache.overall_hits::total 638076218 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 17418310 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 17418310 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 3867432 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 3867432 # number of WriteReq misses
system.cpu.dcache.SoftPFReq_misses::cpu.data 2 # number of SoftPFReq misses
system.cpu.dcache.SoftPFReq_misses::total 2 # number of SoftPFReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.data 4 # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total 4 # number of LoadLockedReq misses
system.cpu.dcache.demand_misses::cpu.data 21285742 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 21285742 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 21285744 # number of overall misses
system.cpu.dcache.overall_misses::total 21285744 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 411945425500 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 411945425500 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 148954509432 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 148954509432 # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 196500 # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total 196500 # number of LoadLockedReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 560899934932 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 560899934932 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 560899934932 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 560899934932 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 486775913 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 486775913 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 172586047 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 172586047 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::cpu.data 2 # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::total 2 # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 61 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total 61 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data 61 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total 61 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 659361960 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 659361960 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 659361962 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 659361962 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.035783 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.035783 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.022409 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.022409 # miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 1 # miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::total 1 # miss rate for SoftPFReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.065574 # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.065574 # miss rate for LoadLockedReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.032282 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.032282 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.032282 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.032282 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 23650.137442 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 23650.137442 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38515.094624 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 38515.094624 # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 49125 # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 49125 # average LoadLockedReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 26350.969345 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 26350.969345 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 26350.966869 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 26350.966869 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 20530392 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 3397643 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 943594 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 67194 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs 21.757654 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets 50.564678 # average number of cycles each access was blocked
system.cpu.dcache.writebacks::writebacks 17003710 # number of writebacks
system.cpu.dcache.writebacks::total 17003710 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 3151672 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 3151672 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1129843 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 1129843 # number of WriteReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 4 # number of LoadLockedReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::total 4 # number of LoadLockedReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data 4281515 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 4281515 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 4281515 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 4281515 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 14266638 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 14266638 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2737589 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 2737589 # number of WriteReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1 # number of SoftPFReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::total 1 # number of SoftPFReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 17004227 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 17004227 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 17004228 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 17004228 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 331755520500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 331755520500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 115729212265 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 115729212265 # number of WriteReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 68000 # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 68000 # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 447484732765 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 447484732765 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 447484800765 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 447484800765 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.029308 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.029308 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015862 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015862 # mshr miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.500000 # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.500000 # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025789 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.025789 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025789 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.025789 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 23253.938349 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 23253.938349 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 42274.136938 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 42274.136938 # average WriteReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 68000 # average SoftPFReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 68000 # average SoftPFReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26316.087921 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 26316.087921 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26316.090373 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 26316.090373 # average overall mshr miss latency
system.cpu.icache.tags.replacements 589 # number of replacements
system.cpu.icache.tags.tagsinuse 444.836642 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 656966815 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 1075 # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs 611131.920930 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst 444.836642 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.868822 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.868822 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024 486 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0 31 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1 14 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::4 441 # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024 0.949219 # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses 1313937945 # Number of tag accesses
system.cpu.icache.tags.data_accesses 1313937945 # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst 656966815 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 656966815 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 656966815 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 656966815 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 656966815 # number of overall hits
system.cpu.icache.overall_hits::total 656966815 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 1620 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 1620 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 1620 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 1620 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 1620 # number of overall misses
system.cpu.icache.overall_misses::total 1620 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 98788987 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 98788987 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 98788987 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 98788987 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 98788987 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 98788987 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 656968435 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 656968435 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 656968435 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 656968435 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 656968435 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 656968435 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000002 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.000002 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.000002 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.000002 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.000002 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.000002 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 60980.856173 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 60980.856173 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 60980.856173 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 60980.856173 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 60980.856173 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 60980.856173 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 17260 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 439 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 183 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 8 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs 94.316940 # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets 54.875000 # average number of cycles each access was blocked
system.cpu.icache.writebacks::writebacks 589 # number of writebacks
system.cpu.icache.writebacks::total 589 # number of writebacks
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 544 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total 544 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst 544 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total 544 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst 544 # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total 544 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1076 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 1076 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 1076 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 1076 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 1076 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 1076 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 73759491 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 73759491 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 73759491 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 73759491 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 73759491 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 73759491 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000002 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.000002 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.000002 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 68549.712825 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 68549.712825 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 68549.712825 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 68549.712825 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 68549.712825 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 68549.712825 # average overall mshr miss latency
system.cpu.l2cache.prefetcher.num_hwpf_issued 11611376 # number of hwpf issued
system.cpu.l2cache.prefetcher.pfIdentified 11640224 # number of prefetch candidates identified
system.cpu.l2cache.prefetcher.pfBufferHit 19566 # number of redundant prefetches already in prefetch queue
system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
system.cpu.l2cache.prefetcher.pfSpanPage 4656640 # number of prefetches not generated due to page crossing
system.cpu.l2cache.tags.replacements 4706089 # number of replacements
system.cpu.l2cache.tags.tagsinuse 16099.754607 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 22829126 # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs 4722015 # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs 4.834615 # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle 54111720000 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks 13098.345143 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 2.290302 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 2999.119162 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks 0.799460 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data 0.000140 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.183052 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total 0.982651 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1022 829 # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_blocks::1024 15097 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1022::0 2 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1022::1 636 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1022::3 191 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 453 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 2943 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 4353 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5523 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 1825 # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1022 0.050598 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.921448 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 552242422 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 552242422 # Number of data accesses
system.cpu.l2cache.WritebackDirty_hits::writebacks 4833112 # number of WritebackDirty hits
system.cpu.l2cache.WritebackDirty_hits::total 4833112 # number of WritebackDirty hits
system.cpu.l2cache.WritebackClean_hits::writebacks 12149903 # number of WritebackClean hits
system.cpu.l2cache.WritebackClean_hits::total 12149903 # number of WritebackClean hits
system.cpu.l2cache.ReadExReq_hits::cpu.data 1757087 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total 1757087 # number of ReadExReq hits
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 56 # number of ReadCleanReq hits
system.cpu.l2cache.ReadCleanReq_hits::total 56 # number of ReadCleanReq hits
system.cpu.l2cache.ReadSharedReq_hits::cpu.data 11522367 # number of ReadSharedReq hits
system.cpu.l2cache.ReadSharedReq_hits::total 11522367 # number of ReadSharedReq hits
system.cpu.l2cache.demand_hits::cpu.inst 56 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data 13279454 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 13279510 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst 56 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data 13279454 # number of overall hits
system.cpu.l2cache.overall_hits::total 13279510 # number of overall hits
system.cpu.l2cache.UpgradeReq_misses::cpu.data 6 # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_misses::total 6 # number of UpgradeReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data 980546 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 980546 # number of ReadExReq misses
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 1020 # number of ReadCleanReq misses
system.cpu.l2cache.ReadCleanReq_misses::total 1020 # number of ReadCleanReq misses
system.cpu.l2cache.ReadSharedReq_misses::cpu.data 2744222 # number of ReadSharedReq misses
system.cpu.l2cache.ReadSharedReq_misses::total 2744222 # number of ReadSharedReq misses
system.cpu.l2cache.demand_misses::cpu.inst 1020 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 3724768 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 3725788 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst 1020 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 3724768 # number of overall misses
system.cpu.l2cache.overall_misses::total 3725788 # number of overall misses
system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 121000 # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::total 121000 # number of UpgradeReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 99083213500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 99083213500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 72272000 # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::total 72272000 # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 234079710000 # number of ReadSharedReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::total 234079710000 # number of ReadSharedReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 72272000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 333162923500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 333235195500 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 72272000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 333162923500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 333235195500 # number of overall miss cycles
system.cpu.l2cache.WritebackDirty_accesses::writebacks 4833112 # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackDirty_accesses::total 4833112 # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::writebacks 12149903 # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::total 12149903 # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::cpu.data 6 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::total 6 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data 2737633 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 2737633 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 1076 # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::total 1076 # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 14266589 # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::total 14266589 # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst 1076 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 17004222 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 17005298 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 1076 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 17004222 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 17005298 # number of overall (read+write) accesses
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 1 # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.358173 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 0.358173 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.947955 # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.947955 # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.192353 # miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.192353 # miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.947955 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.219050 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.219096 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.947955 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.219050 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.219096 # miss rate for overall accesses
system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 20166.666667 # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 20166.666667 # average UpgradeReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 101049.021158 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 101049.021158 # average ReadExReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 70854.901961 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 70854.901961 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 85299.115742 # average ReadSharedReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 85299.115742 # average ReadSharedReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 70854.901961 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 89445.281827 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 89440.192383 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 70854.901961 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 89445.281827 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 89440.192383 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 53 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 1 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs 53 # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.unused_prefetches 56900 # number of HardPF blocks evicted w/o reference
system.cpu.l2cache.writebacks::writebacks 1635896 # number of writebacks
system.cpu.l2cache.writebacks::total 1635896 # number of writebacks
system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 3915 # number of ReadExReq MSHR hits
system.cpu.l2cache.ReadExReq_mshr_hits::total 3915 # number of ReadExReq MSHR hits
system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 1 # number of ReadCleanReq MSHR hits
system.cpu.l2cache.ReadCleanReq_mshr_hits::total 1 # number of ReadCleanReq MSHR hits
system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 45253 # number of ReadSharedReq MSHR hits
system.cpu.l2cache.ReadSharedReq_mshr_hits::total 45253 # number of ReadSharedReq MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.data 49168 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::total 49169 # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.data 49168 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::total 49169 # number of overall MSHR hits
system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 1145204 # number of HardPFReq MSHR misses
system.cpu.l2cache.HardPFReq_mshr_misses::total 1145204 # number of HardPFReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 6 # number of UpgradeReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::total 6 # number of UpgradeReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 976631 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 976631 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 1019 # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::total 1019 # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 2698969 # number of ReadSharedReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::total 2698969 # number of ReadSharedReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 1019 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 3675600 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 3676619 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 1019 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 3675600 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 1145204 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 4821823 # number of overall MSHR misses
system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 72434619378 # number of HardPFReq MSHR miss cycles
system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 72434619378 # number of HardPFReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 85000 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 85000 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 92854351000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 92854351000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 66085000 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 66085000 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 215091513500 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 215091513500 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 66085000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 307945864500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 308011949500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 66085000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 307945864500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 72434619378 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 380446568878 # number of overall MSHR miss cycles
system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses
system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.356743 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.356743 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.947026 # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.947026 # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.189181 # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.189181 # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.947026 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.216158 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.216204 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.947026 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.216158 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.283548 # mshr miss rate for overall accesses
system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 63250.407244 # average HardPFReq mshr miss latency
system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 63250.407244 # average HardPFReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 14166.666667 # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 14166.666667 # average UpgradeReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 95076.186400 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 95076.186400 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 64852.796860 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 64852.796860 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 79693.954803 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 79693.954803 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64852.796860 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 83781.114512 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 83775.868400 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64852.796860 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 83781.114512 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 63250.407244 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 78900.981823 # average overall mshr miss latency
system.cpu.toL2Bus.snoop_filter.tot_requests 34009604 # Total number of requests made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_requests 17004315 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 21284 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.snoop_filter.tot_snoops 2918086 # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2899299 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 18787 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.trans_dist::ReadResp 14267664 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackDirty 6469008 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackClean 12171187 # Transaction distribution
system.cpu.toL2Bus.trans_dist::CleanEvict 5770180 # Transaction distribution
system.cpu.toL2Bus.trans_dist::HardPFReq 1436414 # Transaction distribution
system.cpu.toL2Bus.trans_dist::HardPFResp 9 # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeReq 6 # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeResp 6 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 2737633 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 2737633 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadCleanReq 1076 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadSharedReq 14266589 # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2740 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 51012175 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 51014915 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 106496 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2176508224 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total 2176614720 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops 8842499 # Total snoops (count)