system.cpu.iew.wb_sent 99693752 # cumulative count of insts sent to commit
system.cpu.iew.wb_count 99608605 # cumulative count of insts written-back
system.cpu.iew.wb_producers 59691637 # num instructions producing a value
system.cpu.iew.wb_consumers 95527463 # num instructions consuming a value
system.cpu.iew.wb_rate 0.855758 # insts written-back per cycle
system.cpu.iew.wb_fanout 0.624864 # average fanout of values written-back
system.cpu.commit.commitSquashedInsts 17362842 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 8218 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts 823674 # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples 113658017 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 0.801119 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 1.737711 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0 77235221 67.95% 67.95% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 18611593 16.38% 84.33% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 7151823 6.29% 90.62% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 3469408 3.05% 93.67% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4 1644636 1.45% 95.12% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5 541902 0.48% 95.60% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6 703188 0.62% 96.22% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7 178974 0.16% 96.37% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8 4121272 3.63% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total 113658017 # Number of insts commited each cycle
system.cpu.commit.committedInsts 90602408 # Number of instructions committed
system.cpu.commit.committedOps 91053639 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.refs 27220755 # Number of memory references committed
system.cpu.commit.loads 22475911 # Number of loads committed
system.cpu.commit.membars 3888 # Number of memory barriers committed
system.cpu.commit.branches 18732305 # Number of branches committed
system.cpu.commit.fp_insts 48 # Number of committed floating point instructions.
system.cpu.commit.int_insts 72326352 # Number of committed integer instructions.
system.cpu.commit.function_calls 56148 # Number of function calls committed.
system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
system.cpu.commit.op_class_0::IntAlu 63822387 70.09% 70.09% # Class of committed instruction
system.cpu.commit.op_class_0::IntMult 10474 0.01% 70.10% # Class of committed instruction
system.cpu.commit.op_class_0::IntDiv 0 0.00% 70.10% # Class of committed instruction
system.cpu.commit.op_class_0::FloatAdd 0 0.00% 70.10% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCmp 0 0.00% 70.10% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCvt 0 0.00% 70.10% # Class of committed instruction
system.cpu.commit.op_class_0::FloatMult 0 0.00% 70.10% # Class of committed instruction
system.cpu.commit.op_class_0::FloatDiv 0 0.00% 70.10% # Class of committed instruction
system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 70.10% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAdd 0 0.00% 70.10% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 70.10% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAlu 0 0.00% 70.10% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCmp 0 0.00% 70.10% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCvt 0 0.00% 70.10% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMisc 0 0.00% 70.10% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMult 0 0.00% 70.10% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 70.10% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShift 0 0.00% 70.10% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 70.10% # Class of committed instruction
system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 70.10% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 70.10% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 70.10% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 70.10% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCvt 6 0.00% 70.10% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 70.10% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMisc 15 0.00% 70.10% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 70.10% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMultAcc 2 0.00% 70.10% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 70.10% # Class of committed instruction
system.cpu.commit.op_class_0::MemRead 22475911 24.68% 94.79% # Class of committed instruction
system.cpu.commit.op_class_0::MemWrite 4744844 5.21% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::total 91053639 # Class of committed instruction
system.cpu.commit.bw_lim_events 4121272 # number cycles where commit BW limit reached
system.cpu.rob.rob_reads 217947492 # The number of ROB reads
system.cpu.rob.rob_writes 219521309 # The number of ROB writes
system.cpu.timesIdled 570 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 52283 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 90589799 # Number of Instructions Simulated
system.cpu.committedOps 91041030 # Number of Ops (including micro ops) Simulated
system.cpu.cpi 1.284891 # CPI: Cycles Per Instruction
system.cpu.cpi_total 1.284891 # CPI: Total CPI of All Threads
system.cpu.ipc 0.778276 # IPC: Instructions Per Cycle
system.cpu.ipc_total 0.778276 # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads 108097873 # number of integer regfile reads
system.cpu.int_regfile_writes 58692304 # number of integer regfile writes
system.cpu.fp_regfile_reads 59 # number of floating regfile reads
system.cpu.fp_regfile_writes 96 # number of floating regfile writes
system.cpu.cc_regfile_reads 369004699 # number of cc regfile reads
system.cpu.cc_regfile_writes 58686555 # number of cc regfile writes
system.cpu.misc_regfile_reads 28410220 # number of misc regfile reads
system.cpu.misc_regfile_writes 7784 # number of misc regfile writes
system.cpu.dcache.tags.replacements 5470634 # number of replacements
system.cpu.dcache.tags.tagsinuse 511.784091 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 18249365 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 5471146 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 3.335565 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 35796500 # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data 511.784091 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.999578 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.999578 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0 344 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1 168 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 61906904 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 61906904 # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data 13887331 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 13887331 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 4353747 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 4353747 # number of WriteReq hits
system.cpu.dcache.SoftPFReq_hits::cpu.data 522 # number of SoftPFReq hits
system.cpu.dcache.SoftPFReq_hits::total 522 # number of SoftPFReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data 3872 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total 3872 # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data 3887 # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total 3887 # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data 18241078 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 18241078 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 18241600 # number of overall hits
system.cpu.dcache.overall_hits::total 18241600 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 9587264 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 9587264 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 381234 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 381234 # number of WriteReq misses
system.cpu.dcache.SoftPFReq_misses::cpu.data 7 # number of SoftPFReq misses
system.cpu.dcache.SoftPFReq_misses::total 7 # number of SoftPFReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.data 15 # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total 15 # number of LoadLockedReq misses
system.cpu.dcache.demand_misses::cpu.data 9968498 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 9968498 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 9968505 # number of overall misses
system.cpu.dcache.overall_misses::total 9968505 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 88773272500 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 88773272500 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 4000795875 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 4000795875 # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 291000 # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total 291000 # number of LoadLockedReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 92774068375 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 92774068375 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 92774068375 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 92774068375 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 23474595 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 23474595 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 4734981 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 4734981 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::cpu.data 529 # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::total 529 # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3887 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total 3887 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data 3887 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total 3887 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 28209576 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 28209576 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 28210105 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 28210105 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.408410 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.408410 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.080514 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.080514 # miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.013233 # miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::total 0.013233 # miss rate for SoftPFReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.003859 # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.003859 # miss rate for LoadLockedReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.353373 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.353373 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.353366 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.353366 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 9259.500156 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 9259.500156 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 10494.331238 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 10494.331238 # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 19400 # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 19400 # average LoadLockedReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 9306.724882 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 9306.724882 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 9306.718347 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 9306.718347 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 329915 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 108865 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 121409 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 12838 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs 2.717385 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets 8.479903 # average number of cycles each access was blocked
system.cpu.dcache.writebacks::writebacks 5470634 # number of writebacks
system.cpu.dcache.writebacks::total 5470634 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 4338603 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 4338603 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 158750 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 158750 # number of WriteReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 15 # number of LoadLockedReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::total 15 # number of LoadLockedReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data 4497353 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 4497353 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 4497353 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 4497353 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 5248661 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 5248661 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 222484 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 222484 # number of WriteReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 4 # number of SoftPFReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::total 4 # number of SoftPFReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 5471145 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 5471145 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 5471149 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 5471149 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 43288788000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 43288788000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2285573254 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 2285573254 # number of WriteReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 214500 # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 214500 # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 45574361254 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 45574361254 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 45574575754 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 45574575754 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.223589 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.223589 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.046987 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.046987 # mshr miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.007561 # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.007561 # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.193946 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.193946 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.193943 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.193943 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 8247.586956 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 8247.586956 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 10272.978075 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 10272.978075 # average WriteReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 53625 # average SoftPFReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 53625 # average SoftPFReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 8329.949445 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 8329.949445 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 8329.982560 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 8329.982560 # average overall mshr miss latency
system.cpu.icache.tags.replacements 447 # number of replacements
system.cpu.icache.tags.tagsinuse 427.448157 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 32273898 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 904 # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs 35701.214602 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst 427.448157 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.834860 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.834860 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024 457 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0 53 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::2 51 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::3 18 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::4 335 # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024 0.892578 # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses 64550990 # Number of tag accesses
system.cpu.icache.tags.data_accesses 64550990 # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst 32273898 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 32273898 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 32273898 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 32273898 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 32273898 # number of overall hits
system.cpu.icache.overall_hits::total 32273898 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 1145 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 1145 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 1145 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 1145 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 1145 # number of overall misses
system.cpu.icache.overall_misses::total 1145 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 60302481 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 60302481 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 60302481 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 60302481 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 60302481 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 60302481 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 32275043 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 32275043 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 32275043 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 32275043 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 32275043 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 32275043 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000035 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.000035 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.000035 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.000035 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.000035 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.000035 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 52665.922271 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 52665.922271 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 52665.922271 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 52665.922271 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 52665.922271 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 52665.922271 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 18953 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 107 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 219 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 5 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs 86.543379 # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets 21.400000 # average number of cycles each access was blocked
system.cpu.icache.writebacks::writebacks 447 # number of writebacks
system.cpu.icache.writebacks::total 447 # number of writebacks
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 240 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total 240 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst 240 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total 240 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst 240 # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total 240 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 905 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 905 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 905 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 905 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 905 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 905 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 49734485 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 49734485 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 49734485 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 49734485 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 49734485 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 49734485 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000028 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000028 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000028 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.000028 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000028 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.000028 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 54955.232044 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 54955.232044 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 54955.232044 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 54955.232044 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 54955.232044 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 54955.232044 # average overall mshr miss latency
system.cpu.l2cache.prefetcher.num_hwpf_issued 4981065 # number of hwpf issued
system.cpu.l2cache.prefetcher.pfIdentified 5296247 # number of prefetch candidates identified
system.cpu.l2cache.prefetcher.pfBufferHit 274020 # number of redundant prefetches already in prefetch queue
system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
system.cpu.l2cache.prefetcher.pfSpanPage 14074841 # number of prefetches not generated due to page crossing
system.cpu.l2cache.tags.replacements 248 # number of replacements
system.cpu.l2cache.tags.tagsinuse 11235.818499 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 5318374 # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs 14915 # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs 356.578880 # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks 11061.516911 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 174.301588 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks 0.675141 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.010639 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total 0.685780 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1022 181 # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_blocks::1024 14486 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1022::1 8 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1022::2 3 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1022::3 2 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1022::4 168 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 469 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 3489 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 9544 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 100 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 884 # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1022 0.011047 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.884155 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 180510207 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 180510207 # Number of data accesses
system.cpu.l2cache.WritebackDirty_hits::writebacks 5451171 # number of WritebackDirty hits
system.cpu.l2cache.WritebackDirty_hits::total 5451171 # number of WritebackDirty hits
system.cpu.l2cache.WritebackClean_hits::writebacks 17033 # number of WritebackClean hits
system.cpu.l2cache.WritebackClean_hits::total 17033 # number of WritebackClean hits
system.cpu.l2cache.ReadExReq_hits::cpu.data 226019 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total 226019 # number of ReadExReq hits
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 210 # number of ReadCleanReq hits
system.cpu.l2cache.ReadCleanReq_hits::total 210 # number of ReadCleanReq hits
system.cpu.l2cache.ReadSharedReq_hits::cpu.data 5243562 # number of ReadSharedReq hits
system.cpu.l2cache.ReadSharedReq_hits::total 5243562 # number of ReadSharedReq hits
system.cpu.l2cache.demand_hits::cpu.inst 210 # number of demand (read+write) hits
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system.cpu.l2cache.overall_hits::cpu.inst 210 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data 5469581 # number of overall hits
system.cpu.l2cache.overall_hits::total 5469791 # number of overall hits
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system.cpu.l2cache.UpgradeReq_misses::total 3 # number of UpgradeReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data 500 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 500 # number of ReadExReq misses
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system.cpu.l2cache.ReadCleanReq_misses::total 695 # number of ReadCleanReq misses
system.cpu.l2cache.ReadSharedReq_misses::cpu.data 1065 # number of ReadSharedReq misses
system.cpu.l2cache.ReadSharedReq_misses::total 1065 # number of ReadSharedReq misses
system.cpu.l2cache.demand_misses::cpu.inst 695 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 1565 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 2260 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst 695 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 1565 # number of overall misses
system.cpu.l2cache.overall_misses::total 2260 # number of overall misses
system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 59500 # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::total 59500 # number of UpgradeReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 41259500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 41259500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 47414000 # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::total 47414000 # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 71274500 # number of ReadSharedReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::total 71274500 # number of ReadSharedReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 47414000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 112534000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 159948000 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 47414000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 112534000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 159948000 # number of overall miss cycles
system.cpu.l2cache.WritebackDirty_accesses::writebacks 5451171 # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackDirty_accesses::total 5451171 # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::writebacks 17033 # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::total 17033 # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::cpu.data 3 # number of UpgradeReq accesses(hits+misses)
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system.cpu.l2cache.ReadExReq_accesses::total 226519 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 905 # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::total 905 # number of ReadCleanReq accesses(hits+misses)
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system.cpu.l2cache.ReadSharedReq_accesses::total 5244627 # number of ReadSharedReq accesses(hits+misses)
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system.cpu.l2cache.overall_accesses::cpu.inst 905 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 5471146 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 5472051 # number of overall (read+write) accesses
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system.cpu.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses
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system.cpu.l2cache.ReadExReq_miss_rate::total 0.002207 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.767956 # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.767956 # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.000203 # miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.000203 # miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.767956 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.000286 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.000413 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.767956 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.000286 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.000413 # miss rate for overall accesses
system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 19833.333333 # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 19833.333333 # average UpgradeReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 82519 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 82519 # average ReadExReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 68221.582734 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 68221.582734 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 66924.413146 # average ReadSharedReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 66924.413146 # average ReadSharedReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68221.582734 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 71906.709265 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 70773.451327 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68221.582734 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 71906.709265 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 70773.451327 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.unused_prefetches 7 # number of HardPF blocks evicted w/o reference
system.cpu.l2cache.writebacks::writebacks 175 # number of writebacks
system.cpu.l2cache.writebacks::total 175 # number of writebacks
system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 158 # number of ReadExReq MSHR hits
system.cpu.l2cache.ReadExReq_mshr_hits::total 158 # number of ReadExReq MSHR hits
system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 1 # number of ReadCleanReq MSHR hits
system.cpu.l2cache.ReadCleanReq_mshr_hits::total 1 # number of ReadCleanReq MSHR hits
system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 37 # number of ReadSharedReq MSHR hits
system.cpu.l2cache.ReadSharedReq_mshr_hits::total 37 # number of ReadSharedReq MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.data 195 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::total 196 # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.data 195 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::total 196 # number of overall MSHR hits
system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 316084 # number of HardPFReq MSHR misses
system.cpu.l2cache.HardPFReq_mshr_misses::total 316084 # number of HardPFReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 3 # number of UpgradeReq MSHR misses
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system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 342 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 342 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 694 # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::total 694 # number of ReadCleanReq MSHR misses
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system.cpu.l2cache.overall_mshr_misses::cpu.inst 694 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 1370 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 316084 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 318148 # number of overall MSHR misses
system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 852614747 # number of HardPFReq MSHR miss cycles
system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 852614747 # number of HardPFReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 41500 # number of UpgradeReq MSHR miss cycles
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system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 32745000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 32745000 # number of ReadExReq MSHR miss cycles
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system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 43196500 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 63614500 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 63614500 # number of ReadSharedReq MSHR miss cycles
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system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 43196500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 96359500 # number of overall MSHR miss cycles
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system.cpu.l2cache.overall_mshr_miss_latency::total 992170747 # number of overall MSHR miss cycles
system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses
system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.001510 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.001510 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.766851 # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.766851 # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.000196 # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.000196 # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.766851 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.000250 # mshr miss rate for demand accesses
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system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.766851 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.000250 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.058141 # mshr miss rate for overall accesses
system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 2697.430895 # average HardPFReq mshr miss latency
system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 2697.430895 # average HardPFReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 13833.333333 # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 13833.333333 # average UpgradeReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 95745.614035 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 95745.614035 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 62242.795389 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 62242.795389 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 61881.809339 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 61881.809339 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62242.795389 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 70335.401460 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67614.341085 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62242.795389 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 70335.401460 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 2697.430895 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 3118.582380 # average overall mshr miss latency
system.cpu.toL2Bus.snoop_filter.tot_requests 10943135 # Total number of requests made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_requests 5471097 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 2877 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.snoop_filter.tot_snoops 303361 # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 302576 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 785 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.trans_dist::ReadResp 5245531 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackDirty 5451346 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackClean 19910 # Transaction distribution
system.cpu.toL2Bus.trans_dist::CleanEvict 1794 # Transaction distribution
system.cpu.toL2Bus.trans_dist::HardPFReq 317966 # Transaction distribution
system.cpu.toL2Bus.trans_dist::HardPFResp 4 # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeReq 3 # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeResp 3 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 226519 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 226519 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadCleanReq 905 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadSharedReq 5244627 # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2256 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 16412936 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 16415192 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 86464 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 700274176 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total 700360640 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops 319939 # Total snoops (count)