gem5/tests/long/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  2.582494                       # Number of seconds simulated
sim_ticks                                2582494395500                       # Number of ticks simulated
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                  65512                       # Simulator instruction rate (inst/s)
host_tick_rate                             2118472138                       # Simulator tick rate (ticks/s)
host_mem_usage                                 384260                       # Number of bytes of host memory used
host_seconds                                  1219.04                       # Real time elapsed on the host
sim_insts                                    79862069                       # Number of instructions simulated
system.l2c.replacements                        132200                       # number of replacements
system.l2c.tagsinuse                     27582.989225                       # Cycle average of tags in use
system.l2c.total_refs                         1817822                       # Total number of references to valid blocks.
system.l2c.sampled_refs                        162144                       # Sample count of references to valid blocks.
system.l2c.avg_refs                         11.211158                       # Average number of references to valid blocks.
system.l2c.warmup_cycle                             0                       # Cycle when the warmup percentage was hit.
system.l2c.occ_blocks::0                  5000.897751                       # Average occupied blocks per context
system.l2c.occ_blocks::1                  7176.831699                       # Average occupied blocks per context
system.l2c.occ_blocks::2                 15405.259775                       # Average occupied blocks per context
system.l2c.occ_percent::0                    0.076308                       # Average percentage of cache occupancy
system.l2c.occ_percent::1                    0.109510                       # Average percentage of cache occupancy
system.l2c.occ_percent::2                    0.235066                       # Average percentage of cache occupancy
system.l2c.ReadReq_hits::0                     738573                       # number of ReadReq hits
system.l2c.ReadReq_hits::1                     628212                       # number of ReadReq hits
system.l2c.ReadReq_hits::2                     178875                       # number of ReadReq hits
system.l2c.ReadReq_hits::total                1545660                       # number of ReadReq hits
system.l2c.Writeback_hits::0                   598786                       # number of Writeback hits
system.l2c.Writeback_hits::total               598786                       # number of Writeback hits
system.l2c.UpgradeReq_hits::0                    1039                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::1                    1048                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total                2087                       # number of UpgradeReq hits
system.l2c.SCUpgradeReq_hits::0                   175                       # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::1                   451                       # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::total               626                       # number of SCUpgradeReq hits
system.l2c.ReadExReq_hits::0                    58347                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::1                    39083                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::total                97430                       # number of ReadExReq hits
system.l2c.demand_hits::0                      796920                       # number of demand (read+write) hits
system.l2c.demand_hits::1                      667295                       # number of demand (read+write) hits
system.l2c.demand_hits::2                      178875                       # number of demand (read+write) hits
system.l2c.demand_hits::total                 1643090                       # number of demand (read+write) hits
system.l2c.overall_hits::0                     796920                       # number of overall hits
system.l2c.overall_hits::1                     667295                       # number of overall hits
system.l2c.overall_hits::2                     178875                       # number of overall hits
system.l2c.overall_hits::total                1643090                       # number of overall hits
system.l2c.ReadReq_misses::0                    19694                       # number of ReadReq misses
system.l2c.ReadReq_misses::1                    20569                       # number of ReadReq misses
system.l2c.ReadReq_misses::2                      168                       # number of ReadReq misses
system.l2c.ReadReq_misses::total                40431                       # number of ReadReq misses
system.l2c.UpgradeReq_misses::0                  7390                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::1                  3840                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total             11230                       # number of UpgradeReq misses
system.l2c.SCUpgradeReq_misses::0                 864                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::1                 454                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::total            1318                       # number of SCUpgradeReq misses
system.l2c.ReadExReq_misses::0                  97999                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::1                  50217                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::total             148216                       # number of ReadExReq misses
system.l2c.demand_misses::0                    117693                       # number of demand (read+write) misses
system.l2c.demand_misses::1                     70786                       # number of demand (read+write) misses
system.l2c.demand_misses::2                       168                       # number of demand (read+write) misses
system.l2c.demand_misses::total                188647                       # number of demand (read+write) misses
system.l2c.overall_misses::0                   117693                       # number of overall misses
system.l2c.overall_misses::1                    70786                       # number of overall misses
system.l2c.overall_misses::2                      168                       # number of overall misses
system.l2c.overall_misses::total               188647                       # number of overall misses
system.l2c.ReadReq_miss_latency            2112279500                       # number of ReadReq miss cycles
system.l2c.UpgradeReq_miss_latency           61500500                       # number of UpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency          8037000                       # number of SCUpgradeReq miss cycles
system.l2c.ReadExReq_miss_latency          7780237999                       # number of ReadExReq miss cycles
system.l2c.demand_miss_latency             9892517499                       # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency            9892517499                       # number of overall miss cycles
system.l2c.ReadReq_accesses::0                 758267                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::1                 648781                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::2                 179043                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::total            1586091                       # number of ReadReq accesses(hits+misses)
system.l2c.Writeback_accesses::0               598786                       # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::total           598786                       # number of Writeback accesses(hits+misses)
system.l2c.UpgradeReq_accesses::0                8429                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::1                4888                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total           13317                       # number of UpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::0              1039                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::1               905                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::total          1944                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::0               156346                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::1                89300                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total           245646                       # number of ReadExReq accesses(hits+misses)
system.l2c.demand_accesses::0                  914613                       # number of demand (read+write) accesses
system.l2c.demand_accesses::1                  738081                       # number of demand (read+write) accesses
system.l2c.demand_accesses::2                  179043                       # number of demand (read+write) accesses
system.l2c.demand_accesses::total             1831737                       # number of demand (read+write) accesses
system.l2c.overall_accesses::0                 914613                       # number of overall (read+write) accesses
system.l2c.overall_accesses::1                 738081                       # number of overall (read+write) accesses
system.l2c.overall_accesses::2                 179043                       # number of overall (read+write) accesses
system.l2c.overall_accesses::total            1831737                       # number of overall (read+write) accesses
system.l2c.ReadReq_miss_rate::0              0.025972                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::1              0.031704                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::2              0.000938                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::total          0.058615                       # miss rate for ReadReq accesses
system.l2c.UpgradeReq_miss_rate::0           0.876735                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::1           0.785597                       # miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::0         0.831569                       # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::1         0.501657                       # miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_miss_rate::0            0.626808                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::1            0.562340                       # miss rate for ReadExReq accesses
system.l2c.demand_miss_rate::0               0.128681                       # miss rate for demand accesses
system.l2c.demand_miss_rate::1               0.095905                       # miss rate for demand accesses
system.l2c.demand_miss_rate::2               0.000938                       # miss rate for demand accesses
system.l2c.demand_miss_rate::total           0.225524                       # miss rate for demand accesses
system.l2c.overall_miss_rate::0              0.128681                       # miss rate for overall accesses
system.l2c.overall_miss_rate::1              0.095905                       # miss rate for overall accesses
system.l2c.overall_miss_rate::2              0.000938                       # miss rate for overall accesses
system.l2c.overall_miss_rate::total          0.225524                       # miss rate for overall accesses
system.l2c.ReadReq_avg_miss_latency::0   107254.976135                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::1   102692.376878                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::2   12573092.261905                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::total 12783039.614917                       # average ReadReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::0  8322.124493                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::1 16015.755208                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::2          inf                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total          inf                       # average UpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::0  9302.083333                       # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::1 17702.643172                       # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::2          inf                       # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::total          inf                       # average SCUpgradeReq miss latency
system.l2c.ReadExReq_avg_miss_latency::0 79390.993775                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::1 154932.353566                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::2          inf                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total          inf                       # average ReadExReq miss latency
system.l2c.demand_avg_miss_latency::0    84053.575820                       # average overall miss latency
system.l2c.demand_avg_miss_latency::1    139752.458099                       # average overall miss latency
system.l2c.demand_avg_miss_latency::2    58884032.732143                       # average overall miss latency
system.l2c.demand_avg_miss_latency::total 59107838.766062                       # average overall miss latency
system.l2c.overall_avg_miss_latency::0   84053.575820                       # average overall miss latency
system.l2c.overall_avg_miss_latency::1   139752.458099                       # average overall miss latency
system.l2c.overall_avg_miss_latency::2   58884032.732143                       # average overall miss latency
system.l2c.overall_avg_miss_latency::total 59107838.766062                       # average overall miss latency
system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs      no_value                       # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
system.l2c.fast_writes                              0                       # number of fast writes performed
system.l2c.cache_copies                             0                       # number of cache copies performed
system.l2c.writebacks                          112847                       # number of writebacks
system.l2c.ReadReq_mshr_hits                       98                       # number of ReadReq MSHR hits
system.l2c.demand_mshr_hits                        98                       # number of demand (read+write) MSHR hits
system.l2c.overall_mshr_hits                       98                       # number of overall MSHR hits
system.l2c.ReadReq_mshr_misses                  40333                       # number of ReadReq MSHR misses
system.l2c.UpgradeReq_mshr_misses               11230                       # number of UpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses              1318                       # number of SCUpgradeReq MSHR misses
system.l2c.ReadExReq_mshr_misses               148216                       # number of ReadExReq MSHR misses
system.l2c.demand_mshr_misses                  188549                       # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses                 188549                       # number of overall MSHR misses
system.l2c.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
system.l2c.ReadReq_mshr_miss_latency       1616144000                       # number of ReadReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency     449664000                       # number of UpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency     52753500                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency     5939088499                       # number of ReadExReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency        7555232499                       # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency       7555232499                       # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_uncacheable_latency 131965191500                       # number of ReadReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency  32542078084                       # number of WriteReq MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency 164507269584                       # number of overall MSHR uncacheable cycles
system.l2c.ReadReq_mshr_miss_rate::0         0.053191                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::1         0.062167                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::2         0.225270                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::total     0.340628                       # mshr miss rate for ReadReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::0      1.332305                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::1      2.297463                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::2           inf                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total          inf                       # mshr miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::0     1.268527                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::1     1.456354                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::2          inf                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::total          inf                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::0       0.948000                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::1       1.659754                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::2            inf                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total          inf                       # mshr miss rate for ReadExReq accesses
system.l2c.demand_mshr_miss_rate::0          0.206152                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::1          0.255458                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::2          1.053093                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total      1.514703                       # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::0         0.206152                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::1         0.255458                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::2         1.053093                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total     1.514703                       # mshr miss rate for overall accesses
system.l2c.ReadReq_avg_mshr_miss_latency 40070.017108                       # average ReadReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency 40041.317898                       # average UpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency 40025.417299                       # average SCUpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency 40070.495082                       # average ReadExReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency  40070.392837                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency 40070.392837                       # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency          inf                       # average ReadReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency          inf                       # average WriteReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency          inf                       # average overall mshr uncacheable latency
system.l2c.mshr_cap_events                          0                       # number of times MSHR cap was activated
system.l2c.soft_prefetch_mshr_full                  0                       # number of mshr full events for SW prefetching instrutions
system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
system.cf0.dma_read_full_pages                      0                       # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes                           0                       # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs                             0                       # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages                     0                       # Number of full page size DMA writes.
system.cf0.dma_write_bytes                          0                       # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs                            0                       # Number of DMA write transactions.
system.cpu0.dtb.inst_hits                           0                       # ITB inst hits
system.cpu0.dtb.inst_misses                         0                       # ITB inst misses
system.cpu0.dtb.read_hits                    42404013                       # DTB read hits
system.cpu0.dtb.read_misses                     55271                       # DTB read misses
system.cpu0.dtb.write_hits                    6896316                       # DTB write hits
system.cpu0.dtb.write_misses                    11117                       # DTB write misses
system.cpu0.dtb.flush_tlb                           4                       # Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu0.dtb.flush_tlb_mva_asid               1439                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.dtb.flush_tlb_asid                     63                       # Number of times TLB was flushed by ASID
system.cpu0.dtb.flush_entries                    2702                       # Number of entries that have been flushed from TLB
system.cpu0.dtb.align_faults                    10190                       # Number of TLB faults due to alignment restrictions
system.cpu0.dtb.prefetch_faults                   580                       # Number of TLB faults due to prefetch
system.cpu0.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu0.dtb.perms_faults                     1489                       # Number of TLB faults due to permissions restrictions
system.cpu0.dtb.read_accesses                42459284                       # DTB read accesses
system.cpu0.dtb.write_accesses                6907433                       # DTB write accesses
system.cpu0.dtb.inst_accesses                       0                       # ITB inst accesses
system.cpu0.dtb.hits                         49300329                       # DTB hits
system.cpu0.dtb.misses                          66388                       # DTB misses
system.cpu0.dtb.accesses                     49366717                       # DTB accesses
system.cpu0.itb.inst_hits                     6430047                       # ITB inst hits
system.cpu0.itb.inst_misses                     17344                       # ITB inst misses
system.cpu0.itb.read_hits                           0                       # DTB read hits
system.cpu0.itb.read_misses                         0                       # DTB read misses
system.cpu0.itb.write_hits                          0                       # DTB write hits
system.cpu0.itb.write_misses                        0                       # DTB write misses
system.cpu0.itb.flush_tlb                           4                       # Number of times complete TLB was flushed
system.cpu0.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu0.itb.flush_tlb_mva_asid               1439                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.itb.flush_tlb_asid                     63                       # Number of times TLB was flushed by ASID
system.cpu0.itb.flush_entries                    1577                       # Number of entries that have been flushed from TLB
system.cpu0.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu0.itb.perms_faults                     5810                       # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses                       0                       # DTB read accesses
system.cpu0.itb.write_accesses                      0                       # DTB write accesses
system.cpu0.itb.inst_accesses                 6447391                       # ITB inst accesses
system.cpu0.itb.hits                          6430047                       # DTB hits
system.cpu0.itb.misses                          17344                       # DTB misses
system.cpu0.itb.accesses                      6447391                       # DTB accesses
system.cpu0.numCycles                       352464224                       # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu0.BPredUnit.lookups                 8639262                       # Number of BP lookups
system.cpu0.BPredUnit.condPredicted           6396113                       # Number of conditional branches predicted
system.cpu0.BPredUnit.condIncorrect            634960                       # Number of conditional branches incorrect
system.cpu0.BPredUnit.BTBLookups              7354016                       # Number of BTB lookups
system.cpu0.BPredUnit.BTBHits                 5046946                       # Number of BTB hits
system.cpu0.BPredUnit.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu0.BPredUnit.usedRAS                  806008                       # Number of times the RAS was used to get a target.
system.cpu0.BPredUnit.RASInCorrect             135144                       # Number of incorrect RAS predictions.
system.cpu0.fetch.icacheStallCycles          16864575                       # Number of cycles fetch is stalled on an Icache miss
system.cpu0.fetch.Insts                      45911459                       # Number of instructions fetch has processed
system.cpu0.fetch.Branches                    8639262                       # Number of branches that fetch encountered
system.cpu0.fetch.predictedBranches           5852954                       # Number of branches that fetch has predicted taken
system.cpu0.fetch.Cycles                     11507352                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu0.fetch.SquashCycles                2656909                       # Number of cycles fetch has spent squashing
system.cpu0.fetch.TlbCycles                    105092                       # Number of cycles fetch has spent waiting for tlb
system.cpu0.fetch.BlockedCycles              79183942                       # Number of cycles fetch has spent blocked
system.cpu0.fetch.MiscStallCycles                2005                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu0.fetch.PendingTrapStallCycles       114543                       # Number of stall cycles due to pending traps
system.cpu0.fetch.PendingQuiesceStallCycles       115021                       # Number of stall cycles due to pending quiesce instructions
system.cpu0.fetch.IcacheWaitRetryStallCycles          279                       # Number of stall cycles due to full MSHR
system.cpu0.fetch.CacheLines                  6424056                       # Number of cache lines fetched
system.cpu0.fetch.IcacheSquashes               290090                       # Number of outstanding Icache misses that were squashed
system.cpu0.fetch.ItlbSquashes                   8736                       # Number of outstanding ITLB misses that were squashed
system.cpu0.fetch.rateDist::samples         109741052                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::mean             0.540842                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::stdev            1.794710                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::0                98251365     89.53%     89.53% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::1                 1141553      1.04%     90.57% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::2                 1483062      1.35%     91.92% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::3                 1305311      1.19%     93.11% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::4                 1111109      1.01%     94.12% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::5                  877492      0.80%     94.92% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::6                  783730      0.71%     95.64% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::7                  504789      0.46%     96.10% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::8                 4282641      3.90%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::total           109741052                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.branchRate                 0.024511                       # Number of branch fetches per cycle
system.cpu0.fetch.rate                       0.130258                       # Number of inst fetches per cycle
system.cpu0.decode.IdleCycles                18015904                       # Number of cycles decode is idle
system.cpu0.decode.BlockedCycles             78867966                       # Number of cycles decode is blocked
system.cpu0.decode.RunCycles                 10351735                       # Number of cycles decode is running
system.cpu0.decode.UnblockCycles               744902                       # Number of cycles decode is unblocking
system.cpu0.decode.SquashCycles               1760545                       # Number of cycles decode is squashing
system.cpu0.decode.BranchResolved             1349765                       # Number of times decode resolved a branch
system.cpu0.decode.BranchMispred                89024                       # Number of times decode detected a branch misprediction
system.cpu0.decode.DecodedInsts              56859019                       # Number of instructions handled by decode
system.cpu0.decode.SquashedInsts               296865                       # Number of squashed instructions handled by decode
system.cpu0.rename.SquashCycles               1760545                       # Number of cycles rename is squashing
system.cpu0.rename.IdleCycles                19077781                       # Number of cycles rename is idle
system.cpu0.rename.BlockCycles               33324855                       # Number of cycles rename is blocking
system.cpu0.rename.serializeStallCycles      41068350                       # count of cycles rename stalled for serializing inst
system.cpu0.rename.RunCycles                 10047301                       # Number of cycles rename is running
system.cpu0.rename.UnblockCycles              4462220                       # Number of cycles rename is unblocking
system.cpu0.rename.RenamedInsts              54490886                       # Number of instructions processed by rename
system.cpu0.rename.ROBFullEvents                 1483                       # Number of times rename has blocked due to ROB full
system.cpu0.rename.IQFullEvents                580883                       # Number of times rename has blocked due to IQ full
system.cpu0.rename.LSQFullEvents              3149232                       # Number of times rename has blocked due to LSQ full
system.cpu0.rename.FullRegisterEvents             205                       # Number of times there has been no free registers
system.cpu0.rename.RenamedOperands           54779837                       # Number of destination operands rename has renamed
system.cpu0.rename.RenameLookups            247536349                       # Number of register rename lookups that rename has made
system.cpu0.rename.int_rename_lookups       247487579                       # Number of integer rename lookups
system.cpu0.rename.fp_rename_lookups            48770                       # Number of floating rename lookups
system.cpu0.rename.CommittedMaps             41441157                       # Number of HB maps that are committed
system.cpu0.rename.UndoneMaps                13338679                       # Number of HB maps that are undone due to squashing
system.cpu0.rename.serializingInsts            828868                       # count of serializing insts renamed
system.cpu0.rename.tempSerializingInsts        763855                       # count of temporary serializing insts renamed
system.cpu0.rename.skidInsts                  8500592                       # count of insts added to the skid buffer
system.cpu0.memDep0.insertedLoads            11770384                       # Number of loads inserted to the mem dependence unit.
system.cpu0.memDep0.insertedStores            7686805                       # Number of stores inserted to the mem dependence unit.
system.cpu0.memDep0.conflictingLoads          1443183                       # Number of conflicting loads.
system.cpu0.memDep0.conflictingStores         1570137                       # Number of conflicting stores.
system.cpu0.iq.iqInstsAdded                  50961905                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu0.iq.iqNonSpecInstsAdded            1297752                       # Number of non-speculative instructions added to the IQ
system.cpu0.iq.iqInstsIssued                 80276174                       # Number of instructions issued
system.cpu0.iq.iqSquashedInstsIssued           137636                       # Number of squashed instructions issued
system.cpu0.iq.iqSquashedInstsExamined        9888896                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu0.iq.iqSquashedOperandsExamined     22816025                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu0.iq.iqSquashedNonSpecRemoved        253324                       # Number of squashed non-spec instructions that were removed
system.cpu0.iq.issued_per_cycle::samples    109741052                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::mean        0.731505                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::stdev       1.440076                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::0           80125799     73.01%     73.01% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::1           10111373      9.21%     82.23% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::2            4133530      3.77%     85.99% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::3            3177611      2.90%     88.89% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::4            9954078      9.07%     97.96% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::5            1265279      1.15%     99.11% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::6             670333      0.61%     99.72% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::7             224189      0.20%     99.93% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::8              78860      0.07%    100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::total      109741052                       # Number of insts issued each cycle
system.cpu0.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntAlu                  37808      0.47%      0.47% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntMult                   626      0.01%      0.48% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntDiv                      0      0.00%      0.48% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatAdd                    0      0.00%      0.48% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatCmp                    0      0.00%      0.48% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatCvt                    0      0.00%      0.48% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatMult                   0      0.00%      0.48% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatDiv                    0      0.00%      0.48% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatSqrt                   0      0.00%      0.48% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAdd                     0      0.00%      0.48% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAddAcc                  0      0.00%      0.48% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAlu                     0      0.00%      0.48% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdCmp                     0      0.00%      0.48% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdCvt                     0      0.00%      0.48% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMisc                    0      0.00%      0.48% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMult                    0      0.00%      0.48% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMultAcc                 0      0.00%      0.48% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdShift                   0      0.00%      0.48% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdShiftAcc                0      0.00%      0.48% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdSqrt                    0      0.00%      0.48% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatAdd                0      0.00%      0.48% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatAlu                0      0.00%      0.48% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatCmp                0      0.00%      0.48% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatCvt                0      0.00%      0.48% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatDiv                0      0.00%      0.48% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMisc               0      0.00%      0.48% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMult               0      0.00%      0.48% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMultAcc            0      0.00%      0.48% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatSqrt               0      0.00%      0.48% # attempts to use FU when none available
system.cpu0.iq.fu_full::MemRead               7704393     95.96%     96.44% # attempts to use FU when none available
system.cpu0.iq.fu_full::MemWrite               285533      3.56%    100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
system.cpu0.iq.FU_type_0::No_OpClass            88461      0.11%      0.11% # Type of FU issued
system.cpu0.iq.FU_type_0::IntAlu             29731481     37.04%     37.15% # Type of FU issued
system.cpu0.iq.FU_type_0::IntMult               62351      0.08%     37.22% # Type of FU issued
system.cpu0.iq.FU_type_0::IntDiv                    0      0.00%     37.22% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatAdd                  0      0.00%     37.22% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatCmp                  0      0.00%     37.22% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatCvt                  0      0.00%     37.22% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatMult                 0      0.00%     37.22% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatDiv                  0      0.00%     37.22% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatSqrt                 0      0.00%     37.22% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAdd                   0      0.00%     37.22% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAddAcc                0      0.00%     37.22% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAlu                   0      0.00%     37.22% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdCmp                   0      0.00%     37.22% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdCvt                   0      0.00%     37.22% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMisc                  4      0.00%     37.22% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMult                  0      0.00%     37.22% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMultAcc               0      0.00%     37.22% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdShift                 2      0.00%     37.22% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdShiftAcc              4      0.00%     37.22% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdSqrt                  0      0.00%     37.22% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatAdd              0      0.00%     37.22% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatAlu              0      0.00%     37.22% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatCmp              0      0.00%     37.22% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatCvt              0      0.00%     37.22% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatDiv              0      0.00%     37.22% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMisc          1694      0.00%     37.23% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMult             0      0.00%     37.23% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMultAcc            4      0.00%     37.23% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatSqrt             0      0.00%     37.23% # Type of FU issued
system.cpu0.iq.FU_type_0::MemRead            43135014     53.73%     90.96% # Type of FU issued
system.cpu0.iq.FU_type_0::MemWrite            7257159      9.04%    100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::total              80276174                       # Type of FU issued
system.cpu0.iq.rate                          0.227757                       # Inst issue rate
system.cpu0.iq.fu_busy_cnt                    8028360                       # FU busy when requested
system.cpu0.iq.fu_busy_rate                  0.100009                       # FU busy rate (busy events/executed inst)
system.cpu0.iq.int_inst_queue_reads         278513864                       # Number of integer instruction queue reads
system.cpu0.iq.int_inst_queue_writes         62161443                       # Number of integer instruction queue writes
system.cpu0.iq.int_inst_queue_wakeup_accesses     46668615                       # Number of integer instruction queue wakeup accesses
system.cpu0.iq.fp_inst_queue_reads              11568                       # Number of floating instruction queue reads
system.cpu0.iq.fp_inst_queue_writes              6980                       # Number of floating instruction queue writes
system.cpu0.iq.fp_inst_queue_wakeup_accesses         5172                       # Number of floating instruction queue wakeup accesses
system.cpu0.iq.int_alu_accesses              88210042                       # Number of integer alu accesses
system.cpu0.iq.fp_alu_accesses                   6031                       # Number of floating point alu accesses
system.cpu0.iew.lsq.thread0.forwLoads          399886                       # Number of loads that had data forwarded from stores
system.cpu0.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
system.cpu0.iew.lsq.thread0.squashedLoads      2526229                       # Number of loads squashed
system.cpu0.iew.lsq.thread0.ignoredResponses         5188                       # Number of memory responses ignored because the instruction is squashed
system.cpu0.iew.lsq.thread0.memOrderViolation        20554                       # Number of memory ordering violations
system.cpu0.iew.lsq.thread0.squashedStores       993550                       # Number of stores squashed
system.cpu0.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
system.cpu0.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
system.cpu0.iew.lsq.thread0.rescheduledLoads     32220160                       # Number of loads that were rescheduled
system.cpu0.iew.lsq.thread0.cacheBlocked        13300                       # Number of times an access to memory failed due to the cache being blocked
system.cpu0.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
system.cpu0.iew.iewSquashCycles               1760545                       # Number of cycles IEW is squashing
system.cpu0.iew.iewBlockCycles               25952608                       # Number of cycles IEW is blocking
system.cpu0.iew.iewUnblockCycles               355602                       # Number of cycles IEW is unblocking
system.cpu0.iew.iewDispatchedInsts           52433539                       # Number of instructions dispatched to IQ
system.cpu0.iew.iewDispSquashedInsts           243567                       # Number of squashed instructions skipped by dispatch
system.cpu0.iew.iewDispLoadInsts             11770384                       # Number of dispatched load instructions
system.cpu0.iew.iewDispStoreInsts             7686805                       # Number of dispatched store instructions
system.cpu0.iew.iewDispNonSpecInsts            865740                       # Number of dispatched non-speculative instructions
system.cpu0.iew.iewIQFullEvents                 62160                       # Number of times the IQ has become full, causing a stall
system.cpu0.iew.iewLSQFullEvents                 5553                       # Number of times the LSQ has become full, causing a stall
system.cpu0.iew.memOrderViolationEvents         20554                       # Number of memory order violations
system.cpu0.iew.predictedTakenIncorrect        507509                       # Number of branches that were predicted taken incorrectly
system.cpu0.iew.predictedNotTakenIncorrect       136100                       # Number of branches that were predicted not taken incorrectly
system.cpu0.iew.branchMispredicts              643609                       # Number of branch mispredicts detected at execute
system.cpu0.iew.iewExecutedInsts             79551295                       # Number of executed instructions
system.cpu0.iew.iewExecLoadInsts             42843907                       # Number of load instructions executed
system.cpu0.iew.iewExecSquashedInsts           724879                       # Number of squashed instructions skipped in execute
system.cpu0.iew.exec_swp                            0                       # number of swp insts executed
system.cpu0.iew.exec_nop                       173882                       # number of nop insts executed
system.cpu0.iew.exec_refs                    50011427                       # number of memory reference insts executed
system.cpu0.iew.exec_branches                 6433542                       # Number of branches executed
system.cpu0.iew.exec_stores                   7167520                       # Number of stores executed
system.cpu0.iew.exec_rate                    0.225700                       # Inst execution rate
system.cpu0.iew.wb_sent                      79133797                       # cumulative count of insts sent to commit
system.cpu0.iew.wb_count                     46673787                       # cumulative count of insts written-back
system.cpu0.iew.wb_producers                 24793926                       # num instructions producing a value
system.cpu0.iew.wb_consumers                 46078393                       # num instructions consuming a value
system.cpu0.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
system.cpu0.iew.wb_rate                      0.132421                       # insts written-back per cycle
system.cpu0.iew.wb_fanout                    0.538081                       # average fanout of values written-back
system.cpu0.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu0.commit.commitCommittedInsts      41927345                       # The number of committed instructions
system.cpu0.commit.commitSquashedInsts       10365163                       # The number of squashed insts skipped by commit
system.cpu0.commit.commitNonSpecStalls        1044428                       # The number of times commit has been forced to stall to communicate backwards
system.cpu0.commit.branchMispredicts           567784                       # The number of times a branch was mispredicted
system.cpu0.commit.committed_per_cycle::samples    108024119                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::mean     0.388129                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::stdev     1.248779                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::0     90994296     84.24%     84.24% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::1      9318293      8.63%     92.86% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::2      2453548      2.27%     95.13% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::3      1344047      1.24%     96.38% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::4      1036100      0.96%     97.34% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::5       648919      0.60%     97.94% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::6       654404      0.61%     98.54% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::7       241700      0.22%     98.77% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::8      1332812      1.23%    100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::total    108024119                       # Number of insts commited each cycle
system.cpu0.commit.count                     41927345                       # Number of instructions committed
system.cpu0.commit.swp_count                        0                       # Number of s/w prefetches committed
system.cpu0.commit.refs                      15937410                       # Number of memory references committed
system.cpu0.commit.loads                      9244155                       # Number of loads committed
system.cpu0.commit.membars                     288635                       # Number of memory barriers committed
system.cpu0.commit.branches                   5542672                       # Number of branches committed
system.cpu0.commit.fp_insts                      4916                       # Number of committed floating point instructions.
system.cpu0.commit.int_insts                 37173454                       # Number of committed integer instructions.
system.cpu0.commit.function_calls              620264                       # Number of function calls committed.
system.cpu0.commit.bw_lim_events              1332812                       # number cycles where commit BW limit reached
system.cpu0.commit.bw_limited                       0                       # number of insts not committed due to BW limits
system.cpu0.rob.rob_reads                   157900366                       # The number of ROB reads
system.cpu0.rob.rob_writes                  106355397                       # The number of ROB writes
system.cpu0.timesIdled                        1453890                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu0.idleCycles                      242723172                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu0.quiesceCycles                  4812468828                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu0.committedInsts                   41801518                       # Number of Instructions Simulated
system.cpu0.committedInsts_total             41801518                       # Number of Instructions Simulated
system.cpu0.cpi                              8.431852                       # CPI: Cycles Per Instruction
system.cpu0.cpi_total                        8.431852                       # CPI: Total CPI of All Threads
system.cpu0.ipc                              0.118598                       # IPC: Instructions Per Cycle
system.cpu0.ipc_total                        0.118598                       # IPC: Total IPC of All Threads
system.cpu0.int_regfile_reads               354175079                       # number of integer regfile reads
system.cpu0.int_regfile_writes               46137251                       # number of integer regfile writes
system.cpu0.fp_regfile_reads                     4205                       # number of floating regfile reads
system.cpu0.fp_regfile_writes                    1348                       # number of floating regfile writes
system.cpu0.misc_regfile_reads               65629786                       # number of misc regfile reads
system.cpu0.misc_regfile_writes                635954                       # number of misc regfile writes
system.cpu0.icache.replacements                539173                       # number of replacements
system.cpu0.icache.tagsinuse               511.623608                       # Cycle average of tags in use
system.cpu0.icache.total_refs                 5839899                       # Total number of references to valid blocks.
system.cpu0.icache.sampled_refs                539685                       # Sample count of references to valid blocks.
system.cpu0.icache.avg_refs                 10.820940                       # Average number of references to valid blocks.
system.cpu0.icache.warmup_cycle           16020223000                       # Cycle when the warmup percentage was hit.
system.cpu0.icache.occ_blocks::0           511.623608                       # Average occupied blocks per context
system.cpu0.icache.occ_percent::0            0.999265                       # Average percentage of cache occupancy
system.cpu0.icache.ReadReq_hits::0            5839899                       # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total        5839899                       # number of ReadReq hits
system.cpu0.icache.demand_hits::0             5839899                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::1                   0                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total         5839899                       # number of demand (read+write) hits
system.cpu0.icache.overall_hits::0            5839899                       # number of overall hits
system.cpu0.icache.overall_hits::1                  0                       # number of overall hits
system.cpu0.icache.overall_hits::total        5839899                       # number of overall hits
system.cpu0.icache.ReadReq_misses::0           584029                       # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total       584029                       # number of ReadReq misses
system.cpu0.icache.demand_misses::0            584029                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::1                 0                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total        584029                       # number of demand (read+write) misses
system.cpu0.icache.overall_misses::0           584029                       # number of overall misses
system.cpu0.icache.overall_misses::1                0                       # number of overall misses
system.cpu0.icache.overall_misses::total       584029                       # number of overall misses
system.cpu0.icache.ReadReq_miss_latency    8742056490                       # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency     8742056490                       # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency    8742056490                       # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::0        6423928                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total      6423928                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::0         6423928                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::1               0                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total      6423928                       # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::0        6423928                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::1              0                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total      6423928                       # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::0      0.090915                       # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::0       0.090915                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::1       no_value                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total     no_value                       # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::0      0.090915                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::1      no_value                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total     no_value                       # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::0 14968.531511                       # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::1          inf                       # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total          inf                       # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::0 14968.531511                       # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::1          inf                       # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total          inf                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::0 14968.531511                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::1          inf                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total          inf                       # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs      1586493                       # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs              210                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_mshrs  7554.728571                       # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
system.cpu0.icache.writebacks                   29902                       # number of writebacks
system.cpu0.icache.ReadReq_mshr_hits            44323                       # number of ReadReq MSHR hits
system.cpu0.icache.demand_mshr_hits             44323                       # number of demand (read+write) MSHR hits
system.cpu0.icache.overall_mshr_hits            44323                       # number of overall MSHR hits
system.cpu0.icache.ReadReq_mshr_misses         539706                       # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses          539706                       # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses         539706                       # number of overall MSHR misses
system.cpu0.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
system.cpu0.icache.ReadReq_mshr_miss_latency   6552393493                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency   6552393493                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency   6552393493                       # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency      6685500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency      6685500                       # number of overall MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::0     0.084015                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::1          inf                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total          inf                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::0     0.084015                       # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::1          inf                       # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total          inf                       # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::0     0.084015                       # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::1          inf                       # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total          inf                       # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency 12140.671945                       # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency 12140.671945                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency 12140.671945                       # average overall mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency          inf                       # average overall mshr uncacheable latency
system.cpu0.icache.mshr_cap_events                  0                       # number of times MSHR cap was activated
system.cpu0.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu0.dcache.replacements                372215                       # number of replacements
system.cpu0.dcache.tagsinuse               487.071305                       # Cycle average of tags in use
system.cpu0.dcache.total_refs                12774859                       # Total number of references to valid blocks.
system.cpu0.dcache.sampled_refs                372727                       # Sample count of references to valid blocks.
system.cpu0.dcache.avg_refs                 34.274037                       # Average number of references to valid blocks.
system.cpu0.dcache.warmup_cycle              49147000                       # Cycle when the warmup percentage was hit.
system.cpu0.dcache.occ_blocks::0           487.071305                       # Average occupied blocks per context
system.cpu0.dcache.occ_percent::0            0.951311                       # Average percentage of cache occupancy
system.cpu0.dcache.ReadReq_hits::0            7959466                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total        7959466                       # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::0           4347928                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total       4347928                       # number of WriteReq hits
system.cpu0.dcache.LoadLockedReq_hits::0       221270                       # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::total       221270                       # number of LoadLockedReq hits
system.cpu0.dcache.StoreCondReq_hits::0        199751                       # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::total       199751                       # number of StoreCondReq hits
system.cpu0.dcache.demand_hits::0            12307394                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::1                   0                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total        12307394                       # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::0           12307394                       # number of overall hits
system.cpu0.dcache.overall_hits::1                  0                       # number of overall hits
system.cpu0.dcache.overall_hits::total       12307394                       # number of overall hits
system.cpu0.dcache.ReadReq_misses::0           462880                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total       462880                       # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::0         1863380                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total      1863380                       # number of WriteReq misses
system.cpu0.dcache.LoadLockedReq_misses::0         9956                       # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::total         9956                       # number of LoadLockedReq misses
system.cpu0.dcache.StoreCondReq_misses::0         7770                       # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::total         7770                       # number of StoreCondReq misses
system.cpu0.dcache.demand_misses::0           2326260                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::1                 0                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total       2326260                       # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::0          2326260                       # number of overall misses
system.cpu0.dcache.overall_misses::1                0                       # number of overall misses
system.cpu0.dcache.overall_misses::total      2326260                       # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency    6451753000                       # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency  70471171342                       # number of WriteReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency    120838000                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency     88450500                       # number of StoreCondReq miss cycles
system.cpu0.dcache.demand_miss_latency    76922924342                       # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency   76922924342                       # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::0        8422346                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total      8422346                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::0       6211308                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total      6211308                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::0       231226                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::total       231226                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::0       207521                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::total       207521                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::0        14633654                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::1               0                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total     14633654                       # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::0       14633654                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::1              0                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total     14633654                       # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::0      0.054959                       # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::0     0.299998                       # miss rate for WriteReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::0     0.043057                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::0     0.037442                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_miss_rate::0       0.158966                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::1       no_value                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total     no_value                       # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::0      0.158966                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::1      no_value                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total     no_value                       # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::0 13938.284221                       # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::1          inf                       # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total          inf                       # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::0 37819.001675                       # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::1          inf                       # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total          inf                       # average WriteReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::0 12137.203696                       # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::1          inf                       # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total          inf                       # average LoadLockedReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::0 11383.590734                       # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::1          inf                       # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total          inf                       # average StoreCondReq miss latency
system.cpu0.dcache.demand_avg_miss_latency::0 33067.208456                       # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::1          inf                       # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total          inf                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::0 33067.208456                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::1          inf                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total          inf                       # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs      6759989                       # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets      1802000                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs              868                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets            123                       # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs  7788.005760                       # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets 14650.406504                       # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu0.dcache.writebacks                  326934                       # number of writebacks
system.cpu0.dcache.ReadReq_mshr_hits           223096                       # number of ReadReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits         1684995                       # number of WriteReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits          326                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.demand_mshr_hits           1908091                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.overall_mshr_hits          1908091                       # number of overall MSHR hits
system.cpu0.dcache.ReadReq_mshr_misses         239784                       # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses        178385                       # number of WriteReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses         9630                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses         7769                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.demand_mshr_misses          418169                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses         418169                       # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
system.cpu0.dcache.ReadReq_mshr_miss_latency   2937322500                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency   6377417488                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency     86877000                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency     65112500                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency   9314739988                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency   9314739988                       # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency 138959379000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency   1038732984                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency 139998111984                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::0     0.028470                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::1          inf                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total          inf                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::0     0.028719                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::1          inf                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total          inf                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::0     0.041648                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::1          inf                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total          inf                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::0     0.037437                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::1          inf                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total          inf                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::0     0.028576                       # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::1          inf                       # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total          inf                       # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::0     0.028576                       # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::1          inf                       # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total          inf                       # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency 12249.868632                       # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency 35750.861833                       # average WriteReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency  9021.495327                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency  8381.065774                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency 22275.061011                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency 22275.061011                       # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency          inf                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency          inf                       # average overall mshr uncacheable latency
system.cpu0.dcache.mshr_cap_events                  0                       # number of times MSHR cap was activated
system.cpu0.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu1.dtb.inst_hits                           0                       # ITB inst hits
system.cpu1.dtb.inst_misses                         0                       # ITB inst misses
system.cpu1.dtb.read_hits                    10573739                       # DTB read hits
system.cpu1.dtb.read_misses                     42015                       # DTB read misses
system.cpu1.dtb.write_hits                    5529871                       # DTB write hits
system.cpu1.dtb.write_misses                    15191                       # DTB write misses
system.cpu1.dtb.flush_tlb                           4                       # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu1.dtb.flush_tlb_mva_asid               1439                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.dtb.flush_tlb_asid                     63                       # Number of times TLB was flushed by ASID
system.cpu1.dtb.flush_entries                    1927                       # Number of entries that have been flushed from TLB
system.cpu1.dtb.align_faults                     3403                       # Number of TLB faults due to alignment restrictions
system.cpu1.dtb.prefetch_faults                   280                       # Number of TLB faults due to prefetch
system.cpu1.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu1.dtb.perms_faults                      684                       # Number of TLB faults due to permissions restrictions
system.cpu1.dtb.read_accesses                10615754                       # DTB read accesses
system.cpu1.dtb.write_accesses                5545062                       # DTB write accesses
system.cpu1.dtb.inst_accesses                       0                       # ITB inst accesses
system.cpu1.dtb.hits                         16103610                       # DTB hits
system.cpu1.dtb.misses                          57206                       # DTB misses
system.cpu1.dtb.accesses                     16160816                       # DTB accesses
system.cpu1.itb.inst_hits                     8206065                       # ITB inst hits
system.cpu1.itb.inst_misses                      3031                       # ITB inst misses
system.cpu1.itb.read_hits                           0                       # DTB read hits
system.cpu1.itb.read_misses                         0                       # DTB read misses
system.cpu1.itb.write_hits                          0                       # DTB write hits
system.cpu1.itb.write_misses                        0                       # DTB write misses
system.cpu1.itb.flush_tlb                           4                       # Number of times complete TLB was flushed
system.cpu1.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu1.itb.flush_tlb_mva_asid               1439                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.itb.flush_tlb_asid                     63                       # Number of times TLB was flushed by ASID
system.cpu1.itb.flush_entries                    1367                       # Number of entries that have been flushed from TLB
system.cpu1.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu1.itb.perms_faults                     2156                       # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses                       0                       # DTB read accesses
system.cpu1.itb.write_accesses                      0                       # DTB write accesses
system.cpu1.itb.inst_accesses                 8209096                       # ITB inst accesses
system.cpu1.itb.hits                          8206065                       # DTB hits
system.cpu1.itb.misses                           3031                       # DTB misses
system.cpu1.itb.accesses                      8209096                       # DTB accesses
system.cpu1.numCycles                        69056369                       # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu1.BPredUnit.lookups                 8325282                       # Number of BP lookups
system.cpu1.BPredUnit.condPredicted           6737041                       # Number of conditional branches predicted
system.cpu1.BPredUnit.condIncorrect            502555                       # Number of conditional branches incorrect
system.cpu1.BPredUnit.BTBLookups              7261407                       # Number of BTB lookups
system.cpu1.BPredUnit.BTBHits                 5699060                       # Number of BTB hits
system.cpu1.BPredUnit.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu1.BPredUnit.usedRAS                  682916                       # Number of times the RAS was used to get a target.
system.cpu1.BPredUnit.RASInCorrect             107380                       # Number of incorrect RAS predictions.
system.cpu1.fetch.icacheStallCycles          17608500                       # Number of cycles fetch is stalled on an Icache miss
system.cpu1.fetch.Insts                      62544782                       # Number of instructions fetch has processed
system.cpu1.fetch.Branches                    8325282                       # Number of branches that fetch encountered
system.cpu1.fetch.predictedBranches           6381976                       # Number of branches that fetch has predicted taken
system.cpu1.fetch.Cycles                     13909998                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu1.fetch.SquashCycles                4633998                       # Number of cycles fetch has spent squashing
system.cpu1.fetch.TlbCycles                     45331                       # Number of cycles fetch has spent waiting for tlb
system.cpu1.fetch.BlockedCycles              15806576                       # Number of cycles fetch has spent blocked
system.cpu1.fetch.MiscStallCycles                3075                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu1.fetch.PendingTrapStallCycles        32937                       # Number of stall cycles due to pending traps
system.cpu1.fetch.PendingQuiesceStallCycles       125179                       # Number of stall cycles due to pending quiesce instructions
system.cpu1.fetch.IcacheWaitRetryStallCycles          192                       # Number of stall cycles due to full MSHR
system.cpu1.fetch.CacheLines                  8203545                       # Number of cache lines fetched
system.cpu1.fetch.IcacheSquashes               759342                       # Number of outstanding Icache misses that were squashed
system.cpu1.fetch.ItlbSquashes                   1683                       # Number of outstanding ITLB misses that were squashed
system.cpu1.fetch.rateDist::samples          50660963                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::mean             1.494360                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::stdev            2.745003                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::0                36758800     72.56%     72.56% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::1                  702781      1.39%     73.95% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::2                 1220162      2.41%     76.35% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::3                 2515175      4.96%     81.32% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::4                 1141377      2.25%     83.57% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::5                  650709      1.28%     84.86% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::6                 1886656      3.72%     88.58% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::7                  404310      0.80%     89.38% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::8                 5380993     10.62%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::total            50660963                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.branchRate                 0.120558                       # Number of branch fetches per cycle
system.cpu1.fetch.rate                       0.905706                       # Number of inst fetches per cycle
system.cpu1.decode.IdleCycles                18651451                       # Number of cycles decode is idle
system.cpu1.decode.BlockedCycles             16071797                       # Number of cycles decode is blocked
system.cpu1.decode.RunCycles                 12503703                       # Number of cycles decode is running
system.cpu1.decode.UnblockCycles               383683                       # Number of cycles decode is unblocking
system.cpu1.decode.SquashCycles               3050329                       # Number of cycles decode is squashing
system.cpu1.decode.BranchResolved             1080503                       # Number of times decode resolved a branch
system.cpu1.decode.BranchMispred                80301                       # Number of times decode detected a branch misprediction
system.cpu1.decode.DecodedInsts              69737045                       # Number of instructions handled by decode
system.cpu1.decode.SquashedInsts               259727                       # Number of squashed instructions handled by decode
system.cpu1.rename.SquashCycles               3050329                       # Number of cycles rename is squashing
system.cpu1.rename.IdleCycles                19796555                       # Number of cycles rename is idle
system.cpu1.rename.BlockCycles                3624603                       # Number of cycles rename is blocking
system.cpu1.rename.serializeStallCycles      10867059                       # count of cycles rename stalled for serializing inst
system.cpu1.rename.RunCycles                 11733074                       # Number of cycles rename is running
system.cpu1.rename.UnblockCycles              1589343                       # Number of cycles rename is unblocking
system.cpu1.rename.RenamedInsts              63809564                       # Number of instructions processed by rename
system.cpu1.rename.ROBFullEvents                 2981                       # Number of times rename has blocked due to ROB full
system.cpu1.rename.IQFullEvents                320281                       # Number of times rename has blocked due to IQ full
system.cpu1.rename.LSQFullEvents               864112                       # Number of times rename has blocked due to LSQ full
system.cpu1.rename.FullRegisterEvents           38202                       # Number of times there has been no free registers
system.cpu1.rename.RenamedOperands           68239803                       # Number of destination operands rename has renamed
system.cpu1.rename.RenameLookups            296124940                       # Number of register rename lookups that rename has made
system.cpu1.rename.int_rename_lookups       296072200                       # Number of integer rename lookups
system.cpu1.rename.fp_rename_lookups            52740                       # Number of floating rename lookups
system.cpu1.rename.CommittedMaps             39106608                       # Number of HB maps that are committed
system.cpu1.rename.UndoneMaps                29133195                       # Number of HB maps that are undone due to squashing
system.cpu1.rename.serializingInsts            434621                       # count of serializing insts renamed
system.cpu1.rename.tempSerializingInsts        382462                       # count of temporary serializing insts renamed
system.cpu1.rename.skidInsts                  4203927                       # count of insts added to the skid buffer
system.cpu1.memDep0.insertedLoads            11080202                       # Number of loads inserted to the mem dependence unit.
system.cpu1.memDep0.insertedStores            7013216                       # Number of stores inserted to the mem dependence unit.
system.cpu1.memDep0.conflictingLoads           634211                       # Number of conflicting loads.
system.cpu1.memDep0.conflictingStores          885799                       # Number of conflicting stores.
system.cpu1.iq.iqInstsAdded                  56015216                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu1.iq.iqNonSpecInstsAdded             652114                       # Number of non-speculative instructions added to the IQ
system.cpu1.iq.iqInstsIssued                 50333331                       # Number of instructions issued
system.cpu1.iq.iqSquashedInstsIssued           120412                       # Number of squashed instructions issued
system.cpu1.iq.iqSquashedInstsExamined       18201885                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu1.iq.iqSquashedOperandsExamined     52559759                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu1.iq.iqSquashedNonSpecRemoved        132486                       # Number of squashed non-spec instructions that were removed
system.cpu1.iq.issued_per_cycle::samples     50660963                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::mean        0.993533                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::stdev       1.617126                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::0           32144545     63.45%     63.45% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::1            5530112     10.92%     74.37% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::2            3775848      7.45%     81.82% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::3            3605586      7.12%     88.94% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::4            2986827      5.90%     94.83% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::5            1557942      3.08%     97.91% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::6             784538      1.55%     99.46% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::7             214001      0.42%     99.88% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::8              61564      0.12%    100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::total       50660963                       # Number of insts issued each cycle
system.cpu1.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntAlu                  15475      1.52%      1.52% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntMult                  1190      0.12%      1.63% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntDiv                      0      0.00%      1.63% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatAdd                    0      0.00%      1.63% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatCmp                    0      0.00%      1.63% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatCvt                    0      0.00%      1.63% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatMult                   0      0.00%      1.63% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatDiv                    0      0.00%      1.63% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatSqrt                   0      0.00%      1.63% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAdd                     0      0.00%      1.63% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAddAcc                  0      0.00%      1.63% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAlu                     0      0.00%      1.63% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdCmp                     0      0.00%      1.63% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdCvt                     0      0.00%      1.63% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMisc                    0      0.00%      1.63% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMult                    0      0.00%      1.63% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMultAcc                 0      0.00%      1.63% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdShift                   0      0.00%      1.63% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdShiftAcc                0      0.00%      1.63% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdSqrt                    0      0.00%      1.63% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatAdd                0      0.00%      1.63% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatAlu                0      0.00%      1.63% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatCmp                0      0.00%      1.63% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatCvt                0      0.00%      1.63% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatDiv                0      0.00%      1.63% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMisc               0      0.00%      1.63% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMult               0      0.00%      1.63% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMultAcc            0      0.00%      1.63% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatSqrt               0      0.00%      1.63% # attempts to use FU when none available
system.cpu1.iq.fu_full::MemRead                748820     73.38%     75.02% # attempts to use FU when none available
system.cpu1.iq.fu_full::MemWrite               254917     24.98%    100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
system.cpu1.iq.FU_type_0::No_OpClass            18622      0.04%      0.04% # Type of FU issued
system.cpu1.iq.FU_type_0::IntAlu             32741822     65.05%     65.09% # Type of FU issued
system.cpu1.iq.FU_type_0::IntMult               50334      0.10%     65.19% # Type of FU issued
system.cpu1.iq.FU_type_0::IntDiv                    0      0.00%     65.19% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatAdd                  0      0.00%     65.19% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatCmp                  0      0.00%     65.19% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatCvt                  0      0.00%     65.19% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatMult                 0      0.00%     65.19% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatDiv                  0      0.00%     65.19% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatSqrt                 0      0.00%     65.19% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAdd                   0      0.00%     65.19% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAddAcc                0      0.00%     65.19% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAlu                   0      0.00%     65.19% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdCmp                   0      0.00%     65.19% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdCvt                   0      0.00%     65.19% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMisc                  2      0.00%     65.19% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMult                  0      0.00%     65.19% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMultAcc               0      0.00%     65.19% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdShift                 1      0.00%     65.19% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdShiftAcc              2      0.00%     65.19% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdSqrt                  0      0.00%     65.19% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatAdd              0      0.00%     65.19% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatAlu              0      0.00%     65.19% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatCmp              0      0.00%     65.19% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatCvt              0      0.00%     65.19% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatDiv              0      0.00%     65.19% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMisc           764      0.00%     65.19% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMult             0      0.00%     65.19% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMultAcc            2      0.00%     65.19% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatSqrt             0      0.00%     65.19% # Type of FU issued
system.cpu1.iq.FU_type_0::MemRead            11609954     23.07%     88.25% # Type of FU issued
system.cpu1.iq.FU_type_0::MemWrite            5911828     11.75%    100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::total              50333331                       # Type of FU issued
system.cpu1.iq.rate                          0.728873                       # Inst issue rate
system.cpu1.iq.fu_busy_cnt                    1020402                       # FU busy when requested
system.cpu1.iq.fu_busy_rate                  0.020273                       # FU busy rate (busy events/executed inst)
system.cpu1.iq.int_inst_queue_reads         152512648                       # Number of integer instruction queue reads
system.cpu1.iq.int_inst_queue_writes         74873900                       # Number of integer instruction queue writes
system.cpu1.iq.int_inst_queue_wakeup_accesses     44249478                       # Number of integer instruction queue wakeup accesses
system.cpu1.iq.fp_inst_queue_reads              12744                       # Number of floating instruction queue reads
system.cpu1.iq.fp_inst_queue_writes              7082                       # Number of floating instruction queue writes
system.cpu1.iq.fp_inst_queue_wakeup_accesses         5800                       # Number of floating instruction queue wakeup accesses
system.cpu1.iq.int_alu_accesses              51328452                       # Number of integer alu accesses
system.cpu1.iq.fp_alu_accesses                   6659                       # Number of floating point alu accesses
system.cpu1.iew.lsq.thread0.forwLoads          264599                       # Number of loads that had data forwarded from stores
system.cpu1.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
system.cpu1.iew.lsq.thread0.squashedLoads      3968304                       # Number of loads squashed
system.cpu1.iew.lsq.thread0.ignoredResponses         7379                       # Number of memory responses ignored because the instruction is squashed
system.cpu1.iew.lsq.thread0.memOrderViolation        12210                       # Number of memory ordering violations
system.cpu1.iew.lsq.thread0.squashedStores      1474293                       # Number of stores squashed
system.cpu1.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
system.cpu1.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
system.cpu1.iew.lsq.thread0.rescheduledLoads      1850149                       # Number of loads that were rescheduled
system.cpu1.iew.lsq.thread0.cacheBlocked      1139663                       # Number of times an access to memory failed due to the cache being blocked
system.cpu1.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
system.cpu1.iew.iewSquashCycles               3050329                       # Number of cycles IEW is squashing
system.cpu1.iew.iewBlockCycles                2505738                       # Number of cycles IEW is blocking
system.cpu1.iew.iewUnblockCycles                70750                       # Number of cycles IEW is unblocking
system.cpu1.iew.iewDispatchedInsts           56718238                       # Number of instructions dispatched to IQ
system.cpu1.iew.iewDispSquashedInsts           255272                       # Number of squashed instructions skipped by dispatch
system.cpu1.iew.iewDispLoadInsts             11080202                       # Number of dispatched load instructions
system.cpu1.iew.iewDispStoreInsts             7013216                       # Number of dispatched store instructions
system.cpu1.iew.iewDispNonSpecInsts            408861                       # Number of dispatched non-speculative instructions
system.cpu1.iew.iewIQFullEvents                 28043                       # Number of times the IQ has become full, causing a stall
system.cpu1.iew.iewLSQFullEvents                 3317                       # Number of times the LSQ has become full, causing a stall
system.cpu1.iew.memOrderViolationEvents         12210                       # Number of memory order violations
system.cpu1.iew.predictedTakenIncorrect        383709                       # Number of branches that were predicted taken incorrectly
system.cpu1.iew.predictedNotTakenIncorrect       125709                       # Number of branches that were predicted not taken incorrectly
system.cpu1.iew.branchMispredicts              509418                       # Number of branch mispredicts detected at execute
system.cpu1.iew.iewExecutedInsts             47546383                       # Number of executed instructions
system.cpu1.iew.iewExecLoadInsts             10844490                       # Number of load instructions executed
system.cpu1.iew.iewExecSquashedInsts          2786948                       # Number of squashed instructions skipped in execute
system.cpu1.iew.exec_swp                            0                       # number of swp insts executed
system.cpu1.iew.exec_nop                        50908                       # number of nop insts executed
system.cpu1.iew.exec_refs                    16665607                       # number of memory reference insts executed
system.cpu1.iew.exec_branches                 5805305                       # Number of branches executed
system.cpu1.iew.exec_stores                   5821117                       # Number of stores executed
system.cpu1.iew.exec_rate                    0.688516                       # Inst execution rate
system.cpu1.iew.wb_sent                      46287732                       # cumulative count of insts sent to commit
system.cpu1.iew.wb_count                     44255278                       # cumulative count of insts written-back
system.cpu1.iew.wb_producers                 24264943                       # num instructions producing a value
system.cpu1.iew.wb_consumers                 44435618                       # num instructions consuming a value
system.cpu1.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
system.cpu1.iew.wb_rate                      0.640857                       # insts written-back per cycle
system.cpu1.iew.wb_fanout                    0.546070                       # average fanout of values written-back
system.cpu1.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu1.commit.commitCommittedInsts      38085105                       # The number of committed instructions
system.cpu1.commit.commitSquashedInsts       18540440                       # The number of squashed insts skipped by commit
system.cpu1.commit.commitNonSpecStalls         519628                       # The number of times commit has been forced to stall to communicate backwards
system.cpu1.commit.branchMispredicts           449695                       # The number of times a branch was mispredicted
system.cpu1.commit.committed_per_cycle::samples     47651856                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::mean     0.799237                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::stdev     1.835547                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::0     34686600     72.79%     72.79% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::1      6094128     12.79%     85.58% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::2      1835097      3.85%     89.43% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::3       960943      2.02%     91.45% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::4       825753      1.73%     93.18% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::5       740854      1.55%     94.74% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::6       593786      1.25%     95.98% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::7       449604      0.94%     96.93% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::8      1465091      3.07%    100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::total     47651856                       # Number of insts commited each cycle
system.cpu1.commit.count                     38085105                       # Number of instructions committed
system.cpu1.commit.swp_count                        0                       # Number of s/w prefetches committed
system.cpu1.commit.refs                      12650821                       # Number of memory references committed
system.cpu1.commit.loads                      7111898                       # Number of loads committed
system.cpu1.commit.membars                     148710                       # Number of memory barriers committed
system.cpu1.commit.branches                   4804442                       # Number of branches committed
system.cpu1.commit.fp_insts                      5744                       # Number of committed floating point instructions.
system.cpu1.commit.int_insts                 34027730                       # Number of committed integer instructions.
system.cpu1.commit.function_calls              433273                       # Number of function calls committed.
system.cpu1.commit.bw_lim_events              1465091                       # number cycles where commit BW limit reached
system.cpu1.commit.bw_limited                       0                       # number of insts not committed due to BW limits
system.cpu1.rob.rob_reads                   102053926                       # The number of ROB reads
system.cpu1.rob.rob_writes                  116420763                       # The number of ROB writes
system.cpu1.timesIdled                         449905                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu1.idleCycles                       18395406                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu1.quiesceCycles                  5095165422                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu1.committedInsts                   38060551                       # Number of Instructions Simulated
system.cpu1.committedInsts_total             38060551                       # Number of Instructions Simulated
system.cpu1.cpi                              1.814382                       # CPI: Cycles Per Instruction
system.cpu1.cpi_total                        1.814382                       # CPI: Total CPI of All Threads
system.cpu1.ipc                              0.551152                       # IPC: Instructions Per Cycle
system.cpu1.ipc_total                        0.551152                       # IPC: Total IPC of All Threads
system.cpu1.int_regfile_reads               222777169                       # number of integer regfile reads
system.cpu1.int_regfile_writes               47147395                       # number of integer regfile writes
system.cpu1.fp_regfile_reads                     4225                       # number of floating regfile reads
system.cpu1.fp_regfile_writes                    1812                       # number of floating regfile writes
system.cpu1.misc_regfile_reads               77230796                       # number of misc regfile reads
system.cpu1.misc_regfile_writes                323252                       # number of misc regfile writes
system.cpu1.icache.replacements                485904                       # number of replacements
system.cpu1.icache.tagsinuse               498.788757                       # Cycle average of tags in use
system.cpu1.icache.total_refs                 7675789                       # Total number of references to valid blocks.
system.cpu1.icache.sampled_refs                486416                       # Sample count of references to valid blocks.
system.cpu1.icache.avg_refs                 15.780297                       # Average number of references to valid blocks.
system.cpu1.icache.warmup_cycle           74237229000                       # Cycle when the warmup percentage was hit.
system.cpu1.icache.occ_blocks::0           498.788757                       # Average occupied blocks per context
system.cpu1.icache.occ_percent::0            0.974197                       # Average percentage of cache occupancy
system.cpu1.icache.ReadReq_hits::0            7675789                       # number of ReadReq hits
system.cpu1.icache.ReadReq_hits::total        7675789                       # number of ReadReq hits
system.cpu1.icache.demand_hits::0             7675789                       # number of demand (read+write) hits
system.cpu1.icache.demand_hits::1                   0                       # number of demand (read+write) hits
system.cpu1.icache.demand_hits::total         7675789                       # number of demand (read+write) hits
system.cpu1.icache.overall_hits::0            7675789                       # number of overall hits
system.cpu1.icache.overall_hits::1                  0                       # number of overall hits
system.cpu1.icache.overall_hits::total        7675789                       # number of overall hits
system.cpu1.icache.ReadReq_misses::0           527703                       # number of ReadReq misses
system.cpu1.icache.ReadReq_misses::total       527703                       # number of ReadReq misses
system.cpu1.icache.demand_misses::0            527703                       # number of demand (read+write) misses
system.cpu1.icache.demand_misses::1                 0                       # number of demand (read+write) misses
system.cpu1.icache.demand_misses::total        527703                       # number of demand (read+write) misses
system.cpu1.icache.overall_misses::0           527703                       # number of overall misses
system.cpu1.icache.overall_misses::1                0                       # number of overall misses
system.cpu1.icache.overall_misses::total       527703                       # number of overall misses
system.cpu1.icache.ReadReq_miss_latency    7760328997                       # number of ReadReq miss cycles
system.cpu1.icache.demand_miss_latency     7760328997                       # number of demand (read+write) miss cycles
system.cpu1.icache.overall_miss_latency    7760328997                       # number of overall miss cycles
system.cpu1.icache.ReadReq_accesses::0        8203492                       # number of ReadReq accesses(hits+misses)
system.cpu1.icache.ReadReq_accesses::total      8203492                       # number of ReadReq accesses(hits+misses)
system.cpu1.icache.demand_accesses::0         8203492                       # number of demand (read+write) accesses
system.cpu1.icache.demand_accesses::1               0                       # number of demand (read+write) accesses
system.cpu1.icache.demand_accesses::total      8203492                       # number of demand (read+write) accesses
system.cpu1.icache.overall_accesses::0        8203492                       # number of overall (read+write) accesses
system.cpu1.icache.overall_accesses::1              0                       # number of overall (read+write) accesses
system.cpu1.icache.overall_accesses::total      8203492                       # number of overall (read+write) accesses
system.cpu1.icache.ReadReq_miss_rate::0      0.064327                       # miss rate for ReadReq accesses
system.cpu1.icache.demand_miss_rate::0       0.064327                       # miss rate for demand accesses
system.cpu1.icache.demand_miss_rate::1       no_value                       # miss rate for demand accesses
system.cpu1.icache.demand_miss_rate::total     no_value                       # miss rate for demand accesses
system.cpu1.icache.overall_miss_rate::0      0.064327                       # miss rate for overall accesses
system.cpu1.icache.overall_miss_rate::1      no_value                       # miss rate for overall accesses
system.cpu1.icache.overall_miss_rate::total     no_value                       # miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_miss_latency::0 14705.864846                       # average ReadReq miss latency
system.cpu1.icache.ReadReq_avg_miss_latency::1          inf                       # average ReadReq miss latency
system.cpu1.icache.ReadReq_avg_miss_latency::total          inf                       # average ReadReq miss latency
system.cpu1.icache.demand_avg_miss_latency::0 14705.864846                       # average overall miss latency
system.cpu1.icache.demand_avg_miss_latency::1          inf                       # average overall miss latency
system.cpu1.icache.demand_avg_miss_latency::total          inf                       # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::0 14705.864846                       # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::1          inf                       # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::total          inf                       # average overall miss latency
system.cpu1.icache.blocked_cycles::no_mshrs      1243497                       # number of cycles access was blocked
system.cpu1.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.icache.blocked::no_mshrs              167                       # number of cycles access was blocked
system.cpu1.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu1.icache.avg_blocked_cycles::no_mshrs  7446.089820                       # average number of cycles each access was blocked
system.cpu1.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
system.cpu1.icache.fast_writes                      0                       # number of fast writes performed
system.cpu1.icache.cache_copies                     0                       # number of cache copies performed
system.cpu1.icache.writebacks                   18536                       # number of writebacks
system.cpu1.icache.ReadReq_mshr_hits            41257                       # number of ReadReq MSHR hits
system.cpu1.icache.demand_mshr_hits             41257                       # number of demand (read+write) MSHR hits
system.cpu1.icache.overall_mshr_hits            41257                       # number of overall MSHR hits
system.cpu1.icache.ReadReq_mshr_misses         486446                       # number of ReadReq MSHR misses
system.cpu1.icache.demand_mshr_misses          486446                       # number of demand (read+write) MSHR misses
system.cpu1.icache.overall_mshr_misses         486446                       # number of overall MSHR misses
system.cpu1.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
system.cpu1.icache.ReadReq_mshr_miss_latency   5802515997                       # number of ReadReq MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency   5802515997                       # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency   5802515997                       # number of overall MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_uncacheable_latency      2517500                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.icache.overall_mshr_uncacheable_latency      2517500                       # number of overall MSHR uncacheable cycles
system.cpu1.icache.ReadReq_mshr_miss_rate::0     0.059297                       # mshr miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_mshr_miss_rate::1          inf                       # mshr miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_mshr_miss_rate::total          inf                       # mshr miss rate for ReadReq accesses
system.cpu1.icache.demand_mshr_miss_rate::0     0.059297                       # mshr miss rate for demand accesses
system.cpu1.icache.demand_mshr_miss_rate::1          inf                       # mshr miss rate for demand accesses
system.cpu1.icache.demand_mshr_miss_rate::total          inf                       # mshr miss rate for demand accesses
system.cpu1.icache.overall_mshr_miss_rate::0     0.059297                       # mshr miss rate for overall accesses
system.cpu1.icache.overall_mshr_miss_rate::1          inf                       # mshr miss rate for overall accesses
system.cpu1.icache.overall_mshr_miss_rate::total          inf                       # mshr miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_mshr_miss_latency 11928.386701                       # average ReadReq mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency 11928.386701                       # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency 11928.386701                       # average overall mshr miss latency
system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency          inf                       # average ReadReq mshr uncacheable latency
system.cpu1.icache.overall_avg_mshr_uncacheable_latency          inf                       # average overall mshr uncacheable latency
system.cpu1.icache.mshr_cap_events                  0                       # number of times MSHR cap was activated
system.cpu1.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
system.cpu1.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu1.dcache.replacements                272184                       # number of replacements
system.cpu1.dcache.tagsinuse               444.922817                       # Cycle average of tags in use
system.cpu1.dcache.total_refs                10410516                       # Total number of references to valid blocks.
system.cpu1.dcache.sampled_refs                272526                       # Sample count of references to valid blocks.
system.cpu1.dcache.avg_refs                 38.200084                       # Average number of references to valid blocks.
system.cpu1.dcache.warmup_cycle           66749899000                       # Cycle when the warmup percentage was hit.
system.cpu1.dcache.occ_blocks::0           444.922817                       # Average occupied blocks per context
system.cpu1.dcache.occ_percent::0            0.868990                       # Average percentage of cache occupancy
system.cpu1.dcache.ReadReq_hits::0            7080702                       # number of ReadReq hits
system.cpu1.dcache.ReadReq_hits::total        7080702                       # number of ReadReq hits
system.cpu1.dcache.WriteReq_hits::0           3139041                       # number of WriteReq hits
system.cpu1.dcache.WriteReq_hits::total       3139041                       # number of WriteReq hits
system.cpu1.dcache.LoadLockedReq_hits::0        75297                       # number of LoadLockedReq hits
system.cpu1.dcache.LoadLockedReq_hits::total        75297                       # number of LoadLockedReq hits
system.cpu1.dcache.StoreCondReq_hits::0         72589                       # number of StoreCondReq hits
system.cpu1.dcache.StoreCondReq_hits::total        72589                       # number of StoreCondReq hits
system.cpu1.dcache.demand_hits::0            10219743                       # number of demand (read+write) hits
system.cpu1.dcache.demand_hits::1                   0                       # number of demand (read+write) hits
system.cpu1.dcache.demand_hits::total        10219743                       # number of demand (read+write) hits
system.cpu1.dcache.overall_hits::0           10219743                       # number of overall hits
system.cpu1.dcache.overall_hits::1                  0                       # number of overall hits
system.cpu1.dcache.overall_hits::total       10219743                       # number of overall hits
system.cpu1.dcache.ReadReq_misses::0           323641                       # number of ReadReq misses
system.cpu1.dcache.ReadReq_misses::total       323641                       # number of ReadReq misses
system.cpu1.dcache.WriteReq_misses::0         1274421                       # number of WriteReq misses
system.cpu1.dcache.WriteReq_misses::total      1274421                       # number of WriteReq misses
system.cpu1.dcache.LoadLockedReq_misses::0        12692                       # number of LoadLockedReq misses
system.cpu1.dcache.LoadLockedReq_misses::total        12692                       # number of LoadLockedReq misses
system.cpu1.dcache.StoreCondReq_misses::0        11088                       # number of StoreCondReq misses
system.cpu1.dcache.StoreCondReq_misses::total        11088                       # number of StoreCondReq misses
system.cpu1.dcache.demand_misses::0           1598062                       # number of demand (read+write) misses
system.cpu1.dcache.demand_misses::1                 0                       # number of demand (read+write) misses
system.cpu1.dcache.demand_misses::total       1598062                       # number of demand (read+write) misses
system.cpu1.dcache.overall_misses::0          1598062                       # number of overall misses
system.cpu1.dcache.overall_misses::1                0                       # number of overall misses
system.cpu1.dcache.overall_misses::total      1598062                       # number of overall misses
system.cpu1.dcache.ReadReq_miss_latency    5056918000                       # number of ReadReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency  46262292366                       # number of WriteReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency    147873000                       # number of LoadLockedReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency     87994000                       # number of StoreCondReq miss cycles
system.cpu1.dcache.demand_miss_latency    51319210366                       # number of demand (read+write) miss cycles
system.cpu1.dcache.overall_miss_latency   51319210366                       # number of overall miss cycles
system.cpu1.dcache.ReadReq_accesses::0        7404343                       # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.ReadReq_accesses::total      7404343                       # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::0       4413462                       # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::total      4413462                       # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::0        87989                       # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::total        87989                       # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::0        83677                       # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::total        83677                       # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.demand_accesses::0        11817805                       # number of demand (read+write) accesses
system.cpu1.dcache.demand_accesses::1               0                       # number of demand (read+write) accesses
system.cpu1.dcache.demand_accesses::total     11817805                       # number of demand (read+write) accesses
system.cpu1.dcache.overall_accesses::0       11817805                       # number of overall (read+write) accesses
system.cpu1.dcache.overall_accesses::1              0                       # number of overall (read+write) accesses
system.cpu1.dcache.overall_accesses::total     11817805                       # number of overall (read+write) accesses
system.cpu1.dcache.ReadReq_miss_rate::0      0.043710                       # miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_miss_rate::0     0.288758                       # miss rate for WriteReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::0     0.144245                       # miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::0     0.132510                       # miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_miss_rate::0       0.135225                       # miss rate for demand accesses
system.cpu1.dcache.demand_miss_rate::1       no_value                       # miss rate for demand accesses
system.cpu1.dcache.demand_miss_rate::total     no_value                       # miss rate for demand accesses
system.cpu1.dcache.overall_miss_rate::0      0.135225                       # miss rate for overall accesses
system.cpu1.dcache.overall_miss_rate::1      no_value                       # miss rate for overall accesses
system.cpu1.dcache.overall_miss_rate::total     no_value                       # miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_miss_latency::0 15625.084584                       # average ReadReq miss latency
system.cpu1.dcache.ReadReq_avg_miss_latency::1          inf                       # average ReadReq miss latency
system.cpu1.dcache.ReadReq_avg_miss_latency::total          inf                       # average ReadReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::0 36300.635635                       # average WriteReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::1          inf                       # average WriteReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::total          inf                       # average WriteReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::0 11650.882446                       # average LoadLockedReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::1          inf                       # average LoadLockedReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total          inf                       # average LoadLockedReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::0  7935.966811                       # average StoreCondReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::1          inf                       # average StoreCondReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::total          inf                       # average StoreCondReq miss latency
system.cpu1.dcache.demand_avg_miss_latency::0 32113.403839                       # average overall miss latency
system.cpu1.dcache.demand_avg_miss_latency::1          inf                       # average overall miss latency
system.cpu1.dcache.demand_avg_miss_latency::total          inf                       # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::0 32113.403839                       # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::1          inf                       # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::total          inf                       # average overall miss latency
system.cpu1.dcache.blocked_cycles::no_mshrs     13353050                       # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets      5461500                       # number of cycles access was blocked
system.cpu1.dcache.blocked::no_mshrs             3087                       # number of cycles access was blocked
system.cpu1.dcache.blocked::no_targets            160                       # number of cycles access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_mshrs  4325.574992                       # average number of cycles each access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_targets 34134.375000                       # average number of cycles each access was blocked
system.cpu1.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu1.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu1.dcache.writebacks                  223414                       # number of writebacks
system.cpu1.dcache.ReadReq_mshr_hits           134188                       # number of ReadReq MSHR hits
system.cpu1.dcache.WriteReq_mshr_hits         1158095                       # number of WriteReq MSHR hits
system.cpu1.dcache.LoadLockedReq_mshr_hits          989                       # number of LoadLockedReq MSHR hits
system.cpu1.dcache.demand_mshr_hits           1292283                       # number of demand (read+write) MSHR hits
system.cpu1.dcache.overall_mshr_hits          1292283                       # number of overall MSHR hits
system.cpu1.dcache.ReadReq_mshr_misses         189453                       # number of ReadReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses        116326                       # number of WriteReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses        11703                       # number of LoadLockedReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses        11087                       # number of StoreCondReq MSHR misses
system.cpu1.dcache.demand_mshr_misses          305779                       # number of demand (read+write) MSHR misses
system.cpu1.dcache.overall_mshr_misses         305779                       # number of overall MSHR misses
system.cpu1.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
system.cpu1.dcache.ReadReq_mshr_miss_latency   2493574500                       # number of ReadReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency   3446976050                       # number of WriteReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency     98971000                       # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency     54655500                       # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency   5940550550                       # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency   5940550550                       # number of overall MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency   8455171000                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency  41503599517                       # number of WriteReq MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency  49958770517                       # number of overall MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_miss_rate::0     0.025587                       # mshr miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_mshr_miss_rate::1          inf                       # mshr miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_mshr_miss_rate::total          inf                       # mshr miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::0     0.026357                       # mshr miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::1          inf                       # mshr miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::total          inf                       # mshr miss rate for WriteReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::0     0.133005                       # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::1          inf                       # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total          inf                       # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::0     0.132498                       # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::1          inf                       # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total          inf                       # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_mshr_miss_rate::0     0.025874                       # mshr miss rate for demand accesses
system.cpu1.dcache.demand_mshr_miss_rate::1          inf                       # mshr miss rate for demand accesses
system.cpu1.dcache.demand_mshr_miss_rate::total          inf                       # mshr miss rate for demand accesses
system.cpu1.dcache.overall_mshr_miss_rate::0     0.025874                       # mshr miss rate for overall accesses
system.cpu1.dcache.overall_mshr_miss_rate::1          inf                       # mshr miss rate for overall accesses
system.cpu1.dcache.overall_mshr_miss_rate::total          inf                       # mshr miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency 13161.968932                       # average ReadReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency 29632.034541                       # average WriteReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency  8456.891395                       # average LoadLockedReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency  4929.692433                       # average StoreCondReq mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency 19427.594930                       # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency 19427.594930                       # average overall mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency          inf                       # average ReadReq mshr uncacheable latency
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency          inf                       # average WriteReq mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency          inf                       # average overall mshr uncacheable latency
system.cpu1.dcache.mshr_cap_events                  0                       # number of times MSHR cap was activated
system.cpu1.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
system.cpu1.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.iocache.replacements                         0                       # number of replacements
system.iocache.tagsinuse                            0                       # Cycle average of tags in use
system.iocache.total_refs                           0                       # Total number of references to valid blocks.
system.iocache.sampled_refs                         0                       # Sample count of references to valid blocks.
system.iocache.avg_refs                      no_value                       # Average number of references to valid blocks.
system.iocache.warmup_cycle                         0                       # Cycle when the warmup percentage was hit.
system.iocache.demand_hits::0                       0                       # number of demand (read+write) hits
system.iocache.demand_hits::1                       0                       # number of demand (read+write) hits
system.iocache.demand_hits::total                   0                       # number of demand (read+write) hits
system.iocache.overall_hits::0                      0                       # number of overall hits
system.iocache.overall_hits::1                      0                       # number of overall hits
system.iocache.overall_hits::total                  0                       # number of overall hits
system.iocache.demand_misses::0                     0                       # number of demand (read+write) misses
system.iocache.demand_misses::1                     0                       # number of demand (read+write) misses
system.iocache.demand_misses::total                 0                       # number of demand (read+write) misses
system.iocache.overall_misses::0                    0                       # number of overall misses
system.iocache.overall_misses::1                    0                       # number of overall misses
system.iocache.overall_misses::total                0                       # number of overall misses
system.iocache.demand_miss_latency                  0                       # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency                 0                       # number of overall miss cycles
system.iocache.demand_accesses::0                   0                       # number of demand (read+write) accesses
system.iocache.demand_accesses::1                   0                       # number of demand (read+write) accesses
system.iocache.demand_accesses::total               0                       # number of demand (read+write) accesses
system.iocache.overall_accesses::0                  0                       # number of overall (read+write) accesses
system.iocache.overall_accesses::1                  0                       # number of overall (read+write) accesses
system.iocache.overall_accesses::total              0                       # number of overall (read+write) accesses
system.iocache.demand_miss_rate::0           no_value                       # miss rate for demand accesses
system.iocache.demand_miss_rate::1           no_value                       # miss rate for demand accesses
system.iocache.demand_miss_rate::total       no_value                       # miss rate for demand accesses
system.iocache.overall_miss_rate::0          no_value                       # miss rate for overall accesses
system.iocache.overall_miss_rate::1          no_value                       # miss rate for overall accesses
system.iocache.overall_miss_rate::total      no_value                       # miss rate for overall accesses
system.iocache.demand_avg_miss_latency::0     no_value                       # average overall miss latency
system.iocache.demand_avg_miss_latency::1     no_value                       # average overall miss latency
system.iocache.demand_avg_miss_latency::total     no_value                       # average overall miss latency
system.iocache.overall_avg_miss_latency::0     no_value                       # average overall miss latency
system.iocache.overall_avg_miss_latency::1     no_value                       # average overall miss latency
system.iocache.overall_avg_miss_latency::total     no_value                       # average overall miss latency
system.iocache.blocked_cycles::no_mshrs             0                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.iocache.blocked::no_mshrs                    0                       # number of cycles access was blocked
system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
system.iocache.fast_writes                          0                       # number of fast writes performed
system.iocache.cache_copies                         0                       # number of cache copies performed
system.iocache.writebacks                           0                       # number of writebacks
system.iocache.demand_mshr_hits                     0                       # number of demand (read+write) MSHR hits
system.iocache.overall_mshr_hits                    0                       # number of overall MSHR hits
system.iocache.demand_mshr_misses                   0                       # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses                  0                       # number of overall MSHR misses
system.iocache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
system.iocache.demand_mshr_miss_latency             0                       # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency            0                       # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_uncacheable_latency 1308164258694                       # number of ReadReq MSHR uncacheable cycles
system.iocache.overall_mshr_uncacheable_latency 1308164258694                       # number of overall MSHR uncacheable cycles
system.iocache.demand_mshr_miss_rate::0      no_value                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::1      no_value                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total     no_value                       # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::0     no_value                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::1     no_value                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total     no_value                       # mshr miss rate for overall accesses
system.iocache.demand_avg_mshr_miss_latency     no_value                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency     no_value                       # average overall mshr miss latency
system.iocache.ReadReq_avg_mshr_uncacheable_latency          inf                       # average ReadReq mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency          inf                       # average overall mshr uncacheable latency
system.iocache.mshr_cap_events                      0                       # number of times MSHR cap was activated
system.iocache.soft_prefetch_mshr_full              0                       # number of mshr full events for SW prefetching instrutions
system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu0.kern.inst.quiesce                   55740                       # number of quiesce instructions executed
system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu1.kern.inst.quiesce                   41953                       # number of quiesce instructions executed

---------- End Simulation Statistics   ----------