211 lines
8.5 KiB
Python
211 lines
8.5 KiB
Python
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# Copyright (c) 2006-2007 The Regents of The University of Michigan
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# Copyright (c) 2009 Advanced Micro Devices, Inc.
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# Copyright (c) 2013 Mark D. Hill and David A. Wood
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# All rights reserved.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are
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# met: redistributions of source code must retain the above copyright
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# notice, this list of conditions and the following disclaimer;
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# redistributions in binary form must reproduce the above copyright
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# notice, this list of conditions and the following disclaimer in the
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# documentation and/or other materials provided with the distribution;
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# neither the name of the copyright holders nor the names of its
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# contributors may be used to endorse or promote products derived from
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# this software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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#
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# Authors: Brad Beckmann
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# Nilay Vaish
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import math
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import m5
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from m5.objects import *
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from m5.defines import buildEnv
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from Ruby import create_topology
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#
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# Note: the L1 Cache latency is only used by the sequencer on fast path hits
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#
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class L0Cache(RubyCache):
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latency = 1
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class L1Cache(RubyCache):
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latency = 5
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#
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# Note: the L2 Cache latency is not currently used
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#
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class L2Cache(RubyCache):
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latency = 15
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def define_options(parser):
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parser.add_option("--num-clusters", type="int", default=1,
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help="number of clusters in a design in which there are shared\
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caches private to clusters")
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return
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def create_system(options, system, piobus, dma_ports, ruby_system):
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if buildEnv['PROTOCOL'] != 'MESI_Three_Level':
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fatal("This script requires the MESI_Three_Level protocol to be built.")
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cpu_sequencers = []
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#
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# The ruby network creation expects the list of nodes in the system to be
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# consistent with the NetDest list. Therefore the l1 controller nodes must be
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# listed before the directory nodes and directory nodes before dma nodes, etc.
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#
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l0_cntrl_nodes = []
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l1_cntrl_nodes = []
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l2_cntrl_nodes = []
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dir_cntrl_nodes = []
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dma_cntrl_nodes = []
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assert (options.num_cpus % options.num_clusters == 0)
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num_cpus_per_cluster = options.num_cpus / options.num_clusters
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assert (options.num_l2caches % options.num_clusters == 0)
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num_l2caches_per_cluster = options.num_l2caches / options.num_clusters
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l2_bits = int(math.log(num_l2caches_per_cluster, 2))
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block_size_bits = int(math.log(options.cacheline_size, 2))
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l2_index_start = block_size_bits + l2_bits
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#
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# Must create the individual controllers before the network to ensure the
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# controller constructors are called before the network constructor
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#
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for i in xrange(options.num_clusters):
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for j in xrange(num_cpus_per_cluster):
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#
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# First create the Ruby objects associated with this cpu
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#
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l0i_cache = L0Cache(size = '4096B', assoc = 1, is_icache = True,
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start_index_bit = block_size_bits, replacement_policy="LRU")
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l0d_cache = L0Cache(size = '4096B', assoc = 1, is_icache = False,
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start_index_bit = block_size_bits, replacement_policy="LRU")
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l0_cntrl = L0Cache_Controller(version = i*num_cpus_per_cluster + j,
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Icache = l0i_cache, Dcache = l0d_cache,
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send_evictions = (options.cpu_type == "detailed"),
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ruby_system = ruby_system)
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cpu_seq = RubySequencer(version = i, icache = l0i_cache,
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dcache = l0d_cache, ruby_system = ruby_system)
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l0_cntrl.sequencer = cpu_seq
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l1_cache = L1Cache(size = options.l1d_size, assoc = options.l1d_assoc,
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start_index_bit = block_size_bits, is_icache = False)
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l1_cntrl = L1Cache_Controller(version = i*num_cpus_per_cluster+j,
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cache = l1_cache, l2_select_num_bits = l2_bits,
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cluster_id = i, ruby_system = ruby_system)
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if piobus != None:
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cpu_seq.pio_port = piobus.slave
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exec("ruby_system.l0_cntrl%d = l0_cntrl" % (
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i*num_cpus_per_cluster+j))
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exec("ruby_system.l1_cntrl%d = l1_cntrl" % (
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i*num_cpus_per_cluster+j))
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#
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# Add controllers and sequencers to the appropriate lists
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#
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cpu_sequencers.append(cpu_seq)
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l0_cntrl_nodes.append(l0_cntrl)
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l1_cntrl_nodes.append(l1_cntrl)
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l0_cntrl.peer = l1_cntrl
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for j in xrange(num_l2caches_per_cluster):
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l2_cache = L2Cache(size = options.l2_size,
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assoc = options.l2_assoc,
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start_index_bit = l2_index_start)
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l2_cntrl = L2Cache_Controller(
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version = i * num_l2caches_per_cluster + j,
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L2cache = l2_cache, cluster_id = i,
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transitions_per_cycle=options.ports,
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ruby_system = ruby_system)
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exec("ruby_system.l2_cntrl%d = l2_cntrl" % (
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i * num_l2caches_per_cluster + j))
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l2_cntrl_nodes.append(l2_cntrl)
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phys_mem_size = sum(map(lambda r: r.size(), system.mem_ranges))
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assert(phys_mem_size % options.num_dirs == 0)
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mem_module_size = phys_mem_size / options.num_dirs
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# Run each of the ruby memory controllers at a ratio of the frequency of
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# the ruby system
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# clk_divider value is a fix to pass regression.
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ruby_system.memctrl_clk_domain = DerivedClockDomain(
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clk_domain=ruby_system.clk_domain,
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clk_divider=3)
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for i in xrange(options.num_dirs):
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#
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# Create the Ruby objects associated with the directory controller
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#
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mem_cntrl = RubyMemoryControl(
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clk_domain = ruby_system.memctrl_clk_domain,
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version = i,
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ruby_system = ruby_system)
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dir_size = MemorySize('0B')
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dir_size.value = mem_module_size
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dir_cntrl = Directory_Controller(version = i,
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directory = \
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RubyDirectoryMemory(version = i,
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size = dir_size,
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use_map =
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options.use_map),
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memBuffer = mem_cntrl,
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transitions_per_cycle = options.ports,
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ruby_system = ruby_system)
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exec("ruby_system.dir_cntrl%d = dir_cntrl" % i)
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dir_cntrl_nodes.append(dir_cntrl)
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for i, dma_port in enumerate(dma_ports):
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#
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# Create the Ruby objects associated with the dma controller
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#
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dma_seq = DMASequencer(version = i,
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ruby_system = ruby_system)
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dma_cntrl = DMA_Controller(version = i,
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dma_sequencer = dma_seq,
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transitions_per_cycle = options.ports,
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ruby_system = ruby_system)
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exec("ruby_system.dma_cntrl%d = dma_cntrl" % i)
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exec("ruby_system.dma_cntrl%d.dma_sequencer.slave = dma_port" % i)
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dma_cntrl_nodes.append(dma_cntrl)
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all_cntrls = l0_cntrl_nodes + \
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l1_cntrl_nodes + \
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l2_cntrl_nodes + \
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dir_cntrl_nodes + \
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dma_cntrl_nodes
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topology = create_topology(all_cntrls, options)
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return (cpu_sequencers, dir_cntrl_nodes, topology)
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