2011-07-01 23:29:33 +02:00
|
|
|
# Copyright (c) 2009 Advanced Micro Devices, Inc.
|
|
|
|
# All rights reserved.
|
|
|
|
#
|
|
|
|
# Redistribution and use in source and binary forms, with or without
|
|
|
|
# modification, are permitted provided that the following conditions are
|
|
|
|
# met: redistributions of source code must retain the above copyright
|
|
|
|
# notice, this list of conditions and the following disclaimer;
|
|
|
|
# redistributions in binary form must reproduce the above copyright
|
|
|
|
# notice, this list of conditions and the following disclaimer in the
|
|
|
|
# documentation and/or other materials provided with the distribution;
|
|
|
|
# neither the name of the copyright holders nor the names of its
|
|
|
|
# contributors may be used to endorse or promote products derived from
|
|
|
|
# this software without specific prior written permission.
|
|
|
|
#
|
|
|
|
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
|
|
|
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
|
|
|
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
|
|
|
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
|
|
|
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
|
|
|
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
|
|
|
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
|
|
|
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
|
|
|
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
|
|
|
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
|
|
|
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
|
|
|
#
|
|
|
|
# Authors: Steve Reinhardt
|
|
|
|
# Brad Beckmann
|
|
|
|
|
|
|
|
from m5.params import *
|
|
|
|
from m5.SimObject import SimObject
|
|
|
|
from Controller import RubyController
|
|
|
|
|
|
|
|
class RubyCache(SimObject):
|
|
|
|
type = 'RubyCache'
|
|
|
|
cxx_class = 'CacheMemory'
|
2012-11-02 17:32:01 +01:00
|
|
|
cxx_header = "mem/ruby/system/CacheMemory.hh"
|
2011-07-01 23:29:33 +02:00
|
|
|
size = Param.MemorySize("capacity in bytes");
|
2013-02-11 04:26:24 +01:00
|
|
|
latency = Param.Cycles("");
|
2011-07-01 23:29:33 +02:00
|
|
|
assoc = Param.Int("");
|
|
|
|
replacement_policy = Param.String("PSEUDO_LRU", "");
|
|
|
|
start_index_bit = Param.Int(6, "index start, default 6 for 64-byte line");
|
2012-01-07 14:38:53 +01:00
|
|
|
is_icache = Param.Bool(False, "is instruction only cache");
|
2012-07-11 07:51:54 +02:00
|
|
|
|
|
|
|
dataArrayBanks = Param.Int(1, "Number of banks for the data array")
|
|
|
|
tagArrayBanks = Param.Int(1, "Number of banks for the tag array")
|
2012-09-07 18:34:38 +02:00
|
|
|
dataAccessLatency = Param.Cycles(1, "cycles for a data array access")
|
|
|
|
tagAccessLatency = Param.Cycles(1, "cycles for a tag array access")
|
2012-07-11 07:51:54 +02:00
|
|
|
resourceStalls = Param.Bool(False, "stall if there is a resource failure")
|