2011-01-18 23:30:06 +01:00
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---------- Begin Simulation Statistics ----------
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2011-05-23 17:59:13 +02:00
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sim_seconds 0.320953 # Number of seconds simulated
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sim_ticks 320953109000 # Number of ticks simulated
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2011-01-18 23:30:06 +01:00
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sim_freq 1000000000000 # Frequency of simulated ticks
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2011-05-23 17:59:13 +02:00
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host_inst_rate 40042 # Simulator instruction rate (inst/s)
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host_tick_rate 22415184 # Simulator tick rate (ticks/s)
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host_mem_usage 260460 # Number of bytes of host memory used
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host_seconds 14318.56 # Real time elapsed on the host
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sim_insts 573342262 # Number of instructions simulated
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2011-01-18 23:30:06 +01:00
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system.cpu.dtb.inst_hits 0 # ITB inst hits
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system.cpu.dtb.inst_misses 0 # ITB inst misses
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system.cpu.dtb.read_hits 0 # DTB read hits
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system.cpu.dtb.read_misses 0 # DTB read misses
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system.cpu.dtb.write_hits 0 # DTB write hits
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system.cpu.dtb.write_misses 0 # DTB write misses
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2011-05-23 17:59:13 +02:00
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system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
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system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
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system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
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system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
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system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
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system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
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system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
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system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
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system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
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system.cpu.dtb.read_accesses 0 # DTB read accesses
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system.cpu.dtb.write_accesses 0 # DTB write accesses
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system.cpu.dtb.inst_accesses 0 # ITB inst accesses
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system.cpu.dtb.hits 0 # DTB hits
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system.cpu.dtb.misses 0 # DTB misses
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system.cpu.dtb.accesses 0 # DTB accesses
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system.cpu.itb.inst_hits 0 # ITB inst hits
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system.cpu.itb.inst_misses 0 # ITB inst misses
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system.cpu.itb.read_hits 0 # DTB read hits
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system.cpu.itb.read_misses 0 # DTB read misses
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system.cpu.itb.write_hits 0 # DTB write hits
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system.cpu.itb.write_misses 0 # DTB write misses
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system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
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system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
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system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
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system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
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system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
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system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
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system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
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system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
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system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
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system.cpu.itb.read_accesses 0 # DTB read accesses
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system.cpu.itb.write_accesses 0 # DTB write accesses
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system.cpu.itb.inst_accesses 0 # ITB inst accesses
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system.cpu.itb.hits 0 # DTB hits
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system.cpu.itb.misses 0 # DTB misses
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system.cpu.itb.accesses 0 # DTB accesses
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system.cpu.workload.num_syscalls 548 # Number of system calls
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system.cpu.numCycles 641906219 # number of cpu cycles simulated
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system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
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system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
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system.cpu.BPredUnit.lookups 223949599 # Number of BP lookups
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system.cpu.BPredUnit.condPredicted 179054613 # Number of conditional branches predicted
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system.cpu.BPredUnit.condIncorrect 19156129 # Number of conditional branches incorrect
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system.cpu.BPredUnit.BTBLookups 184229626 # Number of BTB lookups
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system.cpu.BPredUnit.BTBHits 147971030 # Number of BTB hits
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system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
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system.cpu.BPredUnit.usedRAS 11972868 # Number of times the RAS was used to get a target.
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system.cpu.BPredUnit.RASInCorrect 2532941 # Number of incorrect RAS predictions.
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system.cpu.fetch.icacheStallCycles 130565917 # Number of cycles fetch is stalled on an Icache miss
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system.cpu.fetch.Insts 973113322 # Number of instructions fetch has processed
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system.cpu.fetch.Branches 223949599 # Number of branches that fetch encountered
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system.cpu.fetch.predictedBranches 159943898 # Number of branches that fetch has predicted taken
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system.cpu.fetch.Cycles 241546376 # Number of cycles fetch has run and was not squashing or blocked
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system.cpu.fetch.SquashCycles 21862580 # Number of cycles fetch has spent squashing
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system.cpu.fetch.MiscStallCycles 2406 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
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system.cpu.fetch.CacheLines 130565917 # Number of cache lines fetched
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system.cpu.fetch.IcacheSquashes 3998860 # Number of outstanding Icache misses that were squashed
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system.cpu.fetch.rateDist::samples 637850640 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::mean 1.791502 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::stdev 2.743865 # Number of instructions fetched each cycle (Total)
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2011-01-18 23:30:06 +01:00
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system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
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2011-05-23 17:59:13 +02:00
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system.cpu.fetch.rateDist::0 396316059 62.13% 62.13% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::1 20357816 3.19% 65.32% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::2 35705192 5.60% 70.92% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::3 35959525 5.64% 76.56% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::4 37219035 5.84% 82.40% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::5 17602838 2.76% 85.15% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::6 18536216 2.91% 88.06% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::7 14275483 2.24% 90.30% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::8 61878476 9.70% 100.00% # Number of instructions fetched each cycle (Total)
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2011-01-18 23:30:06 +01:00
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system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
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2011-05-23 17:59:13 +02:00
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system.cpu.fetch.rateDist::total 637850640 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.branchRate 0.348882 # Number of branch fetches per cycle
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system.cpu.fetch.rate 1.515974 # Number of inst fetches per cycle
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system.cpu.decode.IdleCycles 274650627 # Number of cycles decode is idle
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system.cpu.decode.BlockedCycles 79437827 # Number of cycles decode is blocked
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system.cpu.decode.RunCycles 227463937 # Number of cycles decode is running
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system.cpu.decode.UnblockCycles 2944119 # Number of cycles decode is unblocking
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system.cpu.decode.SquashCycles 53354130 # Number of cycles decode is squashing
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system.cpu.decode.BranchResolved 31952595 # Number of times decode resolved a branch
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system.cpu.decode.BranchMispred 76091 # Number of times decode detected a branch misprediction
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system.cpu.decode.DecodedInsts 1091620209 # Number of instructions handled by decode
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system.cpu.decode.SquashedInsts 217331 # Number of squashed instructions handled by decode
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system.cpu.rename.SquashCycles 53354130 # Number of cycles rename is squashing
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system.cpu.rename.IdleCycles 289506174 # Number of cycles rename is idle
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system.cpu.rename.BlockCycles 9893108 # Number of cycles rename is blocking
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system.cpu.rename.serializeStallCycles 49317817 # count of cycles rename stalled for serializing inst
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system.cpu.rename.RunCycles 215240896 # Number of cycles rename is running
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system.cpu.rename.UnblockCycles 20538515 # Number of cycles rename is unblocking
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system.cpu.rename.RenamedInsts 1036732054 # Number of instructions processed by rename
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system.cpu.rename.ROBFullEvents 236 # Number of times rename has blocked due to ROB full
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system.cpu.rename.IQFullEvents 6072390 # Number of times rename has blocked due to IQ full
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system.cpu.rename.LSQFullEvents 9974912 # Number of times rename has blocked due to LSQ full
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system.cpu.rename.FullRegisterEvents 19 # Number of times there has been no free registers
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system.cpu.rename.RenamedOperands 1156982067 # Number of destination operands rename has renamed
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system.cpu.rename.RenameLookups 4582431546 # Number of register rename lookups that rename has made
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system.cpu.rename.int_rename_lookups 4582430193 # Number of integer rename lookups
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system.cpu.rename.fp_rename_lookups 1353 # Number of floating rename lookups
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system.cpu.rename.CommittedMaps 672201056 # Number of HB maps that are committed
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system.cpu.rename.UndoneMaps 484781006 # Number of HB maps that are undone due to squashing
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system.cpu.rename.serializingInsts 2811540 # count of serializing insts renamed
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system.cpu.rename.tempSerializingInsts 2811485 # count of temporary serializing insts renamed
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system.cpu.rename.skidInsts 54423240 # count of insts added to the skid buffer
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system.cpu.memDep0.insertedLoads 192516932 # Number of loads inserted to the mem dependence unit.
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system.cpu.memDep0.insertedStores 113728531 # Number of stores inserted to the mem dependence unit.
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system.cpu.memDep0.conflictingLoads 52019514 # Number of conflicting loads.
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system.cpu.memDep0.conflictingStores 56045106 # Number of conflicting stores.
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system.cpu.iq.iqInstsAdded 898220409 # Number of instructions added to the IQ (excludes non-spec)
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system.cpu.iq.iqNonSpecInstsAdded 4649392 # Number of non-speculative instructions added to the IQ
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system.cpu.iq.iqInstsIssued 742085900 # Number of instructions issued
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system.cpu.iq.iqSquashedInstsIssued 4028217 # Number of squashed instructions issued
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system.cpu.iq.iqSquashedInstsExamined 325034737 # Number of squashed instructions iterated over during squash; mainly for profiling
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system.cpu.iq.iqSquashedOperandsExamined 902951971 # Number of squashed operands that are examined and possibly removed from graph
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system.cpu.iq.iqSquashedNonSpecRemoved 771526 # Number of squashed non-spec instructions that were removed
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system.cpu.iq.issued_per_cycle::samples 637850640 # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::mean 1.163416 # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::stdev 1.451606 # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::0 296239264 46.44% 46.44% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::1 133409185 20.92% 67.36% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::2 102098632 16.01% 83.37% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::3 53722534 8.42% 91.79% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::4 32322089 5.07% 96.86% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::5 11168911 1.75% 98.61% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::6 5441714 0.85% 99.46% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::7 2057834 0.32% 99.78% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::8 1390477 0.22% 100.00% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::total 637850640 # Number of insts issued each cycle
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system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
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system.cpu.iq.fu_full::IntAlu 95830 1.04% 1.04% # attempts to use FU when none available
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system.cpu.iq.fu_full::IntMult 0 0.00% 1.04% # attempts to use FU when none available
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system.cpu.iq.fu_full::IntDiv 0 0.00% 1.04% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatAdd 0 0.00% 1.04% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatCmp 0 0.00% 1.04% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatCvt 0 0.00% 1.04% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatMult 0 0.00% 1.04% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatDiv 0 0.00% 1.04% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatSqrt 0 0.00% 1.04% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdAdd 0 0.00% 1.04% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 1.04% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdAlu 0 0.00% 1.04% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdCmp 0 0.00% 1.04% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdCvt 0 0.00% 1.04% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdMisc 0 0.00% 1.04% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdMult 0 0.00% 1.04% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 1.04% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdShift 0 0.00% 1.04% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 1.04% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdSqrt 0 0.00% 1.04% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 1.04% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 1.04% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 1.04% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 1.04% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 1.04% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 1.04% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 1.04% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.04% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 1.04% # attempts to use FU when none available
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system.cpu.iq.fu_full::MemRead 5443662 59.10% 60.15% # attempts to use FU when none available
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system.cpu.iq.fu_full::MemWrite 3670689 39.85% 100.00% # attempts to use FU when none available
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system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
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system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
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system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
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system.cpu.iq.FU_type_0::IntAlu 503818075 67.89% 67.89% # Type of FU issued
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system.cpu.iq.FU_type_0::IntMult 366199 0.05% 67.94% # Type of FU issued
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system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.94% # Type of FU issued
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system.cpu.iq.FU_type_0::FloatAdd 82 0.00% 67.94% # Type of FU issued
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system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.94% # Type of FU issued
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system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.94% # Type of FU issued
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system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.94% # Type of FU issued
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system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.94% # Type of FU issued
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|
|
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.94% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.94% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.94% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.94% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.94% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.94% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.94% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.94% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.94% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.94% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.94% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.94% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.94% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.94% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.94% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.94% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.94% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.00% 67.94% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.94% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.94% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.94% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::MemRead 163695097 22.06% 90.00% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::MemWrite 74206444 10.00% 100.00% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::total 742085900 # Type of FU issued
|
|
|
|
|
system.cpu.iq.rate 1.156066 # Inst issue rate
|
|
|
|
|
system.cpu.iq.fu_busy_cnt 9210181 # FU busy when requested
|
|
|
|
|
system.cpu.iq.fu_busy_rate 0.012411 # FU busy rate (busy events/executed inst)
|
|
|
|
|
system.cpu.iq.int_inst_queue_reads 2135260638 # Number of integer instruction queue reads
|
|
|
|
|
system.cpu.iq.int_inst_queue_writes 1228450518 # Number of integer instruction queue writes
|
|
|
|
|
system.cpu.iq.int_inst_queue_wakeup_accesses 694522935 # Number of integer instruction queue wakeup accesses
|
|
|
|
|
system.cpu.iq.fp_inst_queue_reads 200 # Number of floating instruction queue reads
|
|
|
|
|
system.cpu.iq.fp_inst_queue_writes 304 # Number of floating instruction queue writes
|
|
|
|
|
system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses
|
|
|
|
|
system.cpu.iq.int_alu_accesses 751295979 # Number of integer alu accesses
|
|
|
|
|
system.cpu.iq.fp_alu_accesses 102 # Number of floating point alu accesses
|
|
|
|
|
system.cpu.iew.lsq.thread0.forwLoads 5771553 # Number of loads that had data forwarded from stores
|
|
|
|
|
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
|
|
|
|
system.cpu.iew.lsq.thread0.squashedLoads 65743781 # Number of loads squashed
|
|
|
|
|
system.cpu.iew.lsq.thread0.ignoredResponses 15629 # Number of memory responses ignored because the instruction is squashed
|
|
|
|
|
system.cpu.iew.lsq.thread0.memOrderViolation 596063 # Number of memory ordering violations
|
|
|
|
|
system.cpu.iew.lsq.thread0.squashedStores 56124460 # Number of stores squashed
|
|
|
|
|
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
|
|
|
|
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
|
|
|
|
system.cpu.iew.lsq.thread0.rescheduledLoads 24980 # Number of loads that were rescheduled
|
|
|
|
|
system.cpu.iew.lsq.thread0.cacheBlocked 144 # Number of times an access to memory failed due to the cache being blocked
|
|
|
|
|
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
|
|
|
|
system.cpu.iew.iewSquashCycles 53354130 # Number of cycles IEW is squashing
|
|
|
|
|
system.cpu.iew.iewBlockCycles 2618576 # Number of cycles IEW is blocking
|
|
|
|
|
system.cpu.iew.iewUnblockCycles 142825 # Number of cycles IEW is unblocking
|
|
|
|
|
system.cpu.iew.iewDispatchedInsts 912051296 # Number of instructions dispatched to IQ
|
|
|
|
|
system.cpu.iew.iewDispSquashedInsts 21556193 # Number of squashed instructions skipped by dispatch
|
|
|
|
|
system.cpu.iew.iewDispLoadInsts 192516932 # Number of dispatched load instructions
|
|
|
|
|
system.cpu.iew.iewDispStoreInsts 113728531 # Number of dispatched store instructions
|
|
|
|
|
system.cpu.iew.iewDispNonSpecInsts 2788498 # Number of dispatched non-speculative instructions
|
|
|
|
|
system.cpu.iew.iewIQFullEvents 84227 # Number of times the IQ has become full, causing a stall
|
|
|
|
|
system.cpu.iew.iewLSQFullEvents 8711 # Number of times the LSQ has become full, causing a stall
|
|
|
|
|
system.cpu.iew.memOrderViolationEvents 596063 # Number of memory order violations
|
|
|
|
|
system.cpu.iew.predictedTakenIncorrect 17931306 # Number of branches that were predicted taken incorrectly
|
|
|
|
|
system.cpu.iew.predictedNotTakenIncorrect 6522754 # Number of branches that were predicted not taken incorrectly
|
|
|
|
|
system.cpu.iew.branchMispredicts 24454060 # Number of branch mispredicts detected at execute
|
|
|
|
|
system.cpu.iew.iewExecutedInsts 711877956 # Number of executed instructions
|
|
|
|
|
system.cpu.iew.iewExecLoadInsts 154430876 # Number of load instructions executed
|
|
|
|
|
system.cpu.iew.iewExecSquashedInsts 30207944 # Number of squashed instructions skipped in execute
|
|
|
|
|
system.cpu.iew.exec_swp 0 # number of swp insts executed
|
|
|
|
|
system.cpu.iew.exec_nop 9181495 # number of nop insts executed
|
|
|
|
|
system.cpu.iew.exec_refs 222561224 # number of memory reference insts executed
|
|
|
|
|
system.cpu.iew.exec_branches 143781551 # Number of branches executed
|
|
|
|
|
system.cpu.iew.exec_stores 68130348 # Number of stores executed
|
|
|
|
|
system.cpu.iew.exec_rate 1.109006 # Inst execution rate
|
|
|
|
|
system.cpu.iew.wb_sent 704134955 # cumulative count of insts sent to commit
|
|
|
|
|
system.cpu.iew.wb_count 694522951 # cumulative count of insts written-back
|
|
|
|
|
system.cpu.iew.wb_producers 388125156 # num instructions producing a value
|
|
|
|
|
system.cpu.iew.wb_consumers 688020690 # num instructions consuming a value
|
|
|
|
|
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
|
|
|
|
system.cpu.iew.wb_rate 1.081970 # insts written-back per cycle
|
|
|
|
|
system.cpu.iew.wb_fanout 0.564118 # average fanout of values written-back
|
|
|
|
|
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
|
|
|
|
system.cpu.commit.commitCommittedInsts 574686146 # The number of committed instructions
|
|
|
|
|
system.cpu.commit.commitSquashedInsts 337368429 # The number of squashed insts skipped by commit
|
|
|
|
|
system.cpu.commit.commitNonSpecStalls 3877866 # The number of times commit has been forced to stall to communicate backwards
|
|
|
|
|
system.cpu.commit.branchMispredicts 21251956 # The number of times a branch was mispredicted
|
|
|
|
|
system.cpu.commit.committed_per_cycle::samples 584496511 # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::mean 0.983216 # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::stdev 1.594536 # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::0 311654164 53.32% 53.32% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::1 150316632 25.72% 79.04% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::2 55227209 9.45% 88.49% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::3 24753339 4.23% 92.72% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::4 15848741 2.71% 95.43% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::5 6546524 1.12% 96.55% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::6 7691194 1.32% 97.87% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::7 2289333 0.39% 98.26% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::8 10169375 1.74% 100.00% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::total 584496511 # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.count 574686146 # Number of instructions committed
|
|
|
|
|
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
|
|
|
|
|
system.cpu.commit.refs 184377221 # Number of memory references committed
|
|
|
|
|
system.cpu.commit.loads 126773150 # Number of loads committed
|
|
|
|
|
system.cpu.commit.membars 1488542 # Number of memory barriers committed
|
|
|
|
|
system.cpu.commit.branches 120192335 # Number of branches committed
|
|
|
|
|
system.cpu.commit.fp_insts 16 # Number of committed floating point instructions.
|
|
|
|
|
system.cpu.commit.int_insts 473702077 # Number of committed integer instructions.
|
|
|
|
|
system.cpu.commit.function_calls 9757362 # Number of function calls committed.
|
|
|
|
|
system.cpu.commit.bw_lim_events 10169375 # number cycles where commit BW limit reached
|
|
|
|
|
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
|
|
|
|
|
system.cpu.rob.rob_reads 1486374573 # The number of ROB reads
|
|
|
|
|
system.cpu.rob.rob_writes 1877592139 # The number of ROB writes
|
|
|
|
|
system.cpu.timesIdled 93100 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
|
|
|
|
system.cpu.idleCycles 4055579 # Total number of cycles that the CPU has spent unscheduled due to idling
|
|
|
|
|
system.cpu.committedInsts 573342262 # Number of Instructions Simulated
|
|
|
|
|
system.cpu.committedInsts_total 573342262 # Number of Instructions Simulated
|
|
|
|
|
system.cpu.cpi 1.119586 # CPI: Cycles Per Instruction
|
|
|
|
|
system.cpu.cpi_total 1.119586 # CPI: Total CPI of All Threads
|
|
|
|
|
system.cpu.ipc 0.893187 # IPC: Instructions Per Cycle
|
|
|
|
|
system.cpu.ipc_total 0.893187 # IPC: Total IPC of All Threads
|
|
|
|
|
system.cpu.int_regfile_reads 3288876394 # number of integer regfile reads
|
|
|
|
|
system.cpu.int_regfile_writes 807633235 # number of integer regfile writes
|
2011-02-08 04:23:13 +01:00
|
|
|
system.cpu.fp_regfile_reads 16 # number of floating regfile reads
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.misc_regfile_reads 1209708694 # number of misc regfile reads
|
|
|
|
|
system.cpu.misc_regfile_writes 4464272 # number of misc regfile writes
|
|
|
|
|
system.cpu.icache.replacements 11767 # number of replacements
|
|
|
|
|
system.cpu.icache.tagsinuse 1053.166926 # Cycle average of tags in use
|
|
|
|
|
system.cpu.icache.total_refs 130550979 # Total number of references to valid blocks.
|
|
|
|
|
system.cpu.icache.sampled_refs 13545 # Sample count of references to valid blocks.
|
|
|
|
|
system.cpu.icache.avg_refs 9638.315172 # Average number of references to valid blocks.
|
|
|
|
|
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
|
|
|
system.cpu.icache.occ_blocks::0 1053.166926 # Average occupied blocks per context
|
|
|
|
|
system.cpu.icache.occ_percent::0 0.514242 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.icache.ReadReq_hits 130550990 # number of ReadReq hits
|
|
|
|
|
system.cpu.icache.demand_hits 130550990 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.icache.overall_hits 130550990 # number of overall hits
|
|
|
|
|
system.cpu.icache.ReadReq_misses 14927 # number of ReadReq misses
|
|
|
|
|
system.cpu.icache.demand_misses 14927 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.icache.overall_misses 14927 # number of overall misses
|
|
|
|
|
system.cpu.icache.ReadReq_miss_latency 215353500 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.icache.demand_miss_latency 215353500 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.icache.overall_miss_latency 215353500 # number of overall miss cycles
|
|
|
|
|
system.cpu.icache.ReadReq_accesses 130565917 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.icache.demand_accesses 130565917 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.icache.overall_accesses 130565917 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.icache.ReadReq_miss_rate 0.000114 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.icache.demand_miss_rate 0.000114 # miss rate for demand accesses
|
|
|
|
|
system.cpu.icache.overall_miss_rate 0.000114 # miss rate for overall accesses
|
|
|
|
|
system.cpu.icache.ReadReq_avg_miss_latency 14427.111945 # average ReadReq miss latency
|
|
|
|
|
system.cpu.icache.demand_avg_miss_latency 14427.111945 # average overall miss latency
|
|
|
|
|
system.cpu.icache.overall_avg_miss_latency 14427.111945 # average overall miss latency
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
|
|
|
|
system.cpu.icache.writebacks 2 # number of writebacks
|
|
|
|
|
system.cpu.icache.ReadReq_mshr_hits 1072 # number of ReadReq MSHR hits
|
|
|
|
|
system.cpu.icache.demand_mshr_hits 1072 # number of demand (read+write) MSHR hits
|
|
|
|
|
system.cpu.icache.overall_mshr_hits 1072 # number of overall MSHR hits
|
|
|
|
|
system.cpu.icache.ReadReq_mshr_misses 13855 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.icache.demand_mshr_misses 13855 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.icache.overall_mshr_misses 13855 # number of overall MSHR misses
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.icache.ReadReq_mshr_miss_latency 147833000 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.icache.demand_mshr_miss_latency 147833000 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.icache.overall_mshr_miss_latency 147833000 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
|
|
|
|
system.cpu.icache.ReadReq_mshr_miss_rate 0.000106 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.icache.demand_mshr_miss_rate 0.000106 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.icache.overall_mshr_miss_rate 0.000106 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency 10670.010826 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.icache.demand_avg_mshr_miss_latency 10670.010826 # average overall mshr miss latency
|
|
|
|
|
system.cpu.icache.overall_avg_mshr_miss_latency 10670.010826 # average overall mshr miss latency
|
|
|
|
|
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
|
|
|
|
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
|
|
|
system.cpu.dcache.replacements 1189612 # number of replacements
|
|
|
|
|
system.cpu.dcache.tagsinuse 4060.806862 # Cycle average of tags in use
|
|
|
|
|
system.cpu.dcache.total_refs 200134121 # Total number of references to valid blocks.
|
|
|
|
|
system.cpu.dcache.sampled_refs 1193708 # Sample count of references to valid blocks.
|
|
|
|
|
system.cpu.dcache.avg_refs 167.657518 # Average number of references to valid blocks.
|
|
|
|
|
system.cpu.dcache.warmup_cycle 6159317000 # Cycle when the warmup percentage was hit.
|
|
|
|
|
system.cpu.dcache.occ_blocks::0 4060.806862 # Average occupied blocks per context
|
|
|
|
|
system.cpu.dcache.occ_percent::0 0.991408 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.dcache.ReadReq_hits 142442366 # number of ReadReq hits
|
|
|
|
|
system.cpu.dcache.WriteReq_hits 52854608 # number of WriteReq hits
|
|
|
|
|
system.cpu.dcache.LoadLockedReq_hits 2604415 # number of LoadLockedReq hits
|
|
|
|
|
system.cpu.dcache.StoreCondReq_hits 2232135 # number of StoreCondReq hits
|
|
|
|
|
system.cpu.dcache.demand_hits 195296974 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.dcache.overall_hits 195296974 # number of overall hits
|
|
|
|
|
system.cpu.dcache.ReadReq_misses 1102250 # number of ReadReq misses
|
|
|
|
|
system.cpu.dcache.WriteReq_misses 1384698 # number of WriteReq misses
|
|
|
|
|
system.cpu.dcache.LoadLockedReq_misses 36 # number of LoadLockedReq misses
|
|
|
|
|
system.cpu.dcache.demand_misses 2486948 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.dcache.overall_misses 2486948 # number of overall misses
|
|
|
|
|
system.cpu.dcache.ReadReq_miss_latency 11846428500 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.dcache.WriteReq_miss_latency 20406027500 # number of WriteReq miss cycles
|
|
|
|
|
system.cpu.dcache.LoadLockedReq_miss_latency 313000 # number of LoadLockedReq miss cycles
|
|
|
|
|
system.cpu.dcache.demand_miss_latency 32252456000 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.dcache.overall_miss_latency 32252456000 # number of overall miss cycles
|
|
|
|
|
system.cpu.dcache.ReadReq_accesses 143544616 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.dcache.WriteReq_accesses 54239306 # number of WriteReq accesses(hits+misses)
|
|
|
|
|
system.cpu.dcache.LoadLockedReq_accesses 2604451 # number of LoadLockedReq accesses(hits+misses)
|
|
|
|
|
system.cpu.dcache.StoreCondReq_accesses 2232135 # number of StoreCondReq accesses(hits+misses)
|
|
|
|
|
system.cpu.dcache.demand_accesses 197783922 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.dcache.overall_accesses 197783922 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.dcache.ReadReq_miss_rate 0.007679 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.dcache.WriteReq_miss_rate 0.025529 # miss rate for WriteReq accesses
|
|
|
|
|
system.cpu.dcache.LoadLockedReq_miss_rate 0.000014 # miss rate for LoadLockedReq accesses
|
|
|
|
|
system.cpu.dcache.demand_miss_rate 0.012574 # miss rate for demand accesses
|
|
|
|
|
system.cpu.dcache.overall_miss_rate 0.012574 # miss rate for overall accesses
|
|
|
|
|
system.cpu.dcache.ReadReq_avg_miss_latency 10747.496938 # average ReadReq miss latency
|
|
|
|
|
system.cpu.dcache.WriteReq_avg_miss_latency 14736.807232 # average WriteReq miss latency
|
|
|
|
|
system.cpu.dcache.LoadLockedReq_avg_miss_latency 8694.444444 # average LoadLockedReq miss latency
|
|
|
|
|
system.cpu.dcache.demand_avg_miss_latency 12968.689333 # average overall miss latency
|
|
|
|
|
system.cpu.dcache.overall_avg_miss_latency 12968.689333 # average overall miss latency
|
|
|
|
|
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.dcache.blocked_cycles::no_targets 172500 # number of cycles access was blocked
|
|
|
|
|
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.dcache.blocked::no_targets 32 # number of cycles access was blocked
|
|
|
|
|
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.dcache.avg_blocked_cycles::no_targets 5390.625000 # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
|
|
|
|
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
|
|
|
|
system.cpu.dcache.writebacks 1065401 # number of writebacks
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_hits 244002 # number of ReadReq MSHR hits
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_hits 1048961 # number of WriteReq MSHR hits
|
|
|
|
|
system.cpu.dcache.LoadLockedReq_mshr_hits 36 # number of LoadLockedReq MSHR hits
|
|
|
|
|
system.cpu.dcache.demand_mshr_hits 1292963 # number of demand (read+write) MSHR hits
|
|
|
|
|
system.cpu.dcache.overall_mshr_hits 1292963 # number of overall MSHR hits
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_misses 858248 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_misses 335737 # number of WriteReq MSHR misses
|
|
|
|
|
system.cpu.dcache.demand_mshr_misses 1193985 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.dcache.overall_mshr_misses 1193985 # number of overall MSHR misses
|
|
|
|
|
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency 6157877500 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency 4228090500 # number of WriteReq MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.demand_mshr_miss_latency 10385968000 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.overall_mshr_miss_latency 10385968000 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate 0.005979 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate 0.006190 # mshr miss rate for WriteReq accesses
|
|
|
|
|
system.cpu.dcache.demand_mshr_miss_rate 0.006037 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.dcache.overall_mshr_miss_rate 0.006037 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 7174.939528 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 12593.460060 # average WriteReq mshr miss latency
|
|
|
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency 8698.574940 # average overall mshr miss latency
|
|
|
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency 8698.574940 # average overall mshr miss latency
|
|
|
|
|
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
|
|
|
|
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
|
|
|
|
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
|
|
|
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
|
|
|
system.cpu.l2cache.replacements 214616 # number of replacements
|
|
|
|
|
system.cpu.l2cache.tagsinuse 21258.843371 # Cycle average of tags in use
|
|
|
|
|
system.cpu.l2cache.total_refs 1538764 # Total number of references to valid blocks.
|
|
|
|
|
system.cpu.l2cache.sampled_refs 234845 # Sample count of references to valid blocks.
|
|
|
|
|
system.cpu.l2cache.avg_refs 6.552254 # Average number of references to valid blocks.
|
|
|
|
|
system.cpu.l2cache.warmup_cycle 231195370000 # Cycle when the warmup percentage was hit.
|
|
|
|
|
system.cpu.l2cache.occ_blocks::0 7817.837138 # Average occupied blocks per context
|
|
|
|
|
system.cpu.l2cache.occ_blocks::1 13441.006233 # Average occupied blocks per context
|
|
|
|
|
system.cpu.l2cache.occ_percent::0 0.238581 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.l2cache.occ_percent::1 0.410187 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.l2cache.ReadReq_hits 742273 # number of ReadReq hits
|
|
|
|
|
system.cpu.l2cache.Writeback_hits 1065403 # number of Writeback hits
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_hits 160 # number of UpgradeReq hits
|
|
|
|
|
system.cpu.l2cache.ReadExReq_hits 231247 # number of ReadExReq hits
|
|
|
|
|
system.cpu.l2cache.demand_hits 973520 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.l2cache.overall_hits 973520 # number of overall hits
|
|
|
|
|
system.cpu.l2cache.ReadReq_misses 129152 # number of ReadReq misses
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_misses 112 # number of UpgradeReq misses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_misses 104568 # number of ReadExReq misses
|
|
|
|
|
system.cpu.l2cache.demand_misses 233720 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.l2cache.overall_misses 233720 # number of overall misses
|
|
|
|
|
system.cpu.l2cache.ReadReq_miss_latency 4416243000 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_miss_latency 547000 # number of UpgradeReq miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadExReq_miss_latency 3581590000 # number of ReadExReq miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_miss_latency 7997833000 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_miss_latency 7997833000 # number of overall miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadReq_accesses 871425 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.Writeback_accesses 1065403 # number of Writeback accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_accesses 272 # number of UpgradeReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.ReadExReq_accesses 335815 # number of ReadExReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.demand_accesses 1207240 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.overall_accesses 1207240 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_miss_rate 0.148208 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_miss_rate 0.411765 # miss rate for UpgradeReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_miss_rate 0.311386 # miss rate for ReadExReq accesses
|
|
|
|
|
system.cpu.l2cache.demand_miss_rate 0.193599 # miss rate for demand accesses
|
|
|
|
|
system.cpu.l2cache.overall_miss_rate 0.193599 # miss rate for overall accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency 34194.151078 # average ReadReq miss latency
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_avg_miss_latency 4883.928571 # average UpgradeReq miss latency
|
|
|
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency 34251.300589 # average ReadExReq miss latency
|
|
|
|
|
system.cpu.l2cache.demand_avg_miss_latency 34219.720178 # average overall miss latency
|
|
|
|
|
system.cpu.l2cache.overall_avg_miss_latency 34219.720178 # average overall miss latency
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.l2cache.writebacks 169760 # number of writebacks
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_hits 15 # number of ReadReq MSHR hits
|
2011-05-14 00:29:27 +02:00
|
|
|
system.cpu.l2cache.demand_mshr_hits 15 # number of demand (read+write) MSHR hits
|
|
|
|
|
system.cpu.l2cache.overall_mshr_hits 15 # number of overall MSHR hits
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.l2cache.ReadReq_mshr_misses 129137 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_mshr_misses 112 # number of UpgradeReq MSHR misses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_mshr_misses 104568 # number of ReadExReq MSHR misses
|
|
|
|
|
system.cpu.l2cache.demand_mshr_misses 233705 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.l2cache.overall_mshr_misses 233705 # number of overall MSHR misses
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency 4006675000 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 3473000 # number of UpgradeReq MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency 3242222500 # number of ReadExReq MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_mshr_miss_latency 7248897500 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_mshr_miss_latency 7248897500 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.148191 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 0.411765 # mshr miss rate for UpgradeReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.311386 # mshr miss rate for ReadExReq accesses
|
|
|
|
|
system.cpu.l2cache.demand_mshr_miss_rate 0.193586 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.l2cache.overall_mshr_miss_rate 0.193586 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31026.545452 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31008.928571 # average UpgradeReq mshr miss latency
|
|
|
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31005.876559 # average ReadExReq mshr miss latency
|
|
|
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency 31017.297448 # average overall mshr miss latency
|
|
|
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency 31017.297448 # average overall mshr miss latency
|
|
|
|
|
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
|
|
|
|
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
2011-01-18 23:30:06 +01:00
|
|
|
|
|
|
|
|
---------- End Simulation Statistics ----------
|
