177 lines
5.8 KiB
Python
177 lines
5.8 KiB
Python
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# Copyright (c) 2013-2014 ARM Limited
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# All rights reserved.
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#
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# The license below extends only to copyright in the software and shall
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# not be construed as granting a license to any other intellectual
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# property including but not limited to intellectual property relating
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# to a hardware implementation of the functionality of the software
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# licensed hereunder. You may use the software subject to the license
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# terms below provided that you ensure that this notice is replicated
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# unmodified and in its entirety in all distributions of the software,
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# modified or unmodified, in source code or in binary form.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are
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# met: redistributions of source code must retain the above copyright
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# notice, this list of conditions and the following disclaimer;
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# redistributions in binary form must reproduce the above copyright
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# notice, this list of conditions and the following disclaimer in the
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# documentation and/or other materials provided with the distribution;
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# neither the name of the copyright holders nor the names of its
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# contributors may be used to endorse or promote products derived from
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# this software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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#
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# Authors: Andrew Bardsley
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from m5.params import *
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from m5.SimObject import SimObject
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# These classes define an expression language over uint64_t with only
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# a few operators. This can be used to form expressions for the extra
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# delay required in variable execution time instructions.
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#
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# Expressions, in evaluation, will have access to the ThreadContext and
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# a StaticInst
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class TimingExpr(SimObject):
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type = 'TimingExpr'
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cxx_header = 'cpu/timing_expr.hh'
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abstract = True;
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class TimingExprLiteral(TimingExpr):
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"""Literal 64 bit unsigned value"""
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type = 'TimingExprLiteral'
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cxx_header = 'cpu/timing_expr.hh'
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value = Param.UInt64("literal value")
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def set_params(self, value):
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self.value = value
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return self
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class TimingExpr0(TimingExprLiteral):
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"""Convenient 0"""
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value = 0
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class TimingExprSrcReg(TimingExpr):
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"""Find the source register number from the current inst"""
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type = 'TimingExprSrcReg'
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cxx_header = 'cpu/timing_expr.hh'
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# index = Param.Unsigned("index into inst src regs")
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index = Param.Unsigned("index into inst src regs")
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def set_params(self, index):
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self.index = index
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return self
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class TimingExprReadIntReg(TimingExpr):
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"""Read an architectural register"""
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type = 'TimingExprReadIntReg'
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cxx_header = 'cpu/timing_expr.hh'
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reg = Param.TimingExpr("register raw index to read")
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def set_params(self, reg):
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self.reg = reg
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return self
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class TimingExprLet(TimingExpr):
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"""Block of declarations"""
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type = 'TimingExprLet'
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cxx_header = 'cpu/timing_expr.hh'
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defns = VectorParam.TimingExpr("expressions for bindings")
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expr = Param.TimingExpr("body expression")
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def set_params(self, defns, expr):
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self.defns = defns
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self.expr = expr
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return self
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class TimingExprRef(TimingExpr):
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"""Value of a bound sub-expression"""
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type = 'TimingExprRef'
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cxx_header = 'cpu/timing_expr.hh'
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index = Param.Unsigned("expression index")
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def set_params(self, index):
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self.index = index
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return self
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class TimingExprOp(Enum):
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vals = [
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'timingExprAdd', 'timingExprSub',
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'timingExprUMul', 'timingExprUDiv',
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'timingExprSMul', 'timingExprSDiv',
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'timingExprUCeilDiv', # Unsigned divide rounding up
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'timingExprEqual', 'timingExprNotEqual',
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'timingExprULessThan',
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'timingExprUGreaterThan',
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'timingExprSLessThan',
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'timingExprSGreaterThan',
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'timingExprInvert',
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'timingExprNot',
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'timingExprAnd',
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'timingExprOr',
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'timingExprSizeInBits',
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'timingExprSignExtend32To64',
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'timingExprAbs'
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]
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class TimingExprUn(TimingExpr):
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"""Unary operator"""
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type = 'TimingExprUn'
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cxx_header = 'cpu/timing_expr.hh'
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op = Param.TimingExprOp("operator")
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arg = Param.TimingExpr("expression")
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def set_params(self, op, arg):
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self.op = op
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self.arg = arg
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return self
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class TimingExprBin(TimingExpr):
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"""Binary operator"""
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type = 'TimingExprBin'
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cxx_header = 'cpu/timing_expr.hh'
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op = Param.TimingExprOp("operator")
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left = Param.TimingExpr("LHS expression")
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right = Param.TimingExpr("RHS expression")
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def set_params(self, op, left, right):
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self.op = op
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self.left = left
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self.right = right
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return self
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class TimingExprIf(TimingExpr):
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"""If-then-else operator"""
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type = 'TimingExprIf'
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cxx_header = 'cpu/timing_expr.hh'
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cond = Param.TimingExpr("condition expression")
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trueExpr = Param.TimingExpr("true expression")
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falseExpr = Param.TimingExpr("false expression")
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def set_params(self, cond, trueExpr, falseExpr):
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self.cond = cond
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self.trueExpr = trueExpr
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self.falseExpr = falseExpr
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return self
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