2011-02-23 22:35:25 +01:00
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---------- Begin Simulation Statistics ----------
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2011-06-20 03:43:42 +02:00
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sim_seconds 0.279017 # Number of seconds simulated
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sim_ticks 279017416500 # Number of ticks simulated
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2011-02-23 22:35:25 +01:00
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sim_freq 1000000000000 # Frequency of simulated ticks
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2011-06-20 03:43:42 +02:00
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host_inst_rate 128000 # Simulator instruction rate (inst/s)
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host_tick_rate 59339940 # Simulator tick rate (ticks/s)
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host_mem_usage 192984 # Number of bytes of host memory used
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host_seconds 4702.02 # Real time elapsed on the host
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2011-02-23 22:35:25 +01:00
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sim_insts 601856964 # Number of instructions simulated
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2011-06-20 03:43:42 +02:00
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system.cpu.dtb.fetch_hits 0 # ITB hits
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system.cpu.dtb.fetch_misses 0 # ITB misses
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system.cpu.dtb.fetch_acv 0 # ITB acv
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system.cpu.dtb.fetch_accesses 0 # ITB accesses
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system.cpu.dtb.read_hits 114517555 # DTB read hits
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system.cpu.dtb.read_misses 2631 # DTB read misses
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system.cpu.dtb.read_acv 0 # DTB read access violations
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system.cpu.dtb.read_accesses 114520186 # DTB read accesses
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system.cpu.dtb.write_hits 39666604 # DTB write hits
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system.cpu.dtb.write_misses 2302 # DTB write misses
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system.cpu.dtb.write_acv 0 # DTB write access violations
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system.cpu.dtb.write_accesses 39668906 # DTB write accesses
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system.cpu.dtb.data_hits 154184159 # DTB hits
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system.cpu.dtb.data_misses 4933 # DTB misses
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system.cpu.dtb.data_acv 0 # DTB access violations
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system.cpu.dtb.data_accesses 154189092 # DTB accesses
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system.cpu.itb.fetch_hits 29078095 # ITB hits
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system.cpu.itb.fetch_misses 22 # ITB misses
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system.cpu.itb.fetch_acv 0 # ITB acv
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system.cpu.itb.fetch_accesses 29078117 # ITB accesses
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system.cpu.itb.read_hits 0 # DTB read hits
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system.cpu.itb.read_misses 0 # DTB read misses
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system.cpu.itb.read_acv 0 # DTB read access violations
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system.cpu.itb.read_accesses 0 # DTB read accesses
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system.cpu.itb.write_hits 0 # DTB write hits
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system.cpu.itb.write_misses 0 # DTB write misses
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system.cpu.itb.write_acv 0 # DTB write access violations
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system.cpu.itb.write_accesses 0 # DTB write accesses
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system.cpu.itb.data_hits 0 # DTB hits
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system.cpu.itb.data_misses 0 # DTB misses
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system.cpu.itb.data_acv 0 # DTB access violations
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system.cpu.itb.data_accesses 0 # DTB accesses
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system.cpu.workload.num_syscalls 17 # Number of system calls
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system.cpu.numCycles 558034834 # number of cpu cycles simulated
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system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
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system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
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system.cpu.contextSwitches 1 # Number of context switches
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system.cpu.threadCycles 547808694 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
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system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode
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system.cpu.timesIdled 412073 # Number of times that the entire CPU went into an idle state and unscheduled itself
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system.cpu.idleCycles 61249901 # Number of cycles cpu's stages were not processed
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system.cpu.runCycles 496784933 # Number of cycles cpu stages are processed.
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system.cpu.activity 89.024000 # Percentage of cycles cpu is active
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2011-02-23 22:35:25 +01:00
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system.cpu.comLoads 114514042 # Number of Load instructions committed
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system.cpu.comStores 39451321 # Number of Store instructions committed
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2011-06-20 03:43:42 +02:00
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system.cpu.comBranches 62547159 # Number of Branches instructions committed
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system.cpu.comNops 36304520 # Number of Nop instructions committed
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system.cpu.comNonSpec 17 # Number of Non-Speculative instructions committed
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system.cpu.comInts 349039879 # Number of Integer instructions committed
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system.cpu.comFloats 24 # Number of Floating Point instructions committed
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2011-02-23 22:35:25 +01:00
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system.cpu.committedInsts 601856964 # Number of Instructions Simulated (Per-Thread)
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2011-06-20 03:43:42 +02:00
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system.cpu.smtCommittedInsts 0 # Number of SMT Instructions Simulated (Per-Thread)
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2011-02-23 22:35:25 +01:00
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system.cpu.committedInsts_total 601856964 # Number of Instructions Simulated (Total)
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2011-06-20 03:43:42 +02:00
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system.cpu.cpi 0.927188 # CPI: Cycles Per Instruction (Per-Thread)
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system.cpu.smt_cpi no_value # CPI: Total SMT-CPI
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system.cpu.cpi_total 0.927188 # CPI: Total CPI of All Threads
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system.cpu.ipc 1.078529 # IPC: Instructions Per Cycle (Per-Thread)
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system.cpu.smt_ipc no_value # IPC: Total SMT-IPC
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system.cpu.ipc_total 1.078529 # IPC: Total IPC of All Threads
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system.cpu.branch_predictor.lookups 90037625 # Number of BP lookups
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system.cpu.branch_predictor.condPredicted 84897563 # Number of conditional branches predicted
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system.cpu.branch_predictor.condIncorrect 39773148 # Number of conditional branches incorrect
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system.cpu.branch_predictor.BTBLookups 49497029 # Number of BTB lookups
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system.cpu.branch_predictor.BTBHits 39091844 # Number of BTB hits
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system.cpu.branch_predictor.usedRAS 1197609 # Number of times the RAS was used to get a target.
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system.cpu.branch_predictor.RASInCorrect 6 # Number of incorrect RAS predictions.
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system.cpu.branch_predictor.BTBHitPct 78.978163 # BTB Hit Percentage
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system.cpu.branch_predictor.predictedTaken 41686827 # Number of Branches Predicted As Taken (True).
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system.cpu.branch_predictor.predictedNotTaken 48350798 # Number of Branches Predicted As Not Taken (False).
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system.cpu.regfile_manager.intRegFileReads 541420411 # Number of Reads from Int. Register File
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system.cpu.regfile_manager.intRegFileWrites 463854846 # Number of Writes to Int. Register File
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system.cpu.regfile_manager.intRegFileAccesses 1005275257 # Total Accesses (Read+Write) to the Int. Register File
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system.cpu.regfile_manager.floatRegFileReads 162 # Number of Reads from FP Register File
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system.cpu.regfile_manager.floatRegFileWrites 42 # Number of Writes to FP Register File
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system.cpu.regfile_manager.floatRegFileAccesses 204 # Total Accesses (Read+Write) to the FP Register File
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system.cpu.regfile_manager.regForwards 257533113 # Number of Registers Read Through Forwarding Logic
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system.cpu.agen_unit.agens 154627572 # Number of Address Generations
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system.cpu.execution_unit.predictedTakenIncorrect 38276366 # Number of Branches Incorrectly Predicted As Taken.
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system.cpu.execution_unit.predictedNotTakenIncorrect 1491795 # Number of Branches Incorrectly Predicted As Not Taken).
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system.cpu.execution_unit.mispredicted 39768161 # Number of Branches Incorrectly Predicted
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system.cpu.execution_unit.predicted 22779717 # Number of Branches Incorrectly Predicted
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system.cpu.execution_unit.mispredictPct 63.580352 # Percentage of Incorrect Branches Predicts
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system.cpu.execution_unit.executions 411890550 # Number of Instructions Executed.
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system.cpu.mult_div_unit.multiplies 6482 # Number of Multipy Operations Executed
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system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed
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system.cpu.stage0.idleCycles 210144173 # Number of cycles 0 instructions are processed.
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system.cpu.stage0.runCycles 347890661 # Number of cycles 1+ instructions are processed.
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system.cpu.stage0.utilization 62.342105 # Percentage of cycles stage was utilized (processing insts).
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system.cpu.stage1.idleCycles 246346046 # Number of cycles 0 instructions are processed.
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system.cpu.stage1.runCycles 311688788 # Number of cycles 1+ instructions are processed.
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system.cpu.stage1.utilization 55.854719 # Percentage of cycles stage was utilized (processing insts).
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system.cpu.stage2.idleCycles 214904658 # Number of cycles 0 instructions are processed.
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system.cpu.stage2.runCycles 343130176 # Number of cycles 1+ instructions are processed.
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system.cpu.stage2.utilization 61.489025 # Percentage of cycles stage was utilized (processing insts).
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system.cpu.stage3.idleCycles 446207500 # Number of cycles 0 instructions are processed.
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system.cpu.stage3.runCycles 111827334 # Number of cycles 1+ instructions are processed.
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system.cpu.stage3.utilization 20.039490 # Percentage of cycles stage was utilized (processing insts).
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system.cpu.stage4.idleCycles 210384695 # Number of cycles 0 instructions are processed.
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system.cpu.stage4.runCycles 347650139 # Number of cycles 1+ instructions are processed.
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system.cpu.stage4.utilization 62.299003 # Percentage of cycles stage was utilized (processing insts).
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system.cpu.icache.replacements 30 # number of replacements
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system.cpu.icache.tagsinuse 726.393228 # Cycle average of tags in use
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system.cpu.icache.total_refs 29077078 # Total number of references to valid blocks.
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system.cpu.icache.sampled_refs 852 # Sample count of references to valid blocks.
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system.cpu.icache.avg_refs 34128.025822 # Average number of references to valid blocks.
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system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu.icache.occ_blocks::0 726.393228 # Average occupied blocks per context
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system.cpu.icache.occ_percent::0 0.354684 # Average percentage of cache occupancy
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system.cpu.icache.ReadReq_hits 29077078 # number of ReadReq hits
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system.cpu.icache.demand_hits 29077078 # number of demand (read+write) hits
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system.cpu.icache.overall_hits 29077078 # number of overall hits
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system.cpu.icache.ReadReq_misses 1015 # number of ReadReq misses
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system.cpu.icache.demand_misses 1015 # number of demand (read+write) misses
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system.cpu.icache.overall_misses 1015 # number of overall misses
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system.cpu.icache.ReadReq_miss_latency 56421500 # number of ReadReq miss cycles
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system.cpu.icache.demand_miss_latency 56421500 # number of demand (read+write) miss cycles
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system.cpu.icache.overall_miss_latency 56421500 # number of overall miss cycles
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system.cpu.icache.ReadReq_accesses 29078093 # number of ReadReq accesses(hits+misses)
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system.cpu.icache.demand_accesses 29078093 # number of demand (read+write) accesses
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system.cpu.icache.overall_accesses 29078093 # number of overall (read+write) accesses
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system.cpu.icache.ReadReq_miss_rate 0.000035 # miss rate for ReadReq accesses
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system.cpu.icache.demand_miss_rate 0.000035 # miss rate for demand accesses
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system.cpu.icache.overall_miss_rate 0.000035 # miss rate for overall accesses
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system.cpu.icache.ReadReq_avg_miss_latency 55587.684729 # average ReadReq miss latency
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system.cpu.icache.demand_avg_miss_latency 55587.684729 # average overall miss latency
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system.cpu.icache.overall_avg_miss_latency 55587.684729 # average overall miss latency
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system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
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system.cpu.icache.blocked_cycles::no_targets 43500 # number of cycles access was blocked
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system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
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system.cpu.icache.blocked::no_targets 2 # number of cycles access was blocked
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system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
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system.cpu.icache.avg_blocked_cycles::no_targets 21750 # average number of cycles each access was blocked
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system.cpu.icache.fast_writes 0 # number of fast writes performed
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system.cpu.icache.cache_copies 0 # number of cache copies performed
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system.cpu.icache.writebacks 0 # number of writebacks
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system.cpu.icache.ReadReq_mshr_hits 163 # number of ReadReq MSHR hits
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system.cpu.icache.demand_mshr_hits 163 # number of demand (read+write) MSHR hits
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system.cpu.icache.overall_mshr_hits 163 # number of overall MSHR hits
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system.cpu.icache.ReadReq_mshr_misses 852 # number of ReadReq MSHR misses
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system.cpu.icache.demand_mshr_misses 852 # number of demand (read+write) MSHR misses
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system.cpu.icache.overall_mshr_misses 852 # number of overall MSHR misses
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system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
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system.cpu.icache.ReadReq_mshr_miss_latency 45615500 # number of ReadReq MSHR miss cycles
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system.cpu.icache.demand_mshr_miss_latency 45615500 # number of demand (read+write) MSHR miss cycles
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system.cpu.icache.overall_mshr_miss_latency 45615500 # number of overall MSHR miss cycles
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system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
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system.cpu.icache.ReadReq_mshr_miss_rate 0.000029 # mshr miss rate for ReadReq accesses
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system.cpu.icache.demand_mshr_miss_rate 0.000029 # mshr miss rate for demand accesses
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system.cpu.icache.overall_mshr_miss_rate 0.000029 # mshr miss rate for overall accesses
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system.cpu.icache.ReadReq_avg_mshr_miss_latency 53539.319249 # average ReadReq mshr miss latency
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system.cpu.icache.demand_avg_mshr_miss_latency 53539.319249 # average overall mshr miss latency
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system.cpu.icache.overall_avg_mshr_miss_latency 53539.319249 # average overall mshr miss latency
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system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
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system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
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system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
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system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.dcache.replacements 451299 # number of replacements
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system.cpu.dcache.tagsinuse 4094.156589 # Cycle average of tags in use
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system.cpu.dcache.total_refs 152394384 # Total number of references to valid blocks.
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system.cpu.dcache.sampled_refs 455395 # Sample count of references to valid blocks.
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system.cpu.dcache.avg_refs 334.642199 # Average number of references to valid blocks.
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system.cpu.dcache.warmup_cycle 267634000 # Cycle when the warmup percentage was hit.
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system.cpu.dcache.occ_blocks::0 4094.156589 # Average occupied blocks per context
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system.cpu.dcache.occ_percent::0 0.999550 # Average percentage of cache occupancy
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system.cpu.dcache.ReadReq_hits 114120508 # number of ReadReq hits
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system.cpu.dcache.WriteReq_hits 38273876 # number of WriteReq hits
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system.cpu.dcache.demand_hits 152394384 # number of demand (read+write) hits
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system.cpu.dcache.overall_hits 152394384 # number of overall hits
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system.cpu.dcache.ReadReq_misses 393534 # number of ReadReq misses
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system.cpu.dcache.WriteReq_misses 1177445 # number of WriteReq misses
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system.cpu.dcache.demand_misses 1570979 # number of demand (read+write) misses
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system.cpu.dcache.overall_misses 1570979 # number of overall misses
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system.cpu.dcache.ReadReq_miss_latency 8150455500 # number of ReadReq miss cycles
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system.cpu.dcache.WriteReq_miss_latency 25241828500 # number of WriteReq miss cycles
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system.cpu.dcache.demand_miss_latency 33392284000 # number of demand (read+write) miss cycles
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system.cpu.dcache.overall_miss_latency 33392284000 # number of overall miss cycles
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2011-02-23 22:35:25 +01:00
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system.cpu.dcache.ReadReq_accesses 114514042 # number of ReadReq accesses(hits+misses)
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system.cpu.dcache.WriteReq_accesses 39451321 # number of WriteReq accesses(hits+misses)
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system.cpu.dcache.demand_accesses 153965363 # number of demand (read+write) accesses
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system.cpu.dcache.overall_accesses 153965363 # number of overall (read+write) accesses
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2011-06-20 03:43:42 +02:00
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system.cpu.dcache.ReadReq_miss_rate 0.003437 # miss rate for ReadReq accesses
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system.cpu.dcache.WriteReq_miss_rate 0.029846 # miss rate for WriteReq accesses
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system.cpu.dcache.demand_miss_rate 0.010203 # miss rate for demand accesses
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system.cpu.dcache.overall_miss_rate 0.010203 # miss rate for overall accesses
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system.cpu.dcache.ReadReq_avg_miss_latency 20710.930949 # average ReadReq miss latency
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system.cpu.dcache.WriteReq_avg_miss_latency 21437.798369 # average WriteReq miss latency
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system.cpu.dcache.demand_avg_miss_latency 21255.716340 # average overall miss latency
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system.cpu.dcache.overall_avg_miss_latency 21255.716340 # average overall miss latency
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system.cpu.dcache.blocked_cycles::no_mshrs 12054000 # number of cycles access was blocked
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system.cpu.dcache.blocked_cycles::no_targets 3423892000 # number of cycles access was blocked
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system.cpu.dcache.blocked::no_mshrs 2783 # number of cycles access was blocked
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system.cpu.dcache.blocked::no_targets 216217 # number of cycles access was blocked
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|
|
system.cpu.dcache.avg_blocked_cycles::no_mshrs 4331.297161 # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.dcache.avg_blocked_cycles::no_targets 15835.443097 # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
|
|
|
|
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
|
|
|
|
system.cpu.dcache.writebacks 408187 # number of writebacks
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_hits 192302 # number of ReadReq MSHR hits
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_hits 923282 # number of WriteReq MSHR hits
|
|
|
|
|
system.cpu.dcache.demand_mshr_hits 1115584 # number of demand (read+write) MSHR hits
|
|
|
|
|
system.cpu.dcache.overall_mshr_hits 1115584 # number of overall MSHR hits
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_misses 201232 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_misses 254163 # number of WriteReq MSHR misses
|
|
|
|
|
system.cpu.dcache.demand_mshr_misses 455395 # number of demand (read+write) MSHR misses
|
2011-02-23 22:35:25 +01:00
|
|
|
system.cpu.dcache.overall_mshr_misses 455395 # number of overall MSHR misses
|
|
|
|
|
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
2011-06-20 03:43:42 +02:00
|
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency 3562178000 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency 5466807000 # number of WriteReq MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.demand_mshr_miss_latency 9028985000 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.overall_mshr_miss_latency 9028985000 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate 0.001757 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate 0.006442 # mshr miss rate for WriteReq accesses
|
|
|
|
|
system.cpu.dcache.demand_mshr_miss_rate 0.002958 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.dcache.overall_mshr_miss_rate 0.002958 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 17701.846625 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 21509.059147 # average WriteReq mshr miss latency
|
|
|
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency 19826.710877 # average overall mshr miss latency
|
|
|
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency 19826.710877 # average overall mshr miss latency
|
|
|
|
|
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
|
|
|
|
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
2011-02-23 22:35:25 +01:00
|
|
|
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
2011-06-20 03:43:42 +02:00
|
|
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
|
|
|
system.cpu.l2cache.replacements 73794 # number of replacements
|
|
|
|
|
system.cpu.l2cache.tagsinuse 17696.077368 # Cycle average of tags in use
|
|
|
|
|
system.cpu.l2cache.total_refs 445682 # Total number of references to valid blocks.
|
|
|
|
|
system.cpu.l2cache.sampled_refs 89681 # Sample count of references to valid blocks.
|
|
|
|
|
system.cpu.l2cache.avg_refs 4.969637 # Average number of references to valid blocks.
|
|
|
|
|
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
|
|
|
system.cpu.l2cache.occ_blocks::0 1642.043968 # Average occupied blocks per context
|
|
|
|
|
system.cpu.l2cache.occ_blocks::1 16054.033399 # Average occupied blocks per context
|
|
|
|
|
system.cpu.l2cache.occ_percent::0 0.050111 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.l2cache.occ_percent::1 0.489930 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.l2cache.ReadReq_hits 170050 # number of ReadReq hits
|
|
|
|
|
system.cpu.l2cache.Writeback_hits 408187 # number of Writeback hits
|
|
|
|
|
system.cpu.l2cache.ReadExReq_hits 194105 # number of ReadExReq hits
|
|
|
|
|
system.cpu.l2cache.demand_hits 364155 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.l2cache.overall_hits 364155 # number of overall hits
|
|
|
|
|
system.cpu.l2cache.ReadReq_misses 32017 # number of ReadReq misses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_misses 60075 # number of ReadExReq misses
|
|
|
|
|
system.cpu.l2cache.demand_misses 92092 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.l2cache.overall_misses 92092 # number of overall misses
|
|
|
|
|
system.cpu.l2cache.ReadReq_miss_latency 1674832000 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadExReq_miss_latency 3134450000 # number of ReadExReq miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_miss_latency 4809282000 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_miss_latency 4809282000 # number of overall miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadReq_accesses 202067 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.Writeback_accesses 408187 # number of Writeback accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.ReadExReq_accesses 254180 # number of ReadExReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.demand_accesses 456247 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.overall_accesses 456247 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_miss_rate 0.158447 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_miss_rate 0.236348 # miss rate for ReadExReq accesses
|
|
|
|
|
system.cpu.l2cache.demand_miss_rate 0.201847 # miss rate for demand accesses
|
|
|
|
|
system.cpu.l2cache.overall_miss_rate 0.201847 # miss rate for overall accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency 52310.709935 # average ReadReq miss latency
|
|
|
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency 52175.613816 # average ReadExReq miss latency
|
|
|
|
|
system.cpu.l2cache.demand_avg_miss_latency 52222.581766 # average overall miss latency
|
|
|
|
|
system.cpu.l2cache.overall_avg_miss_latency 52222.581766 # average overall miss latency
|
|
|
|
|
system.cpu.l2cache.blocked_cycles::no_mshrs 1314000 # number of cycles access was blocked
|
2011-02-23 22:35:25 +01:00
|
|
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
2011-06-20 03:43:42 +02:00
|
|
|
system.cpu.l2cache.blocked::no_mshrs 127 # number of cycles access was blocked
|
|
|
|
|
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.l2cache.avg_blocked_cycles::no_mshrs 10346.456693 # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
2011-02-23 22:35:25 +01:00
|
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
2011-06-20 03:43:42 +02:00
|
|
|
system.cpu.l2cache.writebacks 59344 # number of writebacks
|
2011-02-23 22:35:25 +01:00
|
|
|
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
|
|
|
|
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
2011-06-20 03:43:42 +02:00
|
|
|
system.cpu.l2cache.ReadReq_mshr_misses 32017 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_mshr_misses 60075 # number of ReadExReq MSHR misses
|
|
|
|
|
system.cpu.l2cache.demand_mshr_misses 92092 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.l2cache.overall_mshr_misses 92092 # number of overall MSHR misses
|
2011-02-23 22:35:25 +01:00
|
|
|
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
2011-06-20 03:43:42 +02:00
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency 1280946000 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency 2406895000 # number of ReadExReq MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_mshr_miss_latency 3687841000 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_mshr_miss_latency 3687841000 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.158447 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.236348 # mshr miss rate for ReadExReq accesses
|
|
|
|
|
system.cpu.l2cache.demand_mshr_miss_rate 0.201847 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.l2cache.overall_mshr_miss_rate 0.201847 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40008.308086 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40064.835622 # average ReadExReq mshr miss latency
|
|
|
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency 40045.183078 # average overall mshr miss latency
|
|
|
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency 40045.183078 # average overall mshr miss latency
|
|
|
|
|
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
|
|
|
|
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
2011-02-23 22:35:25 +01:00
|
|
|
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
2011-06-20 03:43:42 +02:00
|
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
2011-02-23 22:35:25 +01:00
|
|
|
|
|
|
|
|
---------- End Simulation Statistics ----------
|
