2006-03-29 02:36:34 +02:00
|
|
|
/*
|
|
|
|
* Copyright (c) 2003-2005 The Regents of The University of Michigan
|
|
|
|
* All rights reserved.
|
|
|
|
*
|
|
|
|
* Redistribution and use in source and binary forms, with or without
|
|
|
|
* modification, are permitted provided that the following conditions are
|
|
|
|
* met: redistributions of source code must retain the above copyright
|
|
|
|
* notice, this list of conditions and the following disclaimer;
|
|
|
|
* redistributions in binary form must reproduce the above copyright
|
|
|
|
* notice, this list of conditions and the following disclaimer in the
|
|
|
|
* documentation and/or other materials provided with the distribution;
|
|
|
|
* neither the name of the copyright holders nor the names of its
|
|
|
|
* contributors may be used to endorse or promote products derived from
|
|
|
|
* this software without specific prior written permission.
|
|
|
|
*
|
|
|
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
|
|
|
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
|
|
|
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
|
|
|
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
|
|
|
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
|
|
|
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
|
|
|
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
|
|
|
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
|
|
|
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
|
|
|
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
|
|
|
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
2006-06-01 01:26:56 +02:00
|
|
|
*
|
|
|
|
* Authors: Gabe Black
|
2006-03-29 02:36:34 +02:00
|
|
|
*/
|
|
|
|
|
|
|
|
#ifndef __ARCH_SPARC_UTILITY_HH__
|
|
|
|
#define __ARCH_SPARC_UTILITY_HH__
|
|
|
|
|
|
|
|
#include "arch/sparc/isa_traits.hh"
|
|
|
|
#include "base/misc.hh"
|
2006-10-16 21:52:14 +02:00
|
|
|
#include "base/bitfield.hh"
|
2006-10-12 23:38:06 +02:00
|
|
|
#include "cpu/thread_context.hh"
|
2006-03-29 02:36:34 +02:00
|
|
|
|
|
|
|
namespace SparcISA
|
|
|
|
{
|
|
|
|
inline ExtMachInst
|
2006-10-12 23:38:06 +02:00
|
|
|
makeExtMI(MachInst inst, ThreadContext * xc) {
|
|
|
|
ExtMachInst emi = (unsigned MachInst) inst;
|
|
|
|
//The I bit, bit 13, is used to figure out where the ASI
|
|
|
|
//should come from. Use that in the ExtMachInst. This is
|
|
|
|
//slightly redundant, but it removes the need to put a condition
|
|
|
|
//into all the execute functions
|
|
|
|
if(inst & (1 << 13))
|
|
|
|
emi |= (static_cast<ExtMachInst>(xc->readMiscReg(MISCREG_ASI))
|
|
|
|
<< (sizeof(MachInst) * 8));
|
2006-10-16 21:52:14 +02:00
|
|
|
else
|
|
|
|
emi |= (static_cast<ExtMachInst>(bits(inst, 12, 5))
|
|
|
|
<< (sizeof(MachInst) * 8));
|
2006-10-12 23:38:06 +02:00
|
|
|
return emi;
|
2006-03-29 02:36:34 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
inline bool isCallerSaveIntegerRegister(unsigned int reg) {
|
|
|
|
panic("register classification not implemented");
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
|
|
|
inline bool isCalleeSaveIntegerRegister(unsigned int reg) {
|
|
|
|
panic("register classification not implemented");
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
|
|
|
inline bool isCallerSaveFloatRegister(unsigned int reg) {
|
|
|
|
panic("register classification not implemented");
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
|
|
|
inline bool isCalleeSaveFloatRegister(unsigned int reg) {
|
|
|
|
panic("register classification not implemented");
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
|
|
|
// Instruction address compression hooks
|
|
|
|
inline Addr realPCToFetchPC(const Addr &addr)
|
|
|
|
{
|
|
|
|
return addr;
|
|
|
|
}
|
|
|
|
|
|
|
|
inline Addr fetchPCToRealPC(const Addr &addr)
|
|
|
|
{
|
|
|
|
return addr;
|
|
|
|
}
|
|
|
|
|
|
|
|
// the size of "fetched" instructions (not necessarily the size
|
|
|
|
// of real instructions for PISA)
|
|
|
|
inline size_t fetchInstSize()
|
|
|
|
{
|
|
|
|
return sizeof(MachInst);
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* Function to insure ISA semantics about 0 registers.
|
2006-06-06 23:32:21 +02:00
|
|
|
* @param tc The thread context.
|
2006-03-29 02:36:34 +02:00
|
|
|
*/
|
2006-06-06 23:32:21 +02:00
|
|
|
template <class TC>
|
|
|
|
void zeroRegisters(TC *tc);
|
2006-03-29 02:36:34 +02:00
|
|
|
|
|
|
|
} // namespace SparcISA
|
|
|
|
|
|
|
|
#endif
|