242 lines
8.4 KiB
C++
242 lines
8.4 KiB
C++
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/*
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* Copyright (c) 2010 ARM Limited
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* All rights reserved
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Copyright (c) 2005 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Ali Saidi
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*/
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/** @file
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* Implementiation of a PL390 GIC
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*/
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#ifndef __DEV_ARM_GIC_H__
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#define __DEV_ARM_GIC_H__
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#include "base/bitunion.hh"
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#include "base/range.hh"
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#include "dev/io_device.hh"
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#include "params/Gic.hh"
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/** @todo this code only assumes one processor for now. Low word
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* of intEnabled and pendingInt need to be replicated per CPU.
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* bottom 31 interrupts (7 words) need to be replicated for
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* for interrupt priority register, processor target registers
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* interrupt config registers */
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class Gic : public PioDevice
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{
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protected:
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// distributor memory addresses
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static const int ICDDCR = 0x000; // control register
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static const int ICDICTR = 0x004; // controller type
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static const int ICDIIDR = 0x008; // implementer id
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static const int ICDISER_ST = 0x100; // interrupt set enable
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static const int ICDISER_ED = 0x17c;
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static const int ICDICER_ST = 0x180; // interrupt clear enable
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static const int ICDICER_ED = 0x1fc;
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static const int ICDISPR_ST = 0x200; // set pending interrupt
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static const int ICDISPR_ED = 0x27c;
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static const int ICDICPR_ST = 0x280; // clear pending interrupt
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static const int ICDICPR_ED = 0x2fc;
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static const int ICDABR_ST = 0x300; // active bit registers
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static const int ICDABR_ED = 0x37c;
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static const int ICDIPR_ST = 0x400; // interrupt priority registers
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static const int ICDIPR_ED = 0x7f8;
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static const int ICDIPTR_ST = 0x800; // processor target registers
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static const int ICDIPTR_ED = 0xbf8;
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static const int ICDICFR_ST = 0xc00; // interrupt config registers
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static const int ICDICFR_ED = 0xcfc;
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static const int ICDSGIR = 0xf00; // software generated interrupt
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static const int DIST_SIZE = 0xfff;
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// cpu memory addressesa
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static const int ICCICR = 0x00; // CPU control register
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static const int ICCPMR = 0x04; // Interrupt priority mask
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static const int ICCBPR = 0x08; // binary point register
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static const int ICCIAR = 0x0C; // interrupt ack register
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static const int ICCEOIR = 0x10; // end of interrupt
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static const int ICCRPR = 0x14; // runing priority
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static const int ICCHPIR = 0x18; // highest pending interrupt
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static const int ICCABPR = 0x1c; // aliased binary point
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static const int ICCIIDR = 0xfc; // cpu interface id register
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static const int CPU_SIZE = 0xff;
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static const int SPURIOUS_INT = 1023;
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BitUnion32(SWI)
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Bitfield<3,0> sgi_id;
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Bitfield<23,16> cpu_list;
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Bitfield<25,24> list_type;
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EndBitUnion(SWI)
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/** Distributor address GIC listens at */
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Addr distAddr;
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/** CPU address GIC listens at */
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/** @todo is this one per cpu? */
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Addr cpuAddr;
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/** Latency for a distributor operation */
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Tick distPioDelay;
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/** Latency for a cpu operation */
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Tick cpuPioDelay;
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/** Gic enabled */
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bool enabled;
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/** Number of itLines enabled */
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uint32_t itLines;
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uint32_t itLinesLog2;
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/** interrupt enable bits for all possible 1020 interupts.
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* one bit per interrupt, 32 bit per word = 32 words */
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uint32_t intEnabled[32];
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/** interrupt pending bits for all possible 1020 interupts.
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* one bit per interrupt, 32 bit per word = 32 words */
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uint32_t pendingInt[32];
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/** interrupt active bits for all possible 1020 interupts.
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* one bit per interrupt, 32 bit per word = 32 words */
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uint32_t activeInt[32];
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/** an 8 bit priority (lower is higher priority) for each
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* of the 1020 possible supported interrupts.
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*/
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uint8_t intPriority[1020];
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/** an 8 bit cpu target id for each shared peripheral interrupt
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* of the 1020 possible supported interrupts.
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*/
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uint8_t cpuTarget[1020];
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/** 2 bit per interrupt signaling if it's level or edge sensitive
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* and if it is 1:N or N:N */
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uint32_t intConfig[64];
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/** CPU enabled */
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bool cpuEnabled[8];
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/** CPU priority */
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uint8_t cpuPriority[8];
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/** Binary point registers */
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uint8_t cpuBpr[8];
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/** highest interrupt that is interrupting CPU */
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uint32_t cpuHighestInt[8];
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/** software generated interrupt
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* @param data data to decode that indicates which cpus to interrupt
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*/
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void softInt(SWI swi);
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/** See if some processor interrupt flags need to be enabled/disabled
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* @param hint which set of interrupts needs to be checked
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*/
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void updateIntState(int hint);
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int intNumToWord(int num) const { return num >> 5; }
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int intNumToBit(int num) const { return num % 32; }
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public:
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typedef GicParams Params;
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const Params *
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params() const
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{
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return dynamic_cast<const Params *>(_params);
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}
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Gic(const Params *p);
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/** Return the address ranges used by the Gic
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* This is the distributor address + all cpu addresses
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*/
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virtual void addressRanges(AddrRangeList &range_list);
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/** A PIO read to the device, immediately split up into
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* readDistributor() or readCpu()
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*/
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virtual Tick read(PacketPtr pkt);
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/** A PIO read to the device, immediately split up into
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* writeDistributor() or writeCpu()
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*/
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virtual Tick write(PacketPtr pkt);
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/** Handle a read to the distributor poriton of the GIC
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* @param pkt packet to respond to
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*/
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Tick readDistributor(PacketPtr pkt);
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/** Handle a read to the cpu poriton of the GIC
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* @param pkt packet to respond to
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*/
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Tick readCpu(PacketPtr pkt);
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/** Handle a write to the distributor poriton of the GIC
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* @param pkt packet to respond to
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*/
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Tick writeDistributor(PacketPtr pkt);
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/** Handle a write to the cpu poriton of the GIC
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* @param pkt packet to respond to
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*/
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Tick writeCpu(PacketPtr pkt);
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/** Post an interrupt from a device that is connected to the Gic.
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* Depending on the configuration, the gic will pass this interrupt
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* on through to a CPU.
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* @param number number of interrupt to send */
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void sendInt(uint32_t number);
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/** Clear an interrupt from a device that is connected to the Gic
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* Depending on the configuration, the gic may de-assert it's cpu line
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* @param number number of interrupt to send */
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void clearInt(uint32_t number);
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virtual void serialize(std::ostream &os);
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virtual void unserialize(Checkpoint *cp, const std::string §ion);
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};
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#endif //__DEV_ARM_GIC_H__
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