2016-01-19 20:28:22 +01:00
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/*
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* Copyright (c) 2011-2015 Advanced Micro Devices, Inc.
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* All rights reserved.
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*
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* For use for simulation and test purposes only
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* 3. Neither the name of the copyright holder nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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* Author: Brad Beckmann, Marc Orr
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*/
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#include "gpu-compute/dispatcher.hh"
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#include "cpu/base.hh"
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#include "debug/GPUDisp.hh"
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#include "gpu-compute/cl_driver.hh"
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#include "gpu-compute/cl_event.hh"
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#include "gpu-compute/shader.hh"
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#include "gpu-compute/wavefront.hh"
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#include "mem/packet_access.hh"
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GpuDispatcher *GpuDispatcher::instance = nullptr;
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GpuDispatcher::GpuDispatcher(const Params *p)
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: DmaDevice(p), _masterId(p->system->getMasterId(name() + ".disp")),
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pioAddr(p->pio_addr), pioSize(4096), pioDelay(p->pio_latency),
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dispatchCount(0), dispatchActive(false), cpu(p->cpu),
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shader(p->shader_pointer), driver(p->cl_driver), tickEvent(this)
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{
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shader->handshake(this);
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driver->handshake(this);
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ndRange.wg_disp_rem = false;
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ndRange.globalWgId = 0;
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schedule(&tickEvent, 0);
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// translation port for the dispatcher
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tlbPort = new TLBPort(csprintf("%s-port%d", name()), this);
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num_kernelLaunched
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.name(name() + ".num_kernel_launched")
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.desc("number of kernel launched")
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;
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}
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GpuDispatcher *GpuDispatcherParams::create()
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{
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GpuDispatcher *dispatcher = new GpuDispatcher(this);
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GpuDispatcher::setInstance(dispatcher);
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return GpuDispatcher::getInstance();
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}
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void
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GpuDispatcher::serialize(CheckpointOut &cp) const
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{
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Tick event_tick = 0;
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if (ndRange.wg_disp_rem)
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fatal("Checkpointing not supported during active workgroup execution");
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if (tickEvent.scheduled())
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event_tick = tickEvent.when();
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SERIALIZE_SCALAR(event_tick);
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}
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void
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GpuDispatcher::unserialize(CheckpointIn &cp)
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{
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Tick event_tick;
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if (tickEvent.scheduled())
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deschedule(&tickEvent);
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UNSERIALIZE_SCALAR(event_tick);
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if (event_tick)
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schedule(&tickEvent, event_tick);
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}
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AddrRangeList
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GpuDispatcher::getAddrRanges() const
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{
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AddrRangeList ranges;
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DPRINTF(GPUDisp, "dispatcher registering addr range at %#x size %#x\n",
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pioAddr, pioSize);
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ranges.push_back(RangeSize(pioAddr, pioSize));
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return ranges;
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}
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Tick
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GpuDispatcher::read(PacketPtr pkt)
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{
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assert(pkt->getAddr() >= pioAddr);
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assert(pkt->getAddr() < pioAddr + pioSize);
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int offset = pkt->getAddr() - pioAddr;
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pkt->allocate();
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DPRINTF(GPUDisp, " read register %#x size=%d\n", offset, pkt->getSize());
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if (offset < 8) {
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assert(!offset);
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assert(pkt->getSize() == 8);
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uint64_t retval = dispatchActive;
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pkt->set(retval);
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} else {
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offset -= 8;
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assert(offset + pkt->getSize() < sizeof(HsaQueueEntry));
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char *curTaskPtr = (char*)&curTask;
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memcpy(pkt->getPtr<const void*>(), curTaskPtr + offset, pkt->getSize());
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}
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pkt->makeAtomicResponse();
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return pioDelay;
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}
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Tick
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GpuDispatcher::write(PacketPtr pkt)
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{
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assert(pkt->getAddr() >= pioAddr);
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assert(pkt->getAddr() < pioAddr + pioSize);
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int offset = pkt->getAddr() - pioAddr;
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#if TRACING_ON
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uint64_t data_val = 0;
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switch (pkt->getSize()) {
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case 1:
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data_val = pkt->get<uint8_t>();
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break;
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case 2:
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data_val = pkt->get<uint16_t>();
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break;
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case 4:
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data_val = pkt->get<uint32_t>();
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break;
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case 8:
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data_val = pkt->get<uint64_t>();
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break;
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default:
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DPRINTF(GPUDisp, "bad size %d\n", pkt->getSize());
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}
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DPRINTF(GPUDisp, "write register %#x value %#x size=%d\n", offset, data_val,
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pkt->getSize());
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#endif
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if (!offset) {
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static int nextId = 0;
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// The depends field of the qstruct, which was previously unused, is
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// used to communicate with simulated application.
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if (curTask.depends) {
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HostState hs;
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shader->ReadMem((uint64_t)(curTask.depends), &hs,
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sizeof(HostState), 0);
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// update event start time (in nano-seconds)
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uint64_t start = curTick() / 1000;
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shader->WriteMem((uint64_t)(&((_cl_event*)hs.event)->start),
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&start, sizeof(uint64_t), 0);
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}
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// launch kernel
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++num_kernelLaunched;
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NDRange *ndr = &(ndRangeMap[nextId]);
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// copy dispatch info
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ndr->q = curTask;
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// update the numDispTask polled by the runtime
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accessUserVar(cpu, (uint64_t)(curTask.numDispLeft), 0, 1);
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ndr->numWgTotal = 1;
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for (int i = 0; i < 3; ++i) {
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ndr->wgId[i] = 0;
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ndr->numWg[i] = divCeil(curTask.gdSize[i], curTask.wgSize[i]);
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ndr->numWgTotal *= ndr->numWg[i];
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}
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ndr->numWgCompleted = 0;
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ndr->globalWgId = 0;
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ndr->wg_disp_rem = true;
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ndr->execDone = false;
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ndr->addrToNotify = (volatile bool*)curTask.addrToNotify;
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ndr->numDispLeft = (volatile uint32_t*)curTask.numDispLeft;
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ndr->dispatchId = nextId;
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2016-04-07 16:30:20 +02:00
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ndr->curCid = pkt->req->contextId();
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2016-01-19 20:28:22 +01:00
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DPRINTF(GPUDisp, "launching kernel %d\n",nextId);
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execIds.push(nextId);
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++nextId;
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dispatchActive = true;
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if (!tickEvent.scheduled()) {
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schedule(&tickEvent, curTick() + shader->ticks(1));
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}
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} else {
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// populate current task struct
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// first 64 bits are launch reg
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offset -= 8;
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assert(offset < sizeof(HsaQueueEntry));
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char *curTaskPtr = (char*)&curTask;
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memcpy(curTaskPtr + offset, pkt->getPtr<const void*>(), pkt->getSize());
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}
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pkt->makeAtomicResponse();
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return pioDelay;
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}
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BaseMasterPort&
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GpuDispatcher::getMasterPort(const std::string &if_name, PortID idx)
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{
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if (if_name == "translation_port") {
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return *tlbPort;
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}
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return DmaDevice::getMasterPort(if_name, idx);
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}
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void
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GpuDispatcher::exec()
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{
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int fail_count = 0;
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// There are potentially multiple outstanding kernel launches.
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// It is possible that the workgroups in a different kernel
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// can fit on the GPU even if another kernel's workgroups cannot
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DPRINTF(GPUDisp, "Launching %d Kernels\n", execIds.size());
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while (execIds.size() > fail_count) {
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int execId = execIds.front();
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while (ndRangeMap[execId].wg_disp_rem) {
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//update the thread context
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2016-04-07 16:30:20 +02:00
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shader->updateContext(ndRangeMap[execId].curCid);
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2016-01-19 20:28:22 +01:00
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// attempt to dispatch_workgroup
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if (!shader->dispatch_workgroups(&ndRangeMap[execId])) {
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// if we failed try the next kernel,
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// it may have smaller workgroups.
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// put it on the queue to rety latter
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DPRINTF(GPUDisp, "kernel %d failed to launch\n", execId);
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execIds.push(execId);
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++fail_count;
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break;
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}
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}
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// let's try the next kernel_id
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execIds.pop();
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}
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DPRINTF(GPUDisp, "Returning %d Kernels\n", doneIds.size());
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if (doneIds.size() && cpu) {
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shader->hostWakeUp(cpu);
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}
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while (doneIds.size()) {
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// wakeup the CPU if any Kernels completed this cycle
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DPRINTF(GPUDisp, "WorkGroup %d completed\n", doneIds.front());
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doneIds.pop();
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}
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}
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void
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GpuDispatcher::notifyWgCompl(Wavefront *w)
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{
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2016-09-16 18:26:52 +02:00
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int kern_id = w->kernId;
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2016-01-19 20:28:22 +01:00
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DPRINTF(GPUDisp, "notify WgCompl %d\n",kern_id);
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assert(ndRangeMap[kern_id].dispatchId == kern_id);
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ndRangeMap[kern_id].numWgCompleted++;
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if (ndRangeMap[kern_id].numWgCompleted == ndRangeMap[kern_id].numWgTotal) {
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ndRangeMap[kern_id].execDone = true;
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doneIds.push(kern_id);
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if (ndRangeMap[kern_id].addrToNotify) {
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accessUserVar(cpu, (uint64_t)(ndRangeMap[kern_id].addrToNotify), 1,
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0);
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}
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accessUserVar(cpu, (uint64_t)(ndRangeMap[kern_id].numDispLeft), 0, -1);
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// update event end time (in nano-seconds)
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if (ndRangeMap[kern_id].q.depends) {
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HostState *host_state = (HostState*)ndRangeMap[kern_id].q.depends;
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uint64_t event;
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shader->ReadMem((uint64_t)(&host_state->event), &event,
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sizeof(uint64_t), 0);
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uint64_t end = curTick() / 1000;
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shader->WriteMem((uint64_t)(&((_cl_event*)event)->end), &end,
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sizeof(uint64_t), 0);
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}
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}
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if (!tickEvent.scheduled()) {
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schedule(&tickEvent, curTick() + shader->ticks(1));
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}
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}
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void
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GpuDispatcher::scheduleDispatch()
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{
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if (!tickEvent.scheduled())
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schedule(&tickEvent, curTick() + shader->ticks(1));
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}
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void
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GpuDispatcher::accessUserVar(BaseCPU *cpu, uint64_t addr, int val, int off)
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{
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if (cpu) {
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if (off) {
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shader->AccessMem(addr, &val, sizeof(int), 0, MemCmd::ReadReq,
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true);
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val += off;
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}
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shader->AccessMem(addr, &val, sizeof(int), 0, MemCmd::WriteReq, true);
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} else {
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panic("Cannot find host");
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}
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}
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GpuDispatcher::TickEvent::TickEvent(GpuDispatcher *_dispatcher)
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: Event(CPU_Tick_Pri), dispatcher(_dispatcher)
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{
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}
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void
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GpuDispatcher::TickEvent::process()
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{
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dispatcher->exec();
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}
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const char*
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GpuDispatcher::TickEvent::description() const
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{
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return "GPU Dispatcher tick";
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}
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// helper functions for driver to retrieve GPU attributes
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|
|
int
|
|
|
|
GpuDispatcher::getNumCUs()
|
|
|
|
{
|
|
|
|
return shader->cuList.size();
|
|
|
|
}
|
|
|
|
|
2016-06-09 17:24:55 +02:00
|
|
|
int
|
|
|
|
GpuDispatcher::wfSize() const
|
|
|
|
{
|
|
|
|
return shader->cuList[0]->wfSize();
|
|
|
|
}
|
|
|
|
|
2016-01-19 20:28:22 +01:00
|
|
|
void
|
|
|
|
GpuDispatcher::setFuncargsSize(int funcargs_size)
|
|
|
|
{
|
|
|
|
shader->funcargs_size = funcargs_size;
|
|
|
|
}
|
2016-09-16 18:27:56 +02:00
|
|
|
|
|
|
|
uint32_t
|
2016-09-16 20:47:19 +02:00
|
|
|
GpuDispatcher::getStaticContextSize() const
|
2016-09-16 18:27:56 +02:00
|
|
|
{
|
|
|
|
return shader->cuList[0]->wfList[0][0]->getStaticContextSize();
|
|
|
|
}
|