85 lines
2.9 KiB
C++
85 lines
2.9 KiB
C++
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/*
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* Copyright (c) 2008 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Gabe Black
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*/
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#ifndef __ARCH_X86_INTMESSAGE_HH__
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#define __ARCH_X86_INTMESSAGE_HH__
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#include "arch/x86/x86_traits.hh"
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#include "base/bitunion.hh"
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#include "mem/packet.hh"
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#include "mem/request.hh"
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#include "sim/host.hh"
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namespace X86ISA
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{
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BitUnion32(TriggerIntMessage)
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Bitfield<7, 0> destination;
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Bitfield<15, 8> vector;
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Bitfield<18, 16> deliveryMode;
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Bitfield<19> destMode;
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EndBitUnion(TriggerIntMessage)
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static const Addr TriggerIntOffset = 0;
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static inline PacketPtr
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prepIntRequest(const uint8_t id, Addr offset, Addr size)
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{
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RequestPtr req = new Request(x86InterruptAddress(id, offset),
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size, UNCACHEABLE);
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PacketPtr pkt = new Packet(req, MemCmd::MessageReq, Packet::Broadcast);
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pkt->allocate();
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return pkt;
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}
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template<class T>
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PacketPtr
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buildIntRequest(const uint8_t id, T payload, Addr offset, Addr size)
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{
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PacketPtr pkt = prepIntRequest(id, offset, size);
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pkt->set<T>(payload);
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return pkt;
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}
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static inline PacketPtr
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buildIntRequest(const uint8_t id, TriggerIntMessage payload)
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{
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return buildIntRequest(id, payload, TriggerIntOffset,
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sizeof(TriggerIntMessage));
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}
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static inline PacketPtr
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buildIntResponse()
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{
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panic("buildIntResponse not implemented.\n");
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}
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}
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#endif
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