92 lines
3 KiB
C++
92 lines
3 KiB
C++
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/*
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* Copyright (c) 2008 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Gabe Black
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*/
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#ifndef __ARCH_X86_APICREGS_HH__
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#define __ARCH_X86_APICREGS_HH__
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namespace X86ISA
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{
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enum ApicRegIndex
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{
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APIC_ID,
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APIC_VERSION,
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APIC_TASK_PRIORITY,
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APIC_ARBITRATION_PRIORITY,
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APIC_PROCESSOR_PRIORITY,
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APIC_EOI,
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APIC_LOGICAL_DESTINATION,
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APIC_DESTINATION_FORMAT,
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APIC_SPURIOUS_INTERRUPT_VECTOR,
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APIC_IN_SERVICE_BASE,
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APIC_TRIGGER_MODE_BASE = APIC_IN_SERVICE_BASE + 16,
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APIC_INTERRUPT_REQUEST_BASE = APIC_TRIGGER_MODE_BASE + 16,
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APIC_ERROR_STATUS = APIC_INTERRUPT_REQUEST_BASE + 16,
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APIC_INTERRUPT_COMMAND_LOW,
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APIC_INTERRUPT_COMMAND_HIGH,
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APIC_LVT_TIMER,
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APIC_LVT_THERMAL_SENSOR,
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APIC_LVT_PERFORMANCE_MONITORING_COUNTERS,
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APIC_LVT_LINT0,
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APIC_LVT_LINT1,
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APIC_LVT_ERROR,
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APIC_INITIAL_COUNT,
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APIC_CURRENT_COUNT,
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APIC_DIVIDE_CONFIGURATION,
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APIC_INTERNAL_STATE,
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NUM_APIC_REGS
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};
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static inline ApicRegIndex
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APIC_IN_SERVICE(int index)
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{
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return (ApicRegIndex)(APIC_IN_SERVICE_BASE + index);
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}
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static inline ApicRegIndex
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APIC_TRIGGER_MODE(int index)
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{
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return (ApicRegIndex)(APIC_TRIGGER_MODE_BASE + index);
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}
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static inline ApicRegIndex
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APIC_INTERRUPT_REQUEST(int index)
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{
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return (ApicRegIndex)(APIC_INTERRUPT_REQUEST_BASE + index);
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}
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}
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#endif
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