2014-10-30 05:50:15 +01:00
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[root]
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type=Root
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children=system
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eventq_index=0
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full_system=true
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sim_quantum=0
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time_sync_enable=false
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time_sync_period=100000000000
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time_sync_spin_threshold=100000000
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[system]
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type=LinuxArmSystem
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children=bridge cf0 clk_domain cpu0 cpu1 cpu_clk_domain dvfs_handler intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver voltage_domain
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atags_addr=134217728
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2015-01-04 20:02:12 +01:00
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boot_loader=/scratch/nilay/GEM5/system/binaries/boot_emm.arm64
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2014-10-30 05:50:15 +01:00
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boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1
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boot_release_addr=65528
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cache_line_size=64
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clk_domain=system.clk_domain
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2015-01-04 20:02:12 +01:00
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dtb_filename=/scratch/nilay/GEM5/system/binaries/vexpress.aarch64.20140821.dtb
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2014-10-30 05:50:15 +01:00
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early_kernel_symbols=false
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enable_context_switch_stats_dump=false
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eventq_index=0
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flags_addr=469827632
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gic_cpu_addr=738205696
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have_generic_timer=false
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have_large_asid_64=false
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have_lpae=false
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have_security=false
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have_virtualization=false
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highest_el_is_64=false
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init_param=0
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2015-01-04 20:02:12 +01:00
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kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.aarch64.20140821
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2014-10-30 05:50:15 +01:00
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kernel_addr_check=true
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load_addr_mask=268435455
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load_offset=2147483648
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machine_type=VExpress_EMM64
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mem_mode=atomic
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mem_ranges=2147483648:2415919103
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memories=system.physmem system.realview.nvmem system.realview.vram
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2015-03-09 15:39:09 +01:00
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mmap_using_noreserve=false
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2014-10-30 05:50:15 +01:00
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multi_proc=true
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num_work_ids=16
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panic_on_oops=true
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panic_on_panic=true
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phys_addr_range_64=40
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2015-01-04 20:02:12 +01:00
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readfile=/scratch/nilay/GEM5/gem5/tests/halt.sh
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2014-10-30 05:50:15 +01:00
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reset_addr_64=0
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symbolfile=
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work_begin_ckpt_count=0
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work_begin_cpu_id_exit=-1
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work_begin_exit_count=0
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work_cpus_ckpt_count=0
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work_end_ckpt_count=0
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work_end_exit_count=0
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work_item_id=-1
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system_port=system.membus.slave[1]
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[system.bridge]
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type=Bridge
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clk_domain=system.clk_domain
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delay=50000
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eventq_index=0
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ranges=788529152:805306367 721420288:725614591 805306368:1073741823 1073741824:1610612735 402653184:469762047 469762048:536870911
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req_size=16
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resp_size=16
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master=system.iobus.slave[0]
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slave=system.membus.master[0]
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[system.cf0]
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type=IdeDisk
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children=image
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delay=1000000
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driveID=master
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eventq_index=0
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image=system.cf0.image
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[system.cf0.image]
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type=CowDiskImage
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children=child
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child=system.cf0.image.child
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eventq_index=0
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image_file=
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read_only=false
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table_size=65536
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[system.cf0.image.child]
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type=RawDiskImage
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eventq_index=0
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2015-01-04 20:02:12 +01:00
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image_file=/scratch/nilay/GEM5/system/disks/linaro-minimal-aarch64.img
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2014-10-30 05:50:15 +01:00
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read_only=true
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[system.clk_domain]
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type=SrcClockDomain
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clock=1000
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domain_id=-1
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eventq_index=0
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init_perf_level=0
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voltage_domain=system.voltage_domain
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[system.cpu0]
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type=AtomicSimpleCPU
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children=dcache dstage2_mmu dtb icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer
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branchPred=Null
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checker=Null
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clk_domain=system.cpu_clk_domain
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cpu_id=0
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do_checkpoint_insts=true
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do_quiesce=true
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do_statistics_insts=true
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dstage2_mmu=system.cpu0.dstage2_mmu
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dtb=system.cpu0.dtb
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eventq_index=0
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fastmem=false
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function_trace=false
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function_trace_start=0
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interrupts=system.cpu0.interrupts
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isa=system.cpu0.isa
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istage2_mmu=system.cpu0.istage2_mmu
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itb=system.cpu0.itb
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max_insts_all_threads=0
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max_insts_any_thread=0
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max_loads_all_threads=0
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max_loads_any_thread=0
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numThreads=1
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profile=0
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progress_interval=0
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simpoint_start_insts=
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simulate_data_stalls=false
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simulate_inst_stalls=false
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socket_id=0
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switched_out=false
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system=system
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tracer=system.cpu0.tracer
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width=1
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workload=
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dcache_port=system.cpu0.dcache.cpu_side
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icache_port=system.cpu0.icache.cpu_side
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[system.cpu0.dcache]
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type=BaseCache
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children=tags
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addr_ranges=0:18446744073709551615
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assoc=2
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clk_domain=system.cpu_clk_domain
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2015-01-04 20:02:12 +01:00
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demand_mshr_reserve=1
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2014-10-30 05:50:15 +01:00
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eventq_index=0
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forward_snoops=true
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hit_latency=2
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is_top_level=true
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max_miss_count=0
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mshrs=6
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prefetch_on_access=false
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prefetcher=Null
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response_latency=2
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sequential_access=false
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size=32768
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system=system
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tags=system.cpu0.dcache.tags
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tgts_per_mshr=8
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two_queue=false
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write_buffers=16
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cpu_side=system.cpu0.dcache_port
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mem_side=system.cpu0.toL2Bus.slave[1]
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[system.cpu0.dcache.tags]
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type=LRU
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assoc=2
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block_size=64
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clk_domain=system.cpu_clk_domain
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eventq_index=0
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hit_latency=2
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sequential_access=false
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size=32768
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[system.cpu0.dstage2_mmu]
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type=ArmStage2MMU
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children=stage2_tlb
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eventq_index=0
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stage2_tlb=system.cpu0.dstage2_mmu.stage2_tlb
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2015-03-09 15:39:09 +01:00
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sys=system
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2014-10-30 05:50:15 +01:00
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tlb=system.cpu0.dtb
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[system.cpu0.dstage2_mmu.stage2_tlb]
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type=ArmTLB
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children=walker
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eventq_index=0
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is_stage2=true
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size=32
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walker=system.cpu0.dstage2_mmu.stage2_tlb.walker
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[system.cpu0.dstage2_mmu.stage2_tlb.walker]
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type=ArmTableWalker
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clk_domain=system.cpu_clk_domain
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eventq_index=0
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is_stage2=true
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num_squash_per_cycle=2
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sys=system
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[system.cpu0.dtb]
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type=ArmTLB
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children=walker
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eventq_index=0
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is_stage2=false
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size=64
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walker=system.cpu0.dtb.walker
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[system.cpu0.dtb.walker]
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type=ArmTableWalker
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clk_domain=system.cpu_clk_domain
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eventq_index=0
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is_stage2=false
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num_squash_per_cycle=2
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sys=system
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port=system.cpu0.toL2Bus.slave[3]
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[system.cpu0.icache]
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type=BaseCache
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children=tags
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addr_ranges=0:18446744073709551615
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assoc=2
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clk_domain=system.cpu_clk_domain
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2015-01-04 20:02:12 +01:00
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demand_mshr_reserve=1
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2014-10-30 05:50:15 +01:00
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eventq_index=0
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forward_snoops=true
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hit_latency=1
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is_top_level=true
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max_miss_count=0
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mshrs=2
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prefetch_on_access=false
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prefetcher=Null
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response_latency=1
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sequential_access=false
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size=32768
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system=system
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tags=system.cpu0.icache.tags
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tgts_per_mshr=8
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two_queue=false
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write_buffers=8
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cpu_side=system.cpu0.icache_port
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mem_side=system.cpu0.toL2Bus.slave[0]
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[system.cpu0.icache.tags]
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type=LRU
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assoc=2
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block_size=64
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clk_domain=system.cpu_clk_domain
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eventq_index=0
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hit_latency=1
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sequential_access=false
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size=32768
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[system.cpu0.interrupts]
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type=ArmInterrupts
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eventq_index=0
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[system.cpu0.isa]
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type=ArmISA
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eventq_index=0
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fpsid=1090793632
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id_aa64afr0_el1=0
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id_aa64afr1_el1=0
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id_aa64dfr0_el1=1052678
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id_aa64dfr1_el1=0
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id_aa64isar0_el1=0
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id_aa64isar1_el1=0
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id_aa64mmfr0_el1=15728642
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id_aa64mmfr1_el1=0
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id_aa64pfr0_el1=17
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id_aa64pfr1_el1=0
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id_isar0=34607377
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id_isar1=34677009
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id_isar2=555950401
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id_isar3=17899825
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id_isar4=268501314
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id_isar5=0
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id_mmfr0=270536963
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id_mmfr1=0
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id_mmfr2=19070976
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id_mmfr3=34611729
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id_pfr0=49
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id_pfr1=4113
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midr=1091551472
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pmu=Null
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system=system
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[system.cpu0.istage2_mmu]
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type=ArmStage2MMU
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children=stage2_tlb
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eventq_index=0
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stage2_tlb=system.cpu0.istage2_mmu.stage2_tlb
|
2015-03-09 15:39:09 +01:00
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sys=system
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2014-10-30 05:50:15 +01:00
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tlb=system.cpu0.itb
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[system.cpu0.istage2_mmu.stage2_tlb]
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type=ArmTLB
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children=walker
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eventq_index=0
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is_stage2=true
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size=32
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walker=system.cpu0.istage2_mmu.stage2_tlb.walker
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[system.cpu0.istage2_mmu.stage2_tlb.walker]
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type=ArmTableWalker
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clk_domain=system.cpu_clk_domain
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eventq_index=0
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is_stage2=true
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num_squash_per_cycle=2
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sys=system
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[system.cpu0.itb]
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type=ArmTLB
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children=walker
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eventq_index=0
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is_stage2=false
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size=64
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walker=system.cpu0.itb.walker
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|
|
|
|
[system.cpu0.itb.walker]
|
|
|
|
|
type=ArmTableWalker
|
|
|
|
|
clk_domain=system.cpu_clk_domain
|
|
|
|
|
eventq_index=0
|
|
|
|
|
is_stage2=false
|
|
|
|
|
num_squash_per_cycle=2
|
|
|
|
|
sys=system
|
|
|
|
|
port=system.cpu0.toL2Bus.slave[2]
|
|
|
|
|
|
|
|
|
|
[system.cpu0.l2cache]
|
|
|
|
|
type=BaseCache
|
|
|
|
|
children=prefetcher tags
|
|
|
|
|
addr_ranges=0:18446744073709551615
|
|
|
|
|
assoc=16
|
|
|
|
|
clk_domain=system.cpu_clk_domain
|
2015-01-04 20:02:12 +01:00
|
|
|
demand_mshr_reserve=1
|
2014-10-30 05:50:15 +01:00
|
|
|
eventq_index=0
|
|
|
|
|
forward_snoops=true
|
|
|
|
|
hit_latency=12
|
|
|
|
|
is_top_level=false
|
|
|
|
|
max_miss_count=0
|
|
|
|
|
mshrs=16
|
|
|
|
|
prefetch_on_access=true
|
|
|
|
|
prefetcher=system.cpu0.l2cache.prefetcher
|
|
|
|
|
response_latency=12
|
|
|
|
|
sequential_access=false
|
|
|
|
|
size=1048576
|
|
|
|
|
system=system
|
|
|
|
|
tags=system.cpu0.l2cache.tags
|
|
|
|
|
tgts_per_mshr=8
|
|
|
|
|
two_queue=false
|
|
|
|
|
write_buffers=8
|
|
|
|
|
cpu_side=system.cpu0.toL2Bus.master[0]
|
|
|
|
|
mem_side=system.toL2Bus.slave[0]
|
|
|
|
|
|
|
|
|
|
[system.cpu0.l2cache.prefetcher]
|
|
|
|
|
type=StridePrefetcher
|
2015-01-04 20:02:12 +01:00
|
|
|
cache_snoop=false
|
2014-10-30 05:50:15 +01:00
|
|
|
clk_domain=system.cpu_clk_domain
|
|
|
|
|
degree=8
|
|
|
|
|
eventq_index=0
|
|
|
|
|
latency=1
|
2015-01-04 20:02:12 +01:00
|
|
|
max_conf=7
|
|
|
|
|
min_conf=0
|
|
|
|
|
on_data=true
|
|
|
|
|
on_inst=true
|
|
|
|
|
on_miss=false
|
|
|
|
|
on_read=true
|
|
|
|
|
on_write=true
|
|
|
|
|
queue_filter=true
|
|
|
|
|
queue_size=32
|
|
|
|
|
queue_squash=true
|
|
|
|
|
start_conf=4
|
2014-10-30 05:50:15 +01:00
|
|
|
sys=system
|
2015-01-04 20:02:12 +01:00
|
|
|
table_assoc=4
|
|
|
|
|
table_sets=16
|
|
|
|
|
tag_prefetch=true
|
|
|
|
|
thresh_conf=4
|
2014-10-30 05:50:15 +01:00
|
|
|
use_master_id=true
|
|
|
|
|
|
|
|
|
|
[system.cpu0.l2cache.tags]
|
|
|
|
|
type=RandomRepl
|
|
|
|
|
assoc=16
|
|
|
|
|
block_size=64
|
|
|
|
|
clk_domain=system.cpu_clk_domain
|
|
|
|
|
eventq_index=0
|
|
|
|
|
hit_latency=12
|
|
|
|
|
sequential_access=false
|
|
|
|
|
size=1048576
|
|
|
|
|
|
|
|
|
|
[system.cpu0.toL2Bus]
|
|
|
|
|
type=CoherentXBar
|
|
|
|
|
clk_domain=system.cpu_clk_domain
|
|
|
|
|
eventq_index=0
|
2015-03-09 15:39:09 +01:00
|
|
|
forward_latency=0
|
|
|
|
|
frontend_latency=1
|
|
|
|
|
response_latency=1
|
2014-10-30 05:50:15 +01:00
|
|
|
snoop_filter=Null
|
2015-03-09 15:39:09 +01:00
|
|
|
snoop_response_latency=1
|
2014-10-30 05:50:15 +01:00
|
|
|
system=system
|
|
|
|
|
use_default_range=false
|
|
|
|
|
width=32
|
|
|
|
|
master=system.cpu0.l2cache.cpu_side
|
2015-03-09 15:39:09 +01:00
|
|
|
slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.walker.port system.cpu0.dtb.walker.port
|
2014-10-30 05:50:15 +01:00
|
|
|
|
|
|
|
|
[system.cpu0.tracer]
|
|
|
|
|
type=ExeTracer
|
|
|
|
|
eventq_index=0
|
|
|
|
|
|
|
|
|
|
[system.cpu1]
|
|
|
|
|
type=AtomicSimpleCPU
|
|
|
|
|
children=dcache dstage2_mmu dtb icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer
|
|
|
|
|
branchPred=Null
|
|
|
|
|
checker=Null
|
|
|
|
|
clk_domain=system.cpu_clk_domain
|
|
|
|
|
cpu_id=1
|
|
|
|
|
do_checkpoint_insts=true
|
|
|
|
|
do_quiesce=true
|
|
|
|
|
do_statistics_insts=true
|
|
|
|
|
dstage2_mmu=system.cpu1.dstage2_mmu
|
|
|
|
|
dtb=system.cpu1.dtb
|
|
|
|
|
eventq_index=0
|
|
|
|
|
fastmem=false
|
|
|
|
|
function_trace=false
|
|
|
|
|
function_trace_start=0
|
|
|
|
|
interrupts=system.cpu1.interrupts
|
|
|
|
|
isa=system.cpu1.isa
|
|
|
|
|
istage2_mmu=system.cpu1.istage2_mmu
|
|
|
|
|
itb=system.cpu1.itb
|
|
|
|
|
max_insts_all_threads=0
|
|
|
|
|
max_insts_any_thread=0
|
|
|
|
|
max_loads_all_threads=0
|
|
|
|
|
max_loads_any_thread=0
|
|
|
|
|
numThreads=1
|
|
|
|
|
profile=0
|
|
|
|
|
progress_interval=0
|
|
|
|
|
simpoint_start_insts=
|
|
|
|
|
simulate_data_stalls=false
|
|
|
|
|
simulate_inst_stalls=false
|
|
|
|
|
socket_id=0
|
|
|
|
|
switched_out=false
|
|
|
|
|
system=system
|
|
|
|
|
tracer=system.cpu1.tracer
|
|
|
|
|
width=1
|
|
|
|
|
workload=
|
|
|
|
|
dcache_port=system.cpu1.dcache.cpu_side
|
|
|
|
|
icache_port=system.cpu1.icache.cpu_side
|
|
|
|
|
|
|
|
|
|
[system.cpu1.dcache]
|
|
|
|
|
type=BaseCache
|
|
|
|
|
children=tags
|
|
|
|
|
addr_ranges=0:18446744073709551615
|
|
|
|
|
assoc=2
|
|
|
|
|
clk_domain=system.cpu_clk_domain
|
2015-01-04 20:02:12 +01:00
|
|
|
demand_mshr_reserve=1
|
2014-10-30 05:50:15 +01:00
|
|
|
eventq_index=0
|
|
|
|
|
forward_snoops=true
|
|
|
|
|
hit_latency=2
|
|
|
|
|
is_top_level=true
|
|
|
|
|
max_miss_count=0
|
|
|
|
|
mshrs=6
|
|
|
|
|
prefetch_on_access=false
|
|
|
|
|
prefetcher=Null
|
|
|
|
|
response_latency=2
|
|
|
|
|
sequential_access=false
|
|
|
|
|
size=32768
|
|
|
|
|
system=system
|
|
|
|
|
tags=system.cpu1.dcache.tags
|
|
|
|
|
tgts_per_mshr=8
|
|
|
|
|
two_queue=false
|
|
|
|
|
write_buffers=16
|
|
|
|
|
cpu_side=system.cpu1.dcache_port
|
|
|
|
|
mem_side=system.cpu1.toL2Bus.slave[1]
|
|
|
|
|
|
|
|
|
|
[system.cpu1.dcache.tags]
|
|
|
|
|
type=LRU
|
|
|
|
|
assoc=2
|
|
|
|
|
block_size=64
|
|
|
|
|
clk_domain=system.cpu_clk_domain
|
|
|
|
|
eventq_index=0
|
|
|
|
|
hit_latency=2
|
|
|
|
|
sequential_access=false
|
|
|
|
|
size=32768
|
|
|
|
|
|
|
|
|
|
[system.cpu1.dstage2_mmu]
|
|
|
|
|
type=ArmStage2MMU
|
|
|
|
|
children=stage2_tlb
|
|
|
|
|
eventq_index=0
|
|
|
|
|
stage2_tlb=system.cpu1.dstage2_mmu.stage2_tlb
|
2015-03-09 15:39:09 +01:00
|
|
|
sys=system
|
2014-10-30 05:50:15 +01:00
|
|
|
tlb=system.cpu1.dtb
|
|
|
|
|
|
|
|
|
|
[system.cpu1.dstage2_mmu.stage2_tlb]
|
|
|
|
|
type=ArmTLB
|
|
|
|
|
children=walker
|
|
|
|
|
eventq_index=0
|
|
|
|
|
is_stage2=true
|
|
|
|
|
size=32
|
|
|
|
|
walker=system.cpu1.dstage2_mmu.stage2_tlb.walker
|
|
|
|
|
|
|
|
|
|
[system.cpu1.dstage2_mmu.stage2_tlb.walker]
|
|
|
|
|
type=ArmTableWalker
|
|
|
|
|
clk_domain=system.cpu_clk_domain
|
|
|
|
|
eventq_index=0
|
|
|
|
|
is_stage2=true
|
|
|
|
|
num_squash_per_cycle=2
|
|
|
|
|
sys=system
|
|
|
|
|
|
|
|
|
|
[system.cpu1.dtb]
|
|
|
|
|
type=ArmTLB
|
|
|
|
|
children=walker
|
|
|
|
|
eventq_index=0
|
|
|
|
|
is_stage2=false
|
|
|
|
|
size=64
|
|
|
|
|
walker=system.cpu1.dtb.walker
|
|
|
|
|
|
|
|
|
|
[system.cpu1.dtb.walker]
|
|
|
|
|
type=ArmTableWalker
|
|
|
|
|
clk_domain=system.cpu_clk_domain
|
|
|
|
|
eventq_index=0
|
|
|
|
|
is_stage2=false
|
|
|
|
|
num_squash_per_cycle=2
|
|
|
|
|
sys=system
|
|
|
|
|
port=system.cpu1.toL2Bus.slave[3]
|
|
|
|
|
|
|
|
|
|
[system.cpu1.icache]
|
|
|
|
|
type=BaseCache
|
|
|
|
|
children=tags
|
|
|
|
|
addr_ranges=0:18446744073709551615
|
|
|
|
|
assoc=2
|
|
|
|
|
clk_domain=system.cpu_clk_domain
|
2015-01-04 20:02:12 +01:00
|
|
|
demand_mshr_reserve=1
|
2014-10-30 05:50:15 +01:00
|
|
|
eventq_index=0
|
|
|
|
|
forward_snoops=true
|
|
|
|
|
hit_latency=1
|
|
|
|
|
is_top_level=true
|
|
|
|
|
max_miss_count=0
|
|
|
|
|
mshrs=2
|
|
|
|
|
prefetch_on_access=false
|
|
|
|
|
prefetcher=Null
|
|
|
|
|
response_latency=1
|
|
|
|
|
sequential_access=false
|
|
|
|
|
size=32768
|
|
|
|
|
system=system
|
|
|
|
|
tags=system.cpu1.icache.tags
|
|
|
|
|
tgts_per_mshr=8
|
|
|
|
|
two_queue=false
|
|
|
|
|
write_buffers=8
|
|
|
|
|
cpu_side=system.cpu1.icache_port
|
|
|
|
|
mem_side=system.cpu1.toL2Bus.slave[0]
|
|
|
|
|
|
|
|
|
|
[system.cpu1.icache.tags]
|
|
|
|
|
type=LRU
|
|
|
|
|
assoc=2
|
|
|
|
|
block_size=64
|
|
|
|
|
clk_domain=system.cpu_clk_domain
|
|
|
|
|
eventq_index=0
|
|
|
|
|
hit_latency=1
|
|
|
|
|
sequential_access=false
|
|
|
|
|
size=32768
|
|
|
|
|
|
|
|
|
|
[system.cpu1.interrupts]
|
|
|
|
|
type=ArmInterrupts
|
|
|
|
|
eventq_index=0
|
|
|
|
|
|
|
|
|
|
[system.cpu1.isa]
|
|
|
|
|
type=ArmISA
|
|
|
|
|
eventq_index=0
|
|
|
|
|
fpsid=1090793632
|
|
|
|
|
id_aa64afr0_el1=0
|
|
|
|
|
id_aa64afr1_el1=0
|
|
|
|
|
id_aa64dfr0_el1=1052678
|
|
|
|
|
id_aa64dfr1_el1=0
|
|
|
|
|
id_aa64isar0_el1=0
|
|
|
|
|
id_aa64isar1_el1=0
|
|
|
|
|
id_aa64mmfr0_el1=15728642
|
|
|
|
|
id_aa64mmfr1_el1=0
|
|
|
|
|
id_aa64pfr0_el1=17
|
|
|
|
|
id_aa64pfr1_el1=0
|
|
|
|
|
id_isar0=34607377
|
|
|
|
|
id_isar1=34677009
|
|
|
|
|
id_isar2=555950401
|
|
|
|
|
id_isar3=17899825
|
|
|
|
|
id_isar4=268501314
|
|
|
|
|
id_isar5=0
|
|
|
|
|
id_mmfr0=270536963
|
|
|
|
|
id_mmfr1=0
|
|
|
|
|
id_mmfr2=19070976
|
|
|
|
|
id_mmfr3=34611729
|
|
|
|
|
id_pfr0=49
|
|
|
|
|
id_pfr1=4113
|
|
|
|
|
midr=1091551472
|
|
|
|
|
pmu=Null
|
|
|
|
|
system=system
|
|
|
|
|
|
|
|
|
|
[system.cpu1.istage2_mmu]
|
|
|
|
|
type=ArmStage2MMU
|
|
|
|
|
children=stage2_tlb
|
|
|
|
|
eventq_index=0
|
|
|
|
|
stage2_tlb=system.cpu1.istage2_mmu.stage2_tlb
|
2015-03-09 15:39:09 +01:00
|
|
|
sys=system
|
2014-10-30 05:50:15 +01:00
|
|
|
tlb=system.cpu1.itb
|
|
|
|
|
|
|
|
|
|
[system.cpu1.istage2_mmu.stage2_tlb]
|
|
|
|
|
type=ArmTLB
|
|
|
|
|
children=walker
|
|
|
|
|
eventq_index=0
|
|
|
|
|
is_stage2=true
|
|
|
|
|
size=32
|
|
|
|
|
walker=system.cpu1.istage2_mmu.stage2_tlb.walker
|
|
|
|
|
|
|
|
|
|
[system.cpu1.istage2_mmu.stage2_tlb.walker]
|
|
|
|
|
type=ArmTableWalker
|
|
|
|
|
clk_domain=system.cpu_clk_domain
|
|
|
|
|
eventq_index=0
|
|
|
|
|
is_stage2=true
|
|
|
|
|
num_squash_per_cycle=2
|
|
|
|
|
sys=system
|
|
|
|
|
|
|
|
|
|
[system.cpu1.itb]
|
|
|
|
|
type=ArmTLB
|
|
|
|
|
children=walker
|
|
|
|
|
eventq_index=0
|
|
|
|
|
is_stage2=false
|
|
|
|
|
size=64
|
|
|
|
|
walker=system.cpu1.itb.walker
|
|
|
|
|
|
|
|
|
|
[system.cpu1.itb.walker]
|
|
|
|
|
type=ArmTableWalker
|
|
|
|
|
clk_domain=system.cpu_clk_domain
|
|
|
|
|
eventq_index=0
|
|
|
|
|
is_stage2=false
|
|
|
|
|
num_squash_per_cycle=2
|
|
|
|
|
sys=system
|
|
|
|
|
port=system.cpu1.toL2Bus.slave[2]
|
|
|
|
|
|
|
|
|
|
[system.cpu1.l2cache]
|
|
|
|
|
type=BaseCache
|
|
|
|
|
children=prefetcher tags
|
|
|
|
|
addr_ranges=0:18446744073709551615
|
|
|
|
|
assoc=16
|
|
|
|
|
clk_domain=system.cpu_clk_domain
|
2015-01-04 20:02:12 +01:00
|
|
|
demand_mshr_reserve=1
|
2014-10-30 05:50:15 +01:00
|
|
|
eventq_index=0
|
|
|
|
|
forward_snoops=true
|
|
|
|
|
hit_latency=12
|
|
|
|
|
is_top_level=false
|
|
|
|
|
max_miss_count=0
|
|
|
|
|
mshrs=16
|
|
|
|
|
prefetch_on_access=true
|
|
|
|
|
prefetcher=system.cpu1.l2cache.prefetcher
|
|
|
|
|
response_latency=12
|
|
|
|
|
sequential_access=false
|
|
|
|
|
size=1048576
|
|
|
|
|
system=system
|
|
|
|
|
tags=system.cpu1.l2cache.tags
|
|
|
|
|
tgts_per_mshr=8
|
|
|
|
|
two_queue=false
|
|
|
|
|
write_buffers=8
|
|
|
|
|
cpu_side=system.cpu1.toL2Bus.master[0]
|
|
|
|
|
mem_side=system.toL2Bus.slave[1]
|
|
|
|
|
|
|
|
|
|
[system.cpu1.l2cache.prefetcher]
|
|
|
|
|
type=StridePrefetcher
|
2015-01-04 20:02:12 +01:00
|
|
|
cache_snoop=false
|
2014-10-30 05:50:15 +01:00
|
|
|
clk_domain=system.cpu_clk_domain
|
|
|
|
|
degree=8
|
|
|
|
|
eventq_index=0
|
|
|
|
|
latency=1
|
2015-01-04 20:02:12 +01:00
|
|
|
max_conf=7
|
|
|
|
|
min_conf=0
|
|
|
|
|
on_data=true
|
|
|
|
|
on_inst=true
|
|
|
|
|
on_miss=false
|
|
|
|
|
on_read=true
|
|
|
|
|
on_write=true
|
|
|
|
|
queue_filter=true
|
|
|
|
|
queue_size=32
|
|
|
|
|
queue_squash=true
|
|
|
|
|
start_conf=4
|
2014-10-30 05:50:15 +01:00
|
|
|
sys=system
|
2015-01-04 20:02:12 +01:00
|
|
|
table_assoc=4
|
|
|
|
|
table_sets=16
|
|
|
|
|
tag_prefetch=true
|
|
|
|
|
thresh_conf=4
|
2014-10-30 05:50:15 +01:00
|
|
|
use_master_id=true
|
|
|
|
|
|
|
|
|
|
[system.cpu1.l2cache.tags]
|
|
|
|
|
type=RandomRepl
|
|
|
|
|
assoc=16
|
|
|
|
|
block_size=64
|
|
|
|
|
clk_domain=system.cpu_clk_domain
|
|
|
|
|
eventq_index=0
|
|
|
|
|
hit_latency=12
|
|
|
|
|
sequential_access=false
|
|
|
|
|
size=1048576
|
|
|
|
|
|
|
|
|
|
[system.cpu1.toL2Bus]
|
|
|
|
|
type=CoherentXBar
|
|
|
|
|
clk_domain=system.cpu_clk_domain
|
|
|
|
|
eventq_index=0
|
2015-03-09 15:39:09 +01:00
|
|
|
forward_latency=0
|
|
|
|
|
frontend_latency=1
|
|
|
|
|
response_latency=1
|
2014-10-30 05:50:15 +01:00
|
|
|
snoop_filter=Null
|
2015-03-09 15:39:09 +01:00
|
|
|
snoop_response_latency=1
|
2014-10-30 05:50:15 +01:00
|
|
|
system=system
|
|
|
|
|
use_default_range=false
|
|
|
|
|
width=32
|
|
|
|
|
master=system.cpu1.l2cache.cpu_side
|
2015-03-09 15:39:09 +01:00
|
|
|
slave=system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu1.itb.walker.port system.cpu1.dtb.walker.port
|
2014-10-30 05:50:15 +01:00
|
|
|
|
|
|
|
|
[system.cpu1.tracer]
|
|
|
|
|
type=ExeTracer
|
|
|
|
|
eventq_index=0
|
|
|
|
|
|
|
|
|
|
[system.cpu_clk_domain]
|
|
|
|
|
type=SrcClockDomain
|
|
|
|
|
clock=500
|
|
|
|
|
domain_id=-1
|
|
|
|
|
eventq_index=0
|
|
|
|
|
init_perf_level=0
|
|
|
|
|
voltage_domain=system.voltage_domain
|
|
|
|
|
|
|
|
|
|
[system.dvfs_handler]
|
|
|
|
|
type=DVFSHandler
|
|
|
|
|
domains=
|
|
|
|
|
enable=false
|
|
|
|
|
eventq_index=0
|
|
|
|
|
sys_clk_domain=system.clk_domain
|
|
|
|
|
transition_latency=100000000
|
|
|
|
|
|
|
|
|
|
[system.intrctrl]
|
|
|
|
|
type=IntrControl
|
|
|
|
|
eventq_index=0
|
|
|
|
|
sys=system
|
|
|
|
|
|
|
|
|
|
[system.iobus]
|
|
|
|
|
type=NoncoherentXBar
|
|
|
|
|
clk_domain=system.clk_domain
|
|
|
|
|
eventq_index=0
|
2015-03-09 15:39:09 +01:00
|
|
|
forward_latency=1
|
|
|
|
|
frontend_latency=2
|
|
|
|
|
response_latency=2
|
2014-10-30 05:50:15 +01:00
|
|
|
use_default_range=true
|
2015-03-09 15:39:09 +01:00
|
|
|
width=16
|
2014-10-30 05:50:15 +01:00
|
|
|
default=system.realview.pciconfig.pio
|
|
|
|
|
master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ide.config system.realview.ethernet.pio system.realview.ethernet.config system.iocache.cpu_side
|
|
|
|
|
slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma
|
|
|
|
|
|
|
|
|
|
[system.iocache]
|
|
|
|
|
type=BaseCache
|
|
|
|
|
children=tags
|
|
|
|
|
addr_ranges=2147483648:2415919103
|
|
|
|
|
assoc=8
|
|
|
|
|
clk_domain=system.clk_domain
|
2015-01-04 20:02:12 +01:00
|
|
|
demand_mshr_reserve=1
|
2014-10-30 05:50:15 +01:00
|
|
|
eventq_index=0
|
|
|
|
|
forward_snoops=false
|
|
|
|
|
hit_latency=50
|
|
|
|
|
is_top_level=true
|
|
|
|
|
max_miss_count=0
|
|
|
|
|
mshrs=20
|
|
|
|
|
prefetch_on_access=false
|
|
|
|
|
prefetcher=Null
|
|
|
|
|
response_latency=50
|
|
|
|
|
sequential_access=false
|
|
|
|
|
size=1024
|
|
|
|
|
system=system
|
|
|
|
|
tags=system.iocache.tags
|
|
|
|
|
tgts_per_mshr=12
|
|
|
|
|
two_queue=false
|
|
|
|
|
write_buffers=8
|
|
|
|
|
cpu_side=system.iobus.master[27]
|
|
|
|
|
mem_side=system.membus.slave[3]
|
|
|
|
|
|
|
|
|
|
[system.iocache.tags]
|
|
|
|
|
type=LRU
|
|
|
|
|
assoc=8
|
|
|
|
|
block_size=64
|
|
|
|
|
clk_domain=system.clk_domain
|
|
|
|
|
eventq_index=0
|
|
|
|
|
hit_latency=50
|
|
|
|
|
sequential_access=false
|
|
|
|
|
size=1024
|
|
|
|
|
|
|
|
|
|
[system.l2c]
|
|
|
|
|
type=BaseCache
|
|
|
|
|
children=tags
|
|
|
|
|
addr_ranges=0:18446744073709551615
|
|
|
|
|
assoc=8
|
|
|
|
|
clk_domain=system.cpu_clk_domain
|
2015-01-04 20:02:12 +01:00
|
|
|
demand_mshr_reserve=1
|
2014-10-30 05:50:15 +01:00
|
|
|
eventq_index=0
|
|
|
|
|
forward_snoops=true
|
|
|
|
|
hit_latency=20
|
|
|
|
|
is_top_level=false
|
|
|
|
|
max_miss_count=0
|
|
|
|
|
mshrs=20
|
|
|
|
|
prefetch_on_access=false
|
|
|
|
|
prefetcher=Null
|
|
|
|
|
response_latency=20
|
|
|
|
|
sequential_access=false
|
|
|
|
|
size=4194304
|
|
|
|
|
system=system
|
|
|
|
|
tags=system.l2c.tags
|
|
|
|
|
tgts_per_mshr=12
|
|
|
|
|
two_queue=false
|
|
|
|
|
write_buffers=8
|
|
|
|
|
cpu_side=system.toL2Bus.master[0]
|
|
|
|
|
mem_side=system.membus.slave[2]
|
|
|
|
|
|
|
|
|
|
[system.l2c.tags]
|
|
|
|
|
type=LRU
|
|
|
|
|
assoc=8
|
|
|
|
|
block_size=64
|
|
|
|
|
clk_domain=system.cpu_clk_domain
|
|
|
|
|
eventq_index=0
|
|
|
|
|
hit_latency=20
|
|
|
|
|
sequential_access=false
|
|
|
|
|
size=4194304
|
|
|
|
|
|
|
|
|
|
[system.membus]
|
|
|
|
|
type=CoherentXBar
|
|
|
|
|
children=badaddr_responder
|
|
|
|
|
clk_domain=system.clk_domain
|
|
|
|
|
eventq_index=0
|
2015-03-09 15:39:09 +01:00
|
|
|
forward_latency=4
|
|
|
|
|
frontend_latency=3
|
|
|
|
|
response_latency=2
|
2014-10-30 05:50:15 +01:00
|
|
|
snoop_filter=Null
|
2015-03-09 15:39:09 +01:00
|
|
|
snoop_response_latency=4
|
2014-10-30 05:50:15 +01:00
|
|
|
system=system
|
|
|
|
|
use_default_range=false
|
2015-03-09 15:39:09 +01:00
|
|
|
width=16
|
2014-10-30 05:50:15 +01:00
|
|
|
default=system.membus.badaddr_responder.pio
|
|
|
|
|
master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.local_cpu_timer.pio system.realview.vgic.pio system.physmem.port
|
|
|
|
|
slave=system.realview.hdlcd.dma system.system_port system.l2c.mem_side system.iocache.mem_side
|
|
|
|
|
|
|
|
|
|
[system.membus.badaddr_responder]
|
|
|
|
|
type=IsaFake
|
|
|
|
|
clk_domain=system.clk_domain
|
|
|
|
|
eventq_index=0
|
|
|
|
|
fake_mem=false
|
|
|
|
|
pio_addr=0
|
|
|
|
|
pio_latency=100000
|
|
|
|
|
pio_size=8
|
|
|
|
|
ret_bad_addr=true
|
|
|
|
|
ret_data16=65535
|
|
|
|
|
ret_data32=4294967295
|
|
|
|
|
ret_data64=18446744073709551615
|
|
|
|
|
ret_data8=255
|
|
|
|
|
system=system
|
|
|
|
|
update_data=false
|
|
|
|
|
warn_access=warn
|
|
|
|
|
pio=system.membus.default
|
|
|
|
|
|
|
|
|
|
[system.physmem]
|
|
|
|
|
type=SimpleMemory
|
|
|
|
|
bandwidth=73.000000
|
|
|
|
|
clk_domain=system.clk_domain
|
|
|
|
|
conf_table_reported=true
|
|
|
|
|
eventq_index=0
|
|
|
|
|
in_addr_map=true
|
|
|
|
|
latency=30000
|
|
|
|
|
latency_var=0
|
|
|
|
|
null=false
|
|
|
|
|
range=2147483648:2415919103
|
|
|
|
|
port=system.membus.master[5]
|
|
|
|
|
|
|
|
|
|
[system.realview]
|
|
|
|
|
type=RealView
|
|
|
|
|
children=aaci_fake cf_ctrl clcd energy_ctrl ethernet generic_timer gic hdlcd ide kmi0 kmi1 l2x0_fake lan_fake local_cpu_timer mmc_fake nvmem pciconfig realview_io rtc sp810_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake usb_fake vgic vram watchdog_fake
|
|
|
|
|
eventq_index=0
|
|
|
|
|
intrctrl=system.intrctrl
|
|
|
|
|
pci_cfg_base=805306368
|
|
|
|
|
pci_cfg_gen_offsets=true
|
|
|
|
|
pci_io_base=788529152
|
|
|
|
|
system=system
|
|
|
|
|
|
|
|
|
|
[system.realview.aaci_fake]
|
|
|
|
|
type=AmbaFake
|
|
|
|
|
amba_id=0
|
|
|
|
|
clk_domain=system.clk_domain
|
|
|
|
|
eventq_index=0
|
|
|
|
|
ignore_access=false
|
|
|
|
|
pio_addr=470024192
|
|
|
|
|
pio_latency=100000
|
|
|
|
|
system=system
|
|
|
|
|
pio=system.iobus.master[18]
|
|
|
|
|
|
|
|
|
|
[system.realview.cf_ctrl]
|
|
|
|
|
type=IdeController
|
|
|
|
|
BAR0=471465984
|
|
|
|
|
BAR0LegacyIO=true
|
|
|
|
|
BAR0Size=256
|
|
|
|
|
BAR1=471466240
|
|
|
|
|
BAR1LegacyIO=true
|
|
|
|
|
BAR1Size=4096
|
|
|
|
|
BAR2=1
|
|
|
|
|
BAR2LegacyIO=false
|
|
|
|
|
BAR2Size=8
|
|
|
|
|
BAR3=1
|
|
|
|
|
BAR3LegacyIO=false
|
|
|
|
|
BAR3Size=4
|
|
|
|
|
BAR4=1
|
|
|
|
|
BAR4LegacyIO=false
|
|
|
|
|
BAR4Size=16
|
|
|
|
|
BAR5=1
|
|
|
|
|
BAR5LegacyIO=false
|
|
|
|
|
BAR5Size=0
|
|
|
|
|
BIST=0
|
|
|
|
|
CacheLineSize=0
|
|
|
|
|
CapabilityPtr=0
|
|
|
|
|
CardbusCIS=0
|
|
|
|
|
ClassCode=1
|
|
|
|
|
Command=1
|
|
|
|
|
DeviceID=28945
|
|
|
|
|
ExpansionROM=0
|
|
|
|
|
HeaderType=0
|
|
|
|
|
InterruptLine=31
|
|
|
|
|
InterruptPin=1
|
|
|
|
|
LatencyTimer=0
|
|
|
|
|
LegacyIOBase=0
|
|
|
|
|
MSICAPBaseOffset=0
|
|
|
|
|
MSICAPCapId=0
|
|
|
|
|
MSICAPMaskBits=0
|
|
|
|
|
MSICAPMsgAddr=0
|
|
|
|
|
MSICAPMsgCtrl=0
|
|
|
|
|
MSICAPMsgData=0
|
|
|
|
|
MSICAPMsgUpperAddr=0
|
|
|
|
|
MSICAPNextCapability=0
|
|
|
|
|
MSICAPPendingBits=0
|
|
|
|
|
MSIXCAPBaseOffset=0
|
|
|
|
|
MSIXCAPCapId=0
|
|
|
|
|
MSIXCAPNextCapability=0
|
|
|
|
|
MSIXMsgCtrl=0
|
|
|
|
|
MSIXPbaOffset=0
|
|
|
|
|
MSIXTableOffset=0
|
|
|
|
|
MaximumLatency=0
|
|
|
|
|
MinimumGrant=0
|
|
|
|
|
PMCAPBaseOffset=0
|
|
|
|
|
PMCAPCapId=0
|
|
|
|
|
PMCAPCapabilities=0
|
|
|
|
|
PMCAPCtrlStatus=0
|
|
|
|
|
PMCAPNextCapability=0
|
|
|
|
|
PXCAPBaseOffset=0
|
|
|
|
|
PXCAPCapId=0
|
|
|
|
|
PXCAPCapabilities=0
|
|
|
|
|
PXCAPDevCap2=0
|
|
|
|
|
PXCAPDevCapabilities=0
|
|
|
|
|
PXCAPDevCtrl=0
|
|
|
|
|
PXCAPDevCtrl2=0
|
|
|
|
|
PXCAPDevStatus=0
|
|
|
|
|
PXCAPLinkCap=0
|
|
|
|
|
PXCAPLinkCtrl=0
|
|
|
|
|
PXCAPLinkStatus=0
|
|
|
|
|
PXCAPNextCapability=0
|
|
|
|
|
ProgIF=133
|
|
|
|
|
Revision=0
|
|
|
|
|
Status=640
|
|
|
|
|
SubClassCode=1
|
|
|
|
|
SubsystemID=0
|
|
|
|
|
SubsystemVendorID=0
|
|
|
|
|
VendorID=32902
|
|
|
|
|
clk_domain=system.clk_domain
|
|
|
|
|
config_latency=20000
|
|
|
|
|
ctrl_offset=2
|
|
|
|
|
disks=
|
|
|
|
|
eventq_index=0
|
|
|
|
|
io_shift=2
|
|
|
|
|
pci_bus=2
|
|
|
|
|
pci_dev=0
|
|
|
|
|
pci_func=0
|
|
|
|
|
pio_latency=30000
|
|
|
|
|
platform=system.realview
|
|
|
|
|
system=system
|
|
|
|
|
config=system.iobus.master[9]
|
|
|
|
|
dma=system.iobus.slave[2]
|
|
|
|
|
pio=system.iobus.master[8]
|
|
|
|
|
|
|
|
|
|
[system.realview.clcd]
|
|
|
|
|
type=Pl111
|
|
|
|
|
amba_id=1315089
|
|
|
|
|
clk_domain=system.clk_domain
|
|
|
|
|
enable_capture=true
|
|
|
|
|
eventq_index=0
|
|
|
|
|
gic=system.realview.gic
|
|
|
|
|
int_num=46
|
|
|
|
|
pio_addr=471793664
|
|
|
|
|
pio_latency=10000
|
|
|
|
|
pixel_clock=41667
|
|
|
|
|
system=system
|
|
|
|
|
vnc=system.vncserver
|
|
|
|
|
dma=system.iobus.slave[1]
|
|
|
|
|
pio=system.iobus.master[4]
|
|
|
|
|
|
|
|
|
|
[system.realview.energy_ctrl]
|
|
|
|
|
type=EnergyCtrl
|
|
|
|
|
clk_domain=system.clk_domain
|
|
|
|
|
dvfs_handler=system.dvfs_handler
|
|
|
|
|
eventq_index=0
|
|
|
|
|
pio_addr=470286336
|
|
|
|
|
pio_latency=100000
|
|
|
|
|
system=system
|
|
|
|
|
pio=system.iobus.master[22]
|
|
|
|
|
|
|
|
|
|
[system.realview.ethernet]
|
|
|
|
|
type=IGbE
|
|
|
|
|
BAR0=0
|
|
|
|
|
BAR0LegacyIO=false
|
|
|
|
|
BAR0Size=131072
|
|
|
|
|
BAR1=0
|
|
|
|
|
BAR1LegacyIO=false
|
|
|
|
|
BAR1Size=0
|
|
|
|
|
BAR2=0
|
|
|
|
|
BAR2LegacyIO=false
|
|
|
|
|
BAR2Size=0
|
|
|
|
|
BAR3=0
|
|
|
|
|
BAR3LegacyIO=false
|
|
|
|
|
BAR3Size=0
|
|
|
|
|
BAR4=0
|
|
|
|
|
BAR4LegacyIO=false
|
|
|
|
|
BAR4Size=0
|
|
|
|
|
BAR5=0
|
|
|
|
|
BAR5LegacyIO=false
|
|
|
|
|
BAR5Size=0
|
|
|
|
|
BIST=0
|
|
|
|
|
CacheLineSize=0
|
|
|
|
|
CapabilityPtr=0
|
|
|
|
|
CardbusCIS=0
|
|
|
|
|
ClassCode=2
|
|
|
|
|
Command=0
|
|
|
|
|
DeviceID=4213
|
|
|
|
|
ExpansionROM=0
|
|
|
|
|
HeaderType=0
|
|
|
|
|
InterruptLine=1
|
|
|
|
|
InterruptPin=1
|
|
|
|
|
LatencyTimer=0
|
|
|
|
|
LegacyIOBase=0
|
|
|
|
|
MSICAPBaseOffset=0
|
|
|
|
|
MSICAPCapId=0
|
|
|
|
|
MSICAPMaskBits=0
|
|
|
|
|
MSICAPMsgAddr=0
|
|
|
|
|
MSICAPMsgCtrl=0
|
|
|
|
|
MSICAPMsgData=0
|
|
|
|
|
MSICAPMsgUpperAddr=0
|
|
|
|
|
MSICAPNextCapability=0
|
|
|
|
|
MSICAPPendingBits=0
|
|
|
|
|
MSIXCAPBaseOffset=0
|
|
|
|
|
MSIXCAPCapId=0
|
|
|
|
|
MSIXCAPNextCapability=0
|
|
|
|
|
MSIXMsgCtrl=0
|
|
|
|
|
MSIXPbaOffset=0
|
|
|
|
|
MSIXTableOffset=0
|
|
|
|
|
MaximumLatency=0
|
|
|
|
|
MinimumGrant=255
|
|
|
|
|
PMCAPBaseOffset=0
|
|
|
|
|
PMCAPCapId=0
|
|
|
|
|
PMCAPCapabilities=0
|
|
|
|
|
PMCAPCtrlStatus=0
|
|
|
|
|
PMCAPNextCapability=0
|
|
|
|
|
PXCAPBaseOffset=0
|
|
|
|
|
PXCAPCapId=0
|
|
|
|
|
PXCAPCapabilities=0
|
|
|
|
|
PXCAPDevCap2=0
|
|
|
|
|
PXCAPDevCapabilities=0
|
|
|
|
|
PXCAPDevCtrl=0
|
|
|
|
|
PXCAPDevCtrl2=0
|
|
|
|
|
PXCAPDevStatus=0
|
|
|
|
|
PXCAPLinkCap=0
|
|
|
|
|
PXCAPLinkCtrl=0
|
|
|
|
|
PXCAPLinkStatus=0
|
|
|
|
|
PXCAPNextCapability=0
|
|
|
|
|
ProgIF=0
|
|
|
|
|
Revision=0
|
|
|
|
|
Status=0
|
|
|
|
|
SubClassCode=0
|
|
|
|
|
SubsystemID=4104
|
|
|
|
|
SubsystemVendorID=32902
|
|
|
|
|
VendorID=32902
|
|
|
|
|
clk_domain=system.clk_domain
|
|
|
|
|
config_latency=20000
|
|
|
|
|
eventq_index=0
|
|
|
|
|
fetch_comp_delay=10000
|
|
|
|
|
fetch_delay=10000
|
|
|
|
|
hardware_address=00:90:00:00:00:01
|
|
|
|
|
pci_bus=0
|
|
|
|
|
pci_dev=0
|
|
|
|
|
pci_func=0
|
|
|
|
|
phy_epid=896
|
|
|
|
|
phy_pid=680
|
|
|
|
|
pio_latency=30000
|
|
|
|
|
platform=system.realview
|
|
|
|
|
rx_desc_cache_size=64
|
|
|
|
|
rx_fifo_size=393216
|
|
|
|
|
rx_write_delay=0
|
|
|
|
|
system=system
|
|
|
|
|
tx_desc_cache_size=64
|
|
|
|
|
tx_fifo_size=393216
|
|
|
|
|
tx_read_delay=0
|
|
|
|
|
wb_comp_delay=10000
|
|
|
|
|
wb_delay=10000
|
|
|
|
|
config=system.iobus.master[26]
|
|
|
|
|
dma=system.iobus.slave[4]
|
|
|
|
|
pio=system.iobus.master[25]
|
|
|
|
|
|
|
|
|
|
[system.realview.generic_timer]
|
|
|
|
|
type=GenericTimer
|
|
|
|
|
eventq_index=0
|
|
|
|
|
gic=system.realview.gic
|
|
|
|
|
int_num=29
|
|
|
|
|
system=system
|
|
|
|
|
|
|
|
|
|
[system.realview.gic]
|
|
|
|
|
type=Pl390
|
|
|
|
|
clk_domain=system.clk_domain
|
|
|
|
|
cpu_addr=738205696
|
|
|
|
|
cpu_pio_delay=10000
|
|
|
|
|
dist_addr=738201600
|
|
|
|
|
dist_pio_delay=10000
|
|
|
|
|
eventq_index=0
|
|
|
|
|
int_latency=10000
|
|
|
|
|
it_lines=128
|
|
|
|
|
msix_addr=0
|
|
|
|
|
platform=system.realview
|
|
|
|
|
system=system
|
|
|
|
|
pio=system.membus.master[2]
|
|
|
|
|
|
|
|
|
|
[system.realview.hdlcd]
|
|
|
|
|
type=HDLcd
|
|
|
|
|
amba_id=1314816
|
|
|
|
|
clk_domain=system.clk_domain
|
|
|
|
|
enable_capture=true
|
|
|
|
|
eventq_index=0
|
|
|
|
|
gic=system.realview.gic
|
|
|
|
|
int_num=117
|
|
|
|
|
pio_addr=721420288
|
|
|
|
|
pio_latency=10000
|
|
|
|
|
pixel_clock=7299
|
|
|
|
|
system=system
|
|
|
|
|
vnc=system.vncserver
|
|
|
|
|
dma=system.membus.slave[0]
|
|
|
|
|
pio=system.iobus.master[5]
|
|
|
|
|
|
|
|
|
|
[system.realview.ide]
|
|
|
|
|
type=IdeController
|
|
|
|
|
BAR0=1
|
|
|
|
|
BAR0LegacyIO=false
|
|
|
|
|
BAR0Size=8
|
|
|
|
|
BAR1=1
|
|
|
|
|
BAR1LegacyIO=false
|
|
|
|
|
BAR1Size=4
|
|
|
|
|
BAR2=1
|
|
|
|
|
BAR2LegacyIO=false
|
|
|
|
|
BAR2Size=8
|
|
|
|
|
BAR3=1
|
|
|
|
|
BAR3LegacyIO=false
|
|
|
|
|
BAR3Size=4
|
|
|
|
|
BAR4=1
|
|
|
|
|
BAR4LegacyIO=false
|
|
|
|
|
BAR4Size=16
|
|
|
|
|
BAR5=1
|
|
|
|
|
BAR5LegacyIO=false
|
|
|
|
|
BAR5Size=0
|
|
|
|
|
BIST=0
|
|
|
|
|
CacheLineSize=0
|
|
|
|
|
CapabilityPtr=0
|
|
|
|
|
CardbusCIS=0
|
|
|
|
|
ClassCode=1
|
|
|
|
|
Command=0
|
|
|
|
|
DeviceID=28945
|
|
|
|
|
ExpansionROM=0
|
|
|
|
|
HeaderType=0
|
|
|
|
|
InterruptLine=2
|
|
|
|
|
InterruptPin=2
|
|
|
|
|
LatencyTimer=0
|
|
|
|
|
LegacyIOBase=0
|
|
|
|
|
MSICAPBaseOffset=0
|
|
|
|
|
MSICAPCapId=0
|
|
|
|
|
MSICAPMaskBits=0
|
|
|
|
|
MSICAPMsgAddr=0
|
|
|
|
|
MSICAPMsgCtrl=0
|
|
|
|
|
MSICAPMsgData=0
|
|
|
|
|
MSICAPMsgUpperAddr=0
|
|
|
|
|
MSICAPNextCapability=0
|
|
|
|
|
MSICAPPendingBits=0
|
|
|
|
|
MSIXCAPBaseOffset=0
|
|
|
|
|
MSIXCAPCapId=0
|
|
|
|
|
MSIXCAPNextCapability=0
|
|
|
|
|
MSIXMsgCtrl=0
|
|
|
|
|
MSIXPbaOffset=0
|
|
|
|
|
MSIXTableOffset=0
|
|
|
|
|
MaximumLatency=0
|
|
|
|
|
MinimumGrant=0
|
|
|
|
|
PMCAPBaseOffset=0
|
|
|
|
|
PMCAPCapId=0
|
|
|
|
|
PMCAPCapabilities=0
|
|
|
|
|
PMCAPCtrlStatus=0
|
|
|
|
|
PMCAPNextCapability=0
|
|
|
|
|
PXCAPBaseOffset=0
|
|
|
|
|
PXCAPCapId=0
|
|
|
|
|
PXCAPCapabilities=0
|
|
|
|
|
PXCAPDevCap2=0
|
|
|
|
|
PXCAPDevCapabilities=0
|
|
|
|
|
PXCAPDevCtrl=0
|
|
|
|
|
PXCAPDevCtrl2=0
|
|
|
|
|
PXCAPDevStatus=0
|
|
|
|
|
PXCAPLinkCap=0
|
|
|
|
|
PXCAPLinkCtrl=0
|
|
|
|
|
PXCAPLinkStatus=0
|
|
|
|
|
PXCAPNextCapability=0
|
|
|
|
|
ProgIF=133
|
|
|
|
|
Revision=0
|
|
|
|
|
Status=640
|
|
|
|
|
SubClassCode=1
|
|
|
|
|
SubsystemID=0
|
|
|
|
|
SubsystemVendorID=0
|
|
|
|
|
VendorID=32902
|
|
|
|
|
clk_domain=system.clk_domain
|
|
|
|
|
config_latency=20000
|
|
|
|
|
ctrl_offset=0
|
|
|
|
|
disks=system.cf0
|
|
|
|
|
eventq_index=0
|
|
|
|
|
io_shift=0
|
|
|
|
|
pci_bus=0
|
|
|
|
|
pci_dev=1
|
|
|
|
|
pci_func=0
|
|
|
|
|
pio_latency=30000
|
|
|
|
|
platform=system.realview
|
|
|
|
|
system=system
|
|
|
|
|
config=system.iobus.master[24]
|
|
|
|
|
dma=system.iobus.slave[3]
|
|
|
|
|
pio=system.iobus.master[23]
|
|
|
|
|
|
|
|
|
|
[system.realview.kmi0]
|
|
|
|
|
type=Pl050
|
|
|
|
|
amba_id=1314896
|
|
|
|
|
clk_domain=system.clk_domain
|
|
|
|
|
eventq_index=0
|
|
|
|
|
gic=system.realview.gic
|
|
|
|
|
int_delay=1000000
|
|
|
|
|
int_num=44
|
|
|
|
|
is_mouse=false
|
|
|
|
|
pio_addr=470155264
|
|
|
|
|
pio_latency=100000
|
|
|
|
|
system=system
|
|
|
|
|
vnc=system.vncserver
|
|
|
|
|
pio=system.iobus.master[6]
|
|
|
|
|
|
|
|
|
|
[system.realview.kmi1]
|
|
|
|
|
type=Pl050
|
|
|
|
|
amba_id=1314896
|
|
|
|
|
clk_domain=system.clk_domain
|
|
|
|
|
eventq_index=0
|
|
|
|
|
gic=system.realview.gic
|
|
|
|
|
int_delay=1000000
|
|
|
|
|
int_num=45
|
|
|
|
|
is_mouse=true
|
|
|
|
|
pio_addr=470220800
|
|
|
|
|
pio_latency=100000
|
|
|
|
|
system=system
|
|
|
|
|
vnc=system.vncserver
|
|
|
|
|
pio=system.iobus.master[7]
|
|
|
|
|
|
|
|
|
|
[system.realview.l2x0_fake]
|
|
|
|
|
type=IsaFake
|
|
|
|
|
clk_domain=system.clk_domain
|
|
|
|
|
eventq_index=0
|
|
|
|
|
fake_mem=false
|
|
|
|
|
pio_addr=739246080
|
|
|
|
|
pio_latency=100000
|
|
|
|
|
pio_size=4095
|
|
|
|
|
ret_bad_addr=false
|
|
|
|
|
ret_data16=65535
|
|
|
|
|
ret_data32=4294967295
|
|
|
|
|
ret_data64=18446744073709551615
|
|
|
|
|
ret_data8=255
|
|
|
|
|
system=system
|
|
|
|
|
update_data=false
|
|
|
|
|
warn_access=
|
|
|
|
|
pio=system.iobus.master[12]
|
|
|
|
|
|
|
|
|
|
[system.realview.lan_fake]
|
|
|
|
|
type=IsaFake
|
|
|
|
|
clk_domain=system.clk_domain
|
|
|
|
|
eventq_index=0
|
|
|
|
|
fake_mem=false
|
|
|
|
|
pio_addr=436207616
|
|
|
|
|
pio_latency=100000
|
|
|
|
|
pio_size=65535
|
|
|
|
|
ret_bad_addr=false
|
|
|
|
|
ret_data16=65535
|
|
|
|
|
ret_data32=4294967295
|
|
|
|
|
ret_data64=18446744073709551615
|
|
|
|
|
ret_data8=255
|
|
|
|
|
system=system
|
|
|
|
|
update_data=false
|
|
|
|
|
warn_access=
|
|
|
|
|
pio=system.iobus.master[19]
|
|
|
|
|
|
|
|
|
|
[system.realview.local_cpu_timer]
|
|
|
|
|
type=CpuLocalTimer
|
|
|
|
|
clk_domain=system.clk_domain
|
|
|
|
|
eventq_index=0
|
|
|
|
|
gic=system.realview.gic
|
|
|
|
|
int_num_timer=29
|
|
|
|
|
int_num_watchdog=30
|
|
|
|
|
pio_addr=738721792
|
|
|
|
|
pio_latency=100000
|
|
|
|
|
system=system
|
|
|
|
|
pio=system.membus.master[3]
|
|
|
|
|
|
|
|
|
|
[system.realview.mmc_fake]
|
|
|
|
|
type=AmbaFake
|
|
|
|
|
amba_id=0
|
|
|
|
|
clk_domain=system.clk_domain
|
|
|
|
|
eventq_index=0
|
|
|
|
|
ignore_access=false
|
|
|
|
|
pio_addr=470089728
|
|
|
|
|
pio_latency=100000
|
|
|
|
|
system=system
|
|
|
|
|
pio=system.iobus.master[21]
|
|
|
|
|
|
|
|
|
|
[system.realview.nvmem]
|
|
|
|
|
type=SimpleMemory
|
|
|
|
|
bandwidth=73.000000
|
|
|
|
|
clk_domain=system.clk_domain
|
|
|
|
|
conf_table_reported=true
|
|
|
|
|
eventq_index=0
|
|
|
|
|
in_addr_map=true
|
|
|
|
|
latency=30000
|
|
|
|
|
latency_var=0
|
|
|
|
|
null=false
|
|
|
|
|
range=0:67108863
|
|
|
|
|
port=system.membus.master[1]
|
|
|
|
|
|
|
|
|
|
[system.realview.pciconfig]
|
|
|
|
|
type=PciConfigAll
|
|
|
|
|
bus=0
|
|
|
|
|
clk_domain=system.clk_domain
|
|
|
|
|
eventq_index=0
|
|
|
|
|
pio_addr=0
|
|
|
|
|
pio_latency=30000
|
|
|
|
|
platform=system.realview
|
|
|
|
|
size=268435456
|
|
|
|
|
system=system
|
|
|
|
|
pio=system.iobus.default
|
|
|
|
|
|
|
|
|
|
[system.realview.realview_io]
|
|
|
|
|
type=RealViewCtrl
|
|
|
|
|
clk_domain=system.clk_domain
|
|
|
|
|
eventq_index=0
|
|
|
|
|
idreg=35979264
|
|
|
|
|
pio_addr=469827584
|
|
|
|
|
pio_latency=100000
|
|
|
|
|
proc_id0=335544320
|
|
|
|
|
proc_id1=335544320
|
|
|
|
|
system=system
|
|
|
|
|
pio=system.iobus.master[1]
|
|
|
|
|
|
|
|
|
|
[system.realview.rtc]
|
|
|
|
|
type=PL031
|
|
|
|
|
amba_id=3412017
|
|
|
|
|
clk_domain=system.clk_domain
|
|
|
|
|
eventq_index=0
|
|
|
|
|
gic=system.realview.gic
|
|
|
|
|
int_delay=100000
|
|
|
|
|
int_num=36
|
|
|
|
|
pio_addr=471269376
|
|
|
|
|
pio_latency=100000
|
|
|
|
|
system=system
|
|
|
|
|
time=Thu Jan 1 00:00:00 2009
|
|
|
|
|
pio=system.iobus.master[10]
|
|
|
|
|
|
|
|
|
|
[system.realview.sp810_fake]
|
|
|
|
|
type=AmbaFake
|
|
|
|
|
amba_id=0
|
|
|
|
|
clk_domain=system.clk_domain
|
|
|
|
|
eventq_index=0
|
|
|
|
|
ignore_access=true
|
|
|
|
|
pio_addr=469893120
|
|
|
|
|
pio_latency=100000
|
|
|
|
|
system=system
|
|
|
|
|
pio=system.iobus.master[16]
|
|
|
|
|
|
|
|
|
|
[system.realview.timer0]
|
|
|
|
|
type=Sp804
|
|
|
|
|
amba_id=1316868
|
|
|
|
|
clk_domain=system.clk_domain
|
|
|
|
|
clock0=1000000
|
|
|
|
|
clock1=1000000
|
|
|
|
|
eventq_index=0
|
|
|
|
|
gic=system.realview.gic
|
|
|
|
|
int_num0=34
|
|
|
|
|
int_num1=34
|
|
|
|
|
pio_addr=470876160
|
|
|
|
|
pio_latency=100000
|
|
|
|
|
system=system
|
|
|
|
|
pio=system.iobus.master[2]
|
|
|
|
|
|
|
|
|
|
[system.realview.timer1]
|
|
|
|
|
type=Sp804
|
|
|
|
|
amba_id=1316868
|
|
|
|
|
clk_domain=system.clk_domain
|
|
|
|
|
clock0=1000000
|
|
|
|
|
clock1=1000000
|
|
|
|
|
eventq_index=0
|
|
|
|
|
gic=system.realview.gic
|
|
|
|
|
int_num0=35
|
|
|
|
|
int_num1=35
|
|
|
|
|
pio_addr=470941696
|
|
|
|
|
pio_latency=100000
|
|
|
|
|
system=system
|
|
|
|
|
pio=system.iobus.master[3]
|
|
|
|
|
|
|
|
|
|
[system.realview.uart]
|
|
|
|
|
type=Pl011
|
|
|
|
|
clk_domain=system.clk_domain
|
|
|
|
|
end_on_eot=false
|
|
|
|
|
eventq_index=0
|
|
|
|
|
gic=system.realview.gic
|
|
|
|
|
int_delay=100000
|
|
|
|
|
int_num=37
|
|
|
|
|
pio_addr=470351872
|
|
|
|
|
pio_latency=100000
|
|
|
|
|
platform=system.realview
|
|
|
|
|
system=system
|
|
|
|
|
terminal=system.terminal
|
|
|
|
|
pio=system.iobus.master[0]
|
|
|
|
|
|
|
|
|
|
[system.realview.uart1_fake]
|
|
|
|
|
type=AmbaFake
|
|
|
|
|
amba_id=0
|
|
|
|
|
clk_domain=system.clk_domain
|
|
|
|
|
eventq_index=0
|
|
|
|
|
ignore_access=false
|
|
|
|
|
pio_addr=470417408
|
|
|
|
|
pio_latency=100000
|
|
|
|
|
system=system
|
|
|
|
|
pio=system.iobus.master[13]
|
|
|
|
|
|
|
|
|
|
[system.realview.uart2_fake]
|
|
|
|
|
type=AmbaFake
|
|
|
|
|
amba_id=0
|
|
|
|
|
clk_domain=system.clk_domain
|
|
|
|
|
eventq_index=0
|
|
|
|
|
ignore_access=false
|
|
|
|
|
pio_addr=470482944
|
|
|
|
|
pio_latency=100000
|
|
|
|
|
system=system
|
|
|
|
|
pio=system.iobus.master[14]
|
|
|
|
|
|
|
|
|
|
[system.realview.uart3_fake]
|
|
|
|
|
type=AmbaFake
|
|
|
|
|
amba_id=0
|
|
|
|
|
clk_domain=system.clk_domain
|
|
|
|
|
eventq_index=0
|
|
|
|
|
ignore_access=false
|
|
|
|
|
pio_addr=470548480
|
|
|
|
|
pio_latency=100000
|
|
|
|
|
system=system
|
|
|
|
|
pio=system.iobus.master[15]
|
|
|
|
|
|
|
|
|
|
[system.realview.usb_fake]
|
|
|
|
|
type=IsaFake
|
|
|
|
|
clk_domain=system.clk_domain
|
|
|
|
|
eventq_index=0
|
|
|
|
|
fake_mem=false
|
|
|
|
|
pio_addr=452984832
|
|
|
|
|
pio_latency=100000
|
|
|
|
|
pio_size=131071
|
|
|
|
|
ret_bad_addr=false
|
|
|
|
|
ret_data16=65535
|
|
|
|
|
ret_data32=4294967295
|
|
|
|
|
ret_data64=18446744073709551615
|
|
|
|
|
ret_data8=255
|
|
|
|
|
system=system
|
|
|
|
|
update_data=false
|
|
|
|
|
warn_access=
|
|
|
|
|
pio=system.iobus.master[20]
|
|
|
|
|
|
|
|
|
|
[system.realview.vgic]
|
|
|
|
|
type=VGic
|
|
|
|
|
clk_domain=system.clk_domain
|
|
|
|
|
eventq_index=0
|
|
|
|
|
gic=system.realview.gic
|
|
|
|
|
hv_addr=738213888
|
|
|
|
|
pio_delay=10000
|
|
|
|
|
platform=system.realview
|
|
|
|
|
ppint=25
|
|
|
|
|
system=system
|
|
|
|
|
vcpu_addr=738222080
|
|
|
|
|
pio=system.membus.master[4]
|
|
|
|
|
|
|
|
|
|
[system.realview.vram]
|
|
|
|
|
type=SimpleMemory
|
|
|
|
|
bandwidth=73.000000
|
|
|
|
|
clk_domain=system.clk_domain
|
|
|
|
|
conf_table_reported=false
|
|
|
|
|
eventq_index=0
|
|
|
|
|
in_addr_map=true
|
|
|
|
|
latency=30000
|
|
|
|
|
latency_var=0
|
|
|
|
|
null=false
|
|
|
|
|
range=402653184:436207615
|
|
|
|
|
port=system.iobus.master[11]
|
|
|
|
|
|
|
|
|
|
[system.realview.watchdog_fake]
|
|
|
|
|
type=AmbaFake
|
|
|
|
|
amba_id=0
|
|
|
|
|
clk_domain=system.clk_domain
|
|
|
|
|
eventq_index=0
|
|
|
|
|
ignore_access=false
|
|
|
|
|
pio_addr=470745088
|
|
|
|
|
pio_latency=100000
|
|
|
|
|
system=system
|
|
|
|
|
pio=system.iobus.master[17]
|
|
|
|
|
|
|
|
|
|
[system.terminal]
|
|
|
|
|
type=Terminal
|
|
|
|
|
eventq_index=0
|
|
|
|
|
intr_control=system.intrctrl
|
|
|
|
|
number=0
|
|
|
|
|
output=true
|
|
|
|
|
port=3456
|
|
|
|
|
|
|
|
|
|
[system.toL2Bus]
|
|
|
|
|
type=CoherentXBar
|
|
|
|
|
clk_domain=system.cpu_clk_domain
|
|
|
|
|
eventq_index=0
|
2015-03-09 15:39:09 +01:00
|
|
|
forward_latency=0
|
|
|
|
|
frontend_latency=1
|
|
|
|
|
response_latency=1
|
2014-10-30 05:50:15 +01:00
|
|
|
snoop_filter=Null
|
2015-03-09 15:39:09 +01:00
|
|
|
snoop_response_latency=1
|
2014-10-30 05:50:15 +01:00
|
|
|
system=system
|
|
|
|
|
use_default_range=false
|
2015-03-09 15:39:09 +01:00
|
|
|
width=32
|
2014-10-30 05:50:15 +01:00
|
|
|
master=system.l2c.cpu_side
|
|
|
|
|
slave=system.cpu0.l2cache.mem_side system.cpu1.l2cache.mem_side
|
|
|
|
|
|
|
|
|
|
[system.vncserver]
|
|
|
|
|
type=VncServer
|
|
|
|
|
eventq_index=0
|
|
|
|
|
frame_capture=false
|
|
|
|
|
number=0
|
|
|
|
|
port=5900
|
|
|
|
|
|
|
|
|
|
[system.voltage_domain]
|
|
|
|
|
type=VoltageDomain
|
|
|
|
|
eventq_index=0
|
|
|
|
|
voltage=1.000000
|
|
|
|
|
|
