2014-09-20 23:17:51 +02:00
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/*
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* Copyright (c) 2014 ARM Limited
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* All rights reserved
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Andreas Sandberg
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*/
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#include "debug/VIOPci.hh"
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#include "dev/virtio/pci.hh"
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#include "mem/packet_access.hh"
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#include "params/PciVirtIO.hh"
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PciVirtIO::PciVirtIO(const Params *params)
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2014-11-24 15:03:38 +01:00
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: PciDevice(params), queueNotify(0), interruptDeliveryPending(false),
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vio(*params->vio), callbackKick(this)
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2014-09-20 23:17:51 +02:00
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{
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// Override the subsystem ID with the device ID from VirtIO
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config.subsystemID = htole(vio.deviceId);
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BARSize[0] = BAR0_SIZE_BASE + vio.configSize;
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vio.registerKickCallback(&callbackKick);
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}
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PciVirtIO::~PciVirtIO()
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{
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}
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Tick
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PciVirtIO::read(PacketPtr pkt)
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{
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const unsigned M5_VAR_USED size(pkt->getSize());
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int bar;
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Addr offset;
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if (!getBAR(pkt->getAddr(), bar, offset))
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panic("Invalid PCI memory access to unmapped memory.\n");
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assert(bar == 0);
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DPRINTF(VIOPci, "Reading offset 0x%x [len: %i]\n", offset, size);
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// Forward device configuration writes to the device VirtIO model
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if (offset >= OFF_VIO_DEVICE) {
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vio.readConfig(pkt, offset - OFF_VIO_DEVICE);
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return 0;
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}
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switch(offset) {
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case OFF_DEVICE_FEATURES:
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DPRINTF(VIOPci, " DEVICE_FEATURES request\n");
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assert(size == sizeof(uint32_t));
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pkt->set<uint32_t>(vio.deviceFeatures);
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break;
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case OFF_GUEST_FEATURES:
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DPRINTF(VIOPci, " GUEST_FEATURES request\n");
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assert(size == sizeof(uint32_t));
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pkt->set<uint32_t>(vio.getGuestFeatures());
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break;
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case OFF_QUEUE_ADDRESS:
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DPRINTF(VIOPci, " QUEUE_ADDRESS request\n");
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assert(size == sizeof(uint32_t));
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pkt->set<uint32_t>(vio.getQueueAddress());
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break;
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case OFF_QUEUE_SIZE:
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DPRINTF(VIOPci, " QUEUE_SIZE request\n");
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assert(size == sizeof(uint16_t));
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pkt->set<uint16_t>(vio.getQueueSize());
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break;
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case OFF_QUEUE_SELECT:
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DPRINTF(VIOPci, " QUEUE_SELECT\n");
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assert(size == sizeof(uint16_t));
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pkt->set<uint16_t>(vio.getQueueSelect());
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break;
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case OFF_QUEUE_NOTIFY:
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DPRINTF(VIOPci, " QUEUE_NOTIFY request\n");
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assert(size == sizeof(uint16_t));
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pkt->set<uint16_t>(queueNotify);
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break;
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case OFF_DEVICE_STATUS:
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DPRINTF(VIOPci, " DEVICE_STATUS request\n");
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assert(size == sizeof(uint8_t));
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pkt->set<uint8_t>(vio.getDeviceStatus());
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break;
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case OFF_ISR_STATUS: {
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DPRINTF(VIOPci, " ISR_STATUS\n");
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assert(size == sizeof(uint8_t));
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uint8_t isr_status(interruptDeliveryPending ? 1 : 0);
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interruptDeliveryPending = false;
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pkt->set<uint8_t>(isr_status);
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} break;
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default:
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panic("Unhandled read offset (0x%x)\n", offset);
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}
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return 0;
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}
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Tick
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PciVirtIO::write(PacketPtr pkt)
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{
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const unsigned M5_VAR_USED size(pkt->getSize());
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int bar;
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Addr offset;
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if (!getBAR(pkt->getAddr(), bar, offset))
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panic("Invalid PCI memory access to unmapped memory.\n");
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assert(bar == 0);
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DPRINTF(VIOPci, "Writing offset 0x%x [len: %i]\n", offset, size);
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// Forward device configuration writes to the device VirtIO model
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if (offset >= OFF_VIO_DEVICE) {
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vio.writeConfig(pkt, offset - OFF_VIO_DEVICE);
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return 0;
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}
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switch(offset) {
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case OFF_DEVICE_FEATURES:
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warn("Guest tried to write device features.");
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break;
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case OFF_GUEST_FEATURES:
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DPRINTF(VIOPci, " WRITE GUEST_FEATURES request\n");
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assert(size == sizeof(uint32_t));
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vio.setGuestFeatures(pkt->get<uint32_t>());
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break;
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case OFF_QUEUE_ADDRESS:
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DPRINTF(VIOPci, " WRITE QUEUE_ADDRESS\n");
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assert(size == sizeof(uint32_t));
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vio.setQueueAddress(pkt->get<uint32_t>());
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break;
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case OFF_QUEUE_SIZE:
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panic("Guest tried to write queue size.");
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break;
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case OFF_QUEUE_SELECT:
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DPRINTF(VIOPci, " WRITE QUEUE_SELECT\n");
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assert(size == sizeof(uint16_t));
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vio.setQueueSelect(pkt->get<uint16_t>());
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break;
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case OFF_QUEUE_NOTIFY:
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DPRINTF(VIOPci, " WRITE QUEUE_NOTIFY\n");
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assert(size == sizeof(uint16_t));
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queueNotify = pkt->get<uint16_t>();
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vio.onNotify(queueNotify);
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break;
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case OFF_DEVICE_STATUS: {
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assert(size == sizeof(uint8_t));
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uint8_t status(pkt->get<uint8_t>());
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DPRINTF(VIOPci, "VirtIO set status: 0x%x\n", status);
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vio.setDeviceStatus(status);
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} break;
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case OFF_ISR_STATUS:
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warn("Guest tried to write ISR status.");
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break;
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default:
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panic("Unhandled read offset (0x%x)\n", offset);
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}
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return 0;
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}
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void
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PciVirtIO::kick()
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{
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DPRINTF(VIOPci, "kick(): Sending interrupt...\n");
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interruptDeliveryPending = true;
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intrPost();
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}
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PciVirtIO *
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PciVirtIOParams::create()
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{
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return new PciVirtIO(this);
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}
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