2011-02-08 04:23:11 +01:00
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---------- Begin Simulation Statistics ----------
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2011-08-19 22:08:09 +02:00
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sim_seconds 2.332317 # Number of seconds simulated
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sim_ticks 2332316587000 # Number of ticks simulated
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2011-02-08 04:23:11 +01:00
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sim_freq 1000000000000 # Frequency of simulated ticks
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2011-08-19 22:08:09 +02:00
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host_inst_rate 1407778 # Simulator instruction rate (inst/s)
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host_tick_rate 42901571145 # Simulator tick rate (ticks/s)
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host_mem_usage 417476 # Number of bytes of host memory used
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host_seconds 54.36 # Real time elapsed on the host
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sim_insts 76532931 # Number of instructions simulated
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system.l2c.replacements 116822 # number of replacements
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system.l2c.tagsinuse 24240.388378 # Cycle average of tags in use
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system.l2c.total_refs 1520830 # Total number of references to valid blocks.
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system.l2c.sampled_refs 146847 # Sample count of references to valid blocks.
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system.l2c.avg_refs 10.356562 # Average number of references to valid blocks.
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system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.l2c.occ_blocks::0 10591.091336 # Average occupied blocks per context
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system.l2c.occ_blocks::1 13649.297042 # Average occupied blocks per context
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system.l2c.occ_percent::0 0.161607 # Average percentage of cache occupancy
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system.l2c.occ_percent::1 0.208272 # Average percentage of cache occupancy
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system.l2c.ReadReq_hits::0 1188216 # number of ReadReq hits
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system.l2c.ReadReq_hits::1 10669 # number of ReadReq hits
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system.l2c.ReadReq_hits::total 1198885 # number of ReadReq hits
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system.l2c.Writeback_hits::0 604613 # number of Writeback hits
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system.l2c.Writeback_hits::total 604613 # number of Writeback hits
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system.l2c.UpgradeReq_hits::0 26 # number of UpgradeReq hits
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system.l2c.UpgradeReq_hits::total 26 # number of UpgradeReq hits
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system.l2c.ReadExReq_hits::0 105791 # number of ReadExReq hits
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system.l2c.ReadExReq_hits::total 105791 # number of ReadExReq hits
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system.l2c.demand_hits::0 1294007 # number of demand (read+write) hits
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system.l2c.demand_hits::1 10669 # number of demand (read+write) hits
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system.l2c.demand_hits::total 1304676 # number of demand (read+write) hits
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system.l2c.overall_hits::0 1294007 # number of overall hits
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system.l2c.overall_hits::1 10669 # number of overall hits
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system.l2c.overall_hits::total 1304676 # number of overall hits
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system.l2c.ReadReq_misses::0 31716 # number of ReadReq misses
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system.l2c.ReadReq_misses::1 27 # number of ReadReq misses
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system.l2c.ReadReq_misses::total 31743 # number of ReadReq misses
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system.l2c.UpgradeReq_misses::0 2911 # number of UpgradeReq misses
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system.l2c.UpgradeReq_misses::total 2911 # number of UpgradeReq misses
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system.l2c.ReadExReq_misses::0 141169 # number of ReadExReq misses
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system.l2c.ReadExReq_misses::total 141169 # number of ReadExReq misses
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system.l2c.demand_misses::0 172885 # number of demand (read+write) misses
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system.l2c.demand_misses::1 27 # number of demand (read+write) misses
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system.l2c.demand_misses::total 172912 # number of demand (read+write) misses
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system.l2c.overall_misses::0 172885 # number of overall misses
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system.l2c.overall_misses::1 27 # number of overall misses
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system.l2c.overall_misses::total 172912 # number of overall misses
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system.l2c.demand_miss_latency 0 # number of demand (read+write) miss cycles
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system.l2c.overall_miss_latency 0 # number of overall miss cycles
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system.l2c.ReadReq_accesses::0 1219932 # number of ReadReq accesses(hits+misses)
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system.l2c.ReadReq_accesses::1 10696 # number of ReadReq accesses(hits+misses)
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system.l2c.ReadReq_accesses::total 1230628 # number of ReadReq accesses(hits+misses)
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system.l2c.Writeback_accesses::0 604613 # number of Writeback accesses(hits+misses)
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system.l2c.Writeback_accesses::total 604613 # number of Writeback accesses(hits+misses)
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system.l2c.UpgradeReq_accesses::0 2937 # number of UpgradeReq accesses(hits+misses)
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system.l2c.UpgradeReq_accesses::total 2937 # number of UpgradeReq accesses(hits+misses)
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system.l2c.ReadExReq_accesses::0 246960 # number of ReadExReq accesses(hits+misses)
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system.l2c.ReadExReq_accesses::total 246960 # number of ReadExReq accesses(hits+misses)
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system.l2c.demand_accesses::0 1466892 # number of demand (read+write) accesses
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system.l2c.demand_accesses::1 10696 # number of demand (read+write) accesses
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system.l2c.demand_accesses::total 1477588 # number of demand (read+write) accesses
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system.l2c.overall_accesses::0 1466892 # number of overall (read+write) accesses
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system.l2c.overall_accesses::1 10696 # number of overall (read+write) accesses
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system.l2c.overall_accesses::total 1477588 # number of overall (read+write) accesses
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system.l2c.ReadReq_miss_rate::0 0.025998 # miss rate for ReadReq accesses
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system.l2c.ReadReq_miss_rate::1 0.002524 # miss rate for ReadReq accesses
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system.l2c.ReadReq_miss_rate::total 0.028522 # miss rate for ReadReq accesses
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system.l2c.UpgradeReq_miss_rate::0 0.991147 # miss rate for UpgradeReq accesses
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system.l2c.ReadExReq_miss_rate::0 0.571627 # miss rate for ReadExReq accesses
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system.l2c.demand_miss_rate::0 0.117858 # miss rate for demand accesses
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system.l2c.demand_miss_rate::1 0.002524 # miss rate for demand accesses
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system.l2c.demand_miss_rate::total 0.120382 # miss rate for demand accesses
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system.l2c.overall_miss_rate::0 0.117858 # miss rate for overall accesses
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system.l2c.overall_miss_rate::1 0.002524 # miss rate for overall accesses
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system.l2c.overall_miss_rate::total 0.120382 # miss rate for overall accesses
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system.l2c.demand_avg_miss_latency::0 0 # average overall miss latency
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system.l2c.demand_avg_miss_latency::1 0 # average overall miss latency
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system.l2c.demand_avg_miss_latency::total 0 # average overall miss latency
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system.l2c.overall_avg_miss_latency::0 0 # average overall miss latency
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system.l2c.overall_avg_miss_latency::1 0 # average overall miss latency
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system.l2c.overall_avg_miss_latency::total 0 # average overall miss latency
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system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
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system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
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system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
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system.l2c.blocked::no_targets 0 # number of cycles access was blocked
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system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
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system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
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system.l2c.fast_writes 0 # number of fast writes performed
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system.l2c.cache_copies 0 # number of cache copies performed
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system.l2c.writebacks 102531 # number of writebacks
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system.l2c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
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system.l2c.overall_mshr_hits 0 # number of overall MSHR hits
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system.l2c.demand_mshr_misses 0 # number of demand (read+write) MSHR misses
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system.l2c.overall_mshr_misses 0 # number of overall MSHR misses
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system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
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system.l2c.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles
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system.l2c.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles
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system.l2c.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
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system.l2c.demand_mshr_miss_rate::0 0 # mshr miss rate for demand accesses
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system.l2c.demand_mshr_miss_rate::1 0 # mshr miss rate for demand accesses
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system.l2c.demand_mshr_miss_rate::total 0 # mshr miss rate for demand accesses
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system.l2c.overall_mshr_miss_rate::0 0 # mshr miss rate for overall accesses
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system.l2c.overall_mshr_miss_rate::1 0 # mshr miss rate for overall accesses
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system.l2c.overall_mshr_miss_rate::total 0 # mshr miss rate for overall accesses
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system.l2c.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency
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system.l2c.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency
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system.l2c.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
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system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated
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system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
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system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
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system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
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system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD).
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system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes.
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system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes.
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system.cf0.dma_write_txs 0 # Number of DMA write transactions.
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system.cpu.dtb.inst_hits 0 # ITB inst hits
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system.cpu.dtb.inst_misses 0 # ITB inst misses
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system.cpu.dtb.read_hits 14940566 # DTB read hits
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system.cpu.dtb.read_misses 7288 # DTB read misses
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system.cpu.dtb.write_hits 11198205 # DTB write hits
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system.cpu.dtb.write_misses 2199 # DTB write misses
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2011-02-08 04:23:11 +01:00
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system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed
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system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
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2011-08-19 22:08:09 +02:00
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system.cpu.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
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system.cpu.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
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system.cpu.dtb.flush_entries 3505 # Number of entries that have been flushed from TLB
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system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
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system.cpu.dtb.prefetch_faults 189 # Number of TLB faults due to prefetch
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system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
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system.cpu.dtb.perms_faults 452 # Number of TLB faults due to permissions restrictions
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system.cpu.dtb.read_accesses 14947854 # DTB read accesses
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system.cpu.dtb.write_accesses 11200404 # DTB write accesses
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2011-02-08 04:23:11 +01:00
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system.cpu.dtb.inst_accesses 0 # ITB inst accesses
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2011-08-19 22:08:09 +02:00
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system.cpu.dtb.hits 26138771 # DTB hits
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system.cpu.dtb.misses 9487 # DTB misses
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system.cpu.dtb.accesses 26148258 # DTB accesses
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system.cpu.itb.inst_hits 60273889 # ITB inst hits
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system.cpu.itb.inst_misses 4471 # ITB inst misses
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system.cpu.itb.read_hits 0 # DTB read hits
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system.cpu.itb.read_misses 0 # DTB read misses
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system.cpu.itb.write_hits 0 # DTB write hits
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system.cpu.itb.write_misses 0 # DTB write misses
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system.cpu.itb.flush_tlb 2 # Number of times complete TLB was flushed
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system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
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system.cpu.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
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system.cpu.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
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system.cpu.itb.flush_entries 2343 # Number of entries that have been flushed from TLB
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system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
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system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
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system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
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system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
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system.cpu.itb.read_accesses 0 # DTB read accesses
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system.cpu.itb.write_accesses 0 # DTB write accesses
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system.cpu.itb.inst_accesses 60278360 # ITB inst accesses
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system.cpu.itb.hits 60273889 # DTB hits
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system.cpu.itb.misses 4471 # DTB misses
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system.cpu.itb.accesses 60278360 # DTB accesses
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system.cpu.numCycles 4664556206 # number of cpu cycles simulated
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system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
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system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
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system.cpu.num_insts 76532931 # Number of instructions executed
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system.cpu.num_int_alu_accesses 68161177 # Number of integer alu accesses
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system.cpu.num_fp_alu_accesses 10269 # Number of float alu accesses
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system.cpu.num_func_calls 1971944 # number of times a function call or return occured
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system.cpu.num_conditional_control_insts 7572657 # number of instructions that are conditional controls
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system.cpu.num_int_insts 68161177 # number of integer instructions
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system.cpu.num_fp_insts 10269 # number of float instructions
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system.cpu.num_int_register_reads 345365607 # number of times the integer registers were read
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system.cpu.num_int_register_writes 72877692 # number of times the integer registers were written
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system.cpu.num_fp_register_reads 7493 # number of times the floating registers were read
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system.cpu.num_fp_register_writes 2780 # number of times the floating registers were written
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system.cpu.num_mem_refs 27310784 # number of memory refs
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system.cpu.num_load_insts 15607074 # Number of load instructions
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system.cpu.num_store_insts 11703710 # Number of store instructions
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system.cpu.num_idle_cycles 4586920150.977920 # Number of idle cycles
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system.cpu.num_busy_cycles 77636055.022080 # Number of busy cycles
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system.cpu.not_idle_fraction 0.016644 # Percentage of non-idle cycles
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system.cpu.idle_fraction 0.983356 # Percentage of idle cycles
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system.cpu.kern.inst.arm 0 # number of arm instructions executed
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system.cpu.kern.inst.quiesce 82751 # number of quiesce instructions executed
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system.cpu.icache.replacements 847054 # number of replacements
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|
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system.cpu.icache.tagsinuse 511.678552 # Cycle average of tags in use
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system.cpu.icache.total_refs 59429083 # Total number of references to valid blocks.
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|
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system.cpu.icache.sampled_refs 847566 # Sample count of references to valid blocks.
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system.cpu.icache.avg_refs 70.117351 # Average number of references to valid blocks.
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system.cpu.icache.warmup_cycle 5705452000 # Cycle when the warmup percentage was hit.
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system.cpu.icache.occ_blocks::0 511.678552 # Average occupied blocks per context
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system.cpu.icache.occ_percent::0 0.999372 # Average percentage of cache occupancy
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system.cpu.icache.ReadReq_hits::0 59429083 # number of ReadReq hits
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system.cpu.icache.ReadReq_hits::total 59429083 # number of ReadReq hits
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system.cpu.icache.demand_hits::0 59429083 # number of demand (read+write) hits
|
2011-02-08 04:23:11 +01:00
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system.cpu.icache.demand_hits::1 0 # number of demand (read+write) hits
|
2011-08-19 22:08:09 +02:00
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|
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system.cpu.icache.demand_hits::total 59429083 # number of demand (read+write) hits
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system.cpu.icache.overall_hits::0 59429083 # number of overall hits
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system.cpu.icache.overall_hits::1 0 # number of overall hits
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system.cpu.icache.overall_hits::total 59429083 # number of overall hits
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system.cpu.icache.ReadReq_misses::0 847566 # number of ReadReq misses
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system.cpu.icache.ReadReq_misses::total 847566 # number of ReadReq misses
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system.cpu.icache.demand_misses::0 847566 # number of demand (read+write) misses
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system.cpu.icache.demand_misses::1 0 # number of demand (read+write) misses
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system.cpu.icache.demand_misses::total 847566 # number of demand (read+write) misses
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system.cpu.icache.overall_misses::0 847566 # number of overall misses
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|
|
system.cpu.icache.overall_misses::1 0 # number of overall misses
|
|
|
|
|
system.cpu.icache.overall_misses::total 847566 # number of overall misses
|
2011-02-08 04:23:11 +01:00
|
|
|
system.cpu.icache.demand_miss_latency 0 # number of demand (read+write) miss cycles
|
2011-08-19 22:08:09 +02:00
|
|
|
system.cpu.icache.overall_miss_latency 0 # number of overall miss cycles
|
|
|
|
|
system.cpu.icache.ReadReq_accesses::0 60276649 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.icache.ReadReq_accesses::total 60276649 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.icache.demand_accesses::0 60276649 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.icache.demand_accesses::1 0 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.icache.demand_accesses::total 60276649 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.icache.overall_accesses::0 60276649 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.icache.overall_accesses::1 0 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.icache.overall_accesses::total 60276649 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.icache.ReadReq_miss_rate::0 0.014061 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.icache.demand_miss_rate::0 0.014061 # miss rate for demand accesses
|
2011-02-08 04:23:11 +01:00
|
|
|
system.cpu.icache.demand_miss_rate::1 no_value # miss rate for demand accesses
|
|
|
|
|
system.cpu.icache.demand_miss_rate::total no_value # miss rate for demand accesses
|
2011-08-19 22:08:09 +02:00
|
|
|
system.cpu.icache.overall_miss_rate::0 0.014061 # miss rate for overall accesses
|
|
|
|
|
system.cpu.icache.overall_miss_rate::1 no_value # miss rate for overall accesses
|
|
|
|
|
system.cpu.icache.overall_miss_rate::total no_value # miss rate for overall accesses
|
|
|
|
|
system.cpu.icache.demand_avg_miss_latency::0 0 # average overall miss latency
|
|
|
|
|
system.cpu.icache.demand_avg_miss_latency::1 no_value # average overall miss latency
|
|
|
|
|
system.cpu.icache.demand_avg_miss_latency::total no_value # average overall miss latency
|
2011-02-08 04:23:11 +01:00
|
|
|
system.cpu.icache.overall_avg_miss_latency::0 0 # average overall miss latency
|
|
|
|
|
system.cpu.icache.overall_avg_miss_latency::1 no_value # average overall miss latency
|
|
|
|
|
system.cpu.icache.overall_avg_miss_latency::total no_value # average overall miss latency
|
2011-08-19 22:08:09 +02:00
|
|
|
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
|
|
|
|
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
|
|
|
|
system.cpu.icache.writebacks 44721 # number of writebacks
|
|
|
|
|
system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
2011-02-08 04:23:11 +01:00
|
|
|
system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
|
2011-08-19 22:08:09 +02:00
|
|
|
system.cpu.icache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.icache.overall_mshr_misses 0 # number of overall MSHR misses
|
|
|
|
|
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
|
|
|
|
system.cpu.icache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles
|
2011-02-08 04:23:11 +01:00
|
|
|
system.cpu.icache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles
|
2011-08-19 22:08:09 +02:00
|
|
|
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
|
|
|
|
system.cpu.icache.demand_mshr_miss_rate::0 0 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.icache.demand_mshr_miss_rate::1 no_value # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.icache.demand_mshr_miss_rate::total no_value # mshr miss rate for demand accesses
|
2011-02-08 04:23:11 +01:00
|
|
|
system.cpu.icache.overall_mshr_miss_rate::0 0 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.icache.overall_mshr_miss_rate::1 no_value # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.icache.overall_mshr_miss_rate::total no_value # mshr miss rate for overall accesses
|
2011-08-19 22:08:09 +02:00
|
|
|
system.cpu.icache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency
|
|
|
|
|
system.cpu.icache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency
|
|
|
|
|
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
|
|
|
|
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
2011-02-08 04:23:11 +01:00
|
|
|
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
2011-08-19 22:08:09 +02:00
|
|
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
|
|
|
system.cpu.dcache.replacements 622134 # number of replacements
|
|
|
|
|
system.cpu.dcache.tagsinuse 511.997030 # Cycle average of tags in use
|
|
|
|
|
system.cpu.dcache.total_refs 23580069 # Total number of references to valid blocks.
|
|
|
|
|
system.cpu.dcache.sampled_refs 622646 # Sample count of references to valid blocks.
|
|
|
|
|
system.cpu.dcache.avg_refs 37.870747 # Average number of references to valid blocks.
|
|
|
|
|
system.cpu.dcache.warmup_cycle 21763000 # Cycle when the warmup percentage was hit.
|
|
|
|
|
system.cpu.dcache.occ_blocks::0 511.997030 # Average occupied blocks per context
|
|
|
|
|
system.cpu.dcache.occ_percent::0 0.999994 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.dcache.ReadReq_hits::0 13150366 # number of ReadReq hits
|
|
|
|
|
system.cpu.dcache.ReadReq_hits::total 13150366 # number of ReadReq hits
|
|
|
|
|
system.cpu.dcache.WriteReq_hits::0 9943631 # number of WriteReq hits
|
|
|
|
|
system.cpu.dcache.WriteReq_hits::total 9943631 # number of WriteReq hits
|
|
|
|
|
system.cpu.dcache.LoadLockedReq_hits::0 235999 # number of LoadLockedReq hits
|
|
|
|
|
system.cpu.dcache.LoadLockedReq_hits::total 235999 # number of LoadLockedReq hits
|
|
|
|
|
system.cpu.dcache.StoreCondReq_hits::0 247136 # number of StoreCondReq hits
|
|
|
|
|
system.cpu.dcache.StoreCondReq_hits::total 247136 # number of StoreCondReq hits
|
|
|
|
|
system.cpu.dcache.demand_hits::0 23093997 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.dcache.demand_hits::1 0 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.dcache.demand_hits::total 23093997 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.dcache.overall_hits::0 23093997 # number of overall hits
|
|
|
|
|
system.cpu.dcache.overall_hits::1 0 # number of overall hits
|
|
|
|
|
system.cpu.dcache.overall_hits::total 23093997 # number of overall hits
|
|
|
|
|
system.cpu.dcache.ReadReq_misses::0 364548 # number of ReadReq misses
|
|
|
|
|
system.cpu.dcache.ReadReq_misses::total 364548 # number of ReadReq misses
|
|
|
|
|
system.cpu.dcache.WriteReq_misses::0 249897 # number of WriteReq misses
|
|
|
|
|
system.cpu.dcache.WriteReq_misses::total 249897 # number of WriteReq misses
|
|
|
|
|
system.cpu.dcache.LoadLockedReq_misses::0 11138 # number of LoadLockedReq misses
|
|
|
|
|
system.cpu.dcache.LoadLockedReq_misses::total 11138 # number of LoadLockedReq misses
|
|
|
|
|
system.cpu.dcache.demand_misses::0 614445 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.dcache.demand_misses::1 0 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.dcache.demand_misses::total 614445 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.dcache.overall_misses::0 614445 # number of overall misses
|
|
|
|
|
system.cpu.dcache.overall_misses::1 0 # number of overall misses
|
|
|
|
|
system.cpu.dcache.overall_misses::total 614445 # number of overall misses
|
|
|
|
|
system.cpu.dcache.demand_miss_latency 0 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.dcache.overall_miss_latency 0 # number of overall miss cycles
|
|
|
|
|
system.cpu.dcache.ReadReq_accesses::0 13514914 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.dcache.ReadReq_accesses::total 13514914 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.dcache.WriteReq_accesses::0 10193528 # number of WriteReq accesses(hits+misses)
|
|
|
|
|
system.cpu.dcache.WriteReq_accesses::total 10193528 # number of WriteReq accesses(hits+misses)
|
|
|
|
|
system.cpu.dcache.LoadLockedReq_accesses::0 247137 # number of LoadLockedReq accesses(hits+misses)
|
|
|
|
|
system.cpu.dcache.LoadLockedReq_accesses::total 247137 # number of LoadLockedReq accesses(hits+misses)
|
|
|
|
|
system.cpu.dcache.StoreCondReq_accesses::0 247136 # number of StoreCondReq accesses(hits+misses)
|
|
|
|
|
system.cpu.dcache.StoreCondReq_accesses::total 247136 # number of StoreCondReq accesses(hits+misses)
|
|
|
|
|
system.cpu.dcache.demand_accesses::0 23708442 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.dcache.demand_accesses::1 0 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.dcache.demand_accesses::total 23708442 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.dcache.overall_accesses::0 23708442 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.dcache.overall_accesses::1 0 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.dcache.overall_accesses::total 23708442 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.dcache.ReadReq_miss_rate::0 0.026974 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.dcache.WriteReq_miss_rate::0 0.024515 # miss rate for WriteReq accesses
|
|
|
|
|
system.cpu.dcache.LoadLockedReq_miss_rate::0 0.045068 # miss rate for LoadLockedReq accesses
|
|
|
|
|
system.cpu.dcache.demand_miss_rate::0 0.025917 # miss rate for demand accesses
|
|
|
|
|
system.cpu.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses
|
|
|
|
|
system.cpu.dcache.demand_miss_rate::total no_value # miss rate for demand accesses
|
|
|
|
|
system.cpu.dcache.overall_miss_rate::0 0.025917 # miss rate for overall accesses
|
|
|
|
|
system.cpu.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses
|
|
|
|
|
system.cpu.dcache.overall_miss_rate::total no_value # miss rate for overall accesses
|
|
|
|
|
system.cpu.dcache.demand_avg_miss_latency::0 0 # average overall miss latency
|
|
|
|
|
system.cpu.dcache.demand_avg_miss_latency::1 no_value # average overall miss latency
|
|
|
|
|
system.cpu.dcache.demand_avg_miss_latency::total no_value # average overall miss latency
|
|
|
|
|
system.cpu.dcache.overall_avg_miss_latency::0 0 # average overall miss latency
|
|
|
|
|
system.cpu.dcache.overall_avg_miss_latency::1 no_value # average overall miss latency
|
|
|
|
|
system.cpu.dcache.overall_avg_miss_latency::total no_value # average overall miss latency
|
|
|
|
|
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
|
|
|
|
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
|
|
|
|
system.cpu.dcache.writebacks 559892 # number of writebacks
|
|
|
|
|
system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
|
|
|
|
system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
|
|
|
|
|
system.cpu.dcache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.dcache.overall_mshr_misses 0 # number of overall MSHR misses
|
|
|
|
|
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
|
|
|
|
system.cpu.dcache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
|
|
|
|
system.cpu.dcache.demand_mshr_miss_rate::0 0 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.dcache.demand_mshr_miss_rate::1 no_value # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.dcache.demand_mshr_miss_rate::total no_value # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.dcache.overall_mshr_miss_rate::0 0 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.dcache.overall_mshr_miss_rate::1 no_value # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.dcache.overall_mshr_miss_rate::total no_value # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency
|
|
|
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency
|
|
|
|
|
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
|
|
|
|
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
|
|
|
|
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
|
|
|
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
|
|
|
system.iocache.replacements 0 # number of replacements
|
|
|
|
|
system.iocache.tagsinuse 0 # Cycle average of tags in use
|
|
|
|
|
system.iocache.total_refs 0 # Total number of references to valid blocks.
|
|
|
|
|
system.iocache.sampled_refs 0 # Sample count of references to valid blocks.
|
2011-02-08 04:23:11 +01:00
|
|
|
system.iocache.avg_refs no_value # Average number of references to valid blocks.
|
2011-08-19 22:08:09 +02:00
|
|
|
system.iocache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
2011-02-08 04:23:11 +01:00
|
|
|
system.iocache.demand_hits::0 0 # number of demand (read+write) hits
|
|
|
|
|
system.iocache.demand_hits::1 0 # number of demand (read+write) hits
|
|
|
|
|
system.iocache.demand_hits::total 0 # number of demand (read+write) hits
|
2011-08-19 22:08:09 +02:00
|
|
|
system.iocache.overall_hits::0 0 # number of overall hits
|
|
|
|
|
system.iocache.overall_hits::1 0 # number of overall hits
|
|
|
|
|
system.iocache.overall_hits::total 0 # number of overall hits
|
2011-02-08 04:23:11 +01:00
|
|
|
system.iocache.demand_misses::0 0 # number of demand (read+write) misses
|
|
|
|
|
system.iocache.demand_misses::1 0 # number of demand (read+write) misses
|
|
|
|
|
system.iocache.demand_misses::total 0 # number of demand (read+write) misses
|
2011-08-19 22:08:09 +02:00
|
|
|
system.iocache.overall_misses::0 0 # number of overall misses
|
|
|
|
|
system.iocache.overall_misses::1 0 # number of overall misses
|
|
|
|
|
system.iocache.overall_misses::total 0 # number of overall misses
|
|
|
|
|
system.iocache.demand_miss_latency 0 # number of demand (read+write) miss cycles
|
|
|
|
|
system.iocache.overall_miss_latency 0 # number of overall miss cycles
|
|
|
|
|
system.iocache.demand_accesses::0 0 # number of demand (read+write) accesses
|
|
|
|
|
system.iocache.demand_accesses::1 0 # number of demand (read+write) accesses
|
|
|
|
|
system.iocache.demand_accesses::total 0 # number of demand (read+write) accesses
|
2011-02-08 04:23:11 +01:00
|
|
|
system.iocache.overall_accesses::0 0 # number of overall (read+write) accesses
|
|
|
|
|
system.iocache.overall_accesses::1 0 # number of overall (read+write) accesses
|
|
|
|
|
system.iocache.overall_accesses::total 0 # number of overall (read+write) accesses
|
2011-08-19 22:08:09 +02:00
|
|
|
system.iocache.demand_miss_rate::0 no_value # miss rate for demand accesses
|
|
|
|
|
system.iocache.demand_miss_rate::1 no_value # miss rate for demand accesses
|
|
|
|
|
system.iocache.demand_miss_rate::total no_value # miss rate for demand accesses
|
2011-02-08 04:23:11 +01:00
|
|
|
system.iocache.overall_miss_rate::0 no_value # miss rate for overall accesses
|
|
|
|
|
system.iocache.overall_miss_rate::1 no_value # miss rate for overall accesses
|
|
|
|
|
system.iocache.overall_miss_rate::total no_value # miss rate for overall accesses
|
2011-08-19 22:08:09 +02:00
|
|
|
system.iocache.demand_avg_miss_latency::0 no_value # average overall miss latency
|
|
|
|
|
system.iocache.demand_avg_miss_latency::1 no_value # average overall miss latency
|
|
|
|
|
system.iocache.demand_avg_miss_latency::total no_value # average overall miss latency
|
|
|
|
|
system.iocache.overall_avg_miss_latency::0 no_value # average overall miss latency
|
|
|
|
|
system.iocache.overall_avg_miss_latency::1 no_value # average overall miss latency
|
|
|
|
|
system.iocache.overall_avg_miss_latency::total no_value # average overall miss latency
|
|
|
|
|
system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.iocache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
|
|
|
|
system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
|
|
|
|
system.iocache.fast_writes 0 # number of fast writes performed
|
|
|
|
|
system.iocache.cache_copies 0 # number of cache copies performed
|
|
|
|
|
system.iocache.writebacks 0 # number of writebacks
|
|
|
|
|
system.iocache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
2011-02-08 04:23:11 +01:00
|
|
|
system.iocache.overall_mshr_hits 0 # number of overall MSHR hits
|
2011-08-19 22:08:09 +02:00
|
|
|
system.iocache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.iocache.overall_mshr_misses 0 # number of overall MSHR misses
|
|
|
|
|
system.iocache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
|
|
|
|
system.iocache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles
|
2011-02-08 04:23:11 +01:00
|
|
|
system.iocache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles
|
2011-08-19 22:08:09 +02:00
|
|
|
system.iocache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
|
|
|
|
system.iocache.demand_mshr_miss_rate::0 no_value # mshr miss rate for demand accesses
|
|
|
|
|
system.iocache.demand_mshr_miss_rate::1 no_value # mshr miss rate for demand accesses
|
|
|
|
|
system.iocache.demand_mshr_miss_rate::total no_value # mshr miss rate for demand accesses
|
2011-02-08 04:23:11 +01:00
|
|
|
system.iocache.overall_mshr_miss_rate::0 no_value # mshr miss rate for overall accesses
|
|
|
|
|
system.iocache.overall_mshr_miss_rate::1 no_value # mshr miss rate for overall accesses
|
|
|
|
|
system.iocache.overall_mshr_miss_rate::total no_value # mshr miss rate for overall accesses
|
2011-08-19 22:08:09 +02:00
|
|
|
system.iocache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency
|
|
|
|
|
system.iocache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency
|
|
|
|
|
system.iocache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
|
|
|
|
system.iocache.mshr_cap_events 0 # number of times MSHR cap was activated
|
2011-02-08 04:23:11 +01:00
|
|
|
system.iocache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
2011-08-19 22:08:09 +02:00
|
|
|
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
|
2011-02-08 04:23:11 +01:00
|
|
|
|
|
|
|
|
---------- End Simulation Statistics ----------
|
