191 lines
4.3 KiB
Text
191 lines
4.3 KiB
Text
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//Default parameters, taken from /athitos/export/08spr_ee382a/sanchezd/runs/gen-scripts/ruby.defaults
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//General config
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g_DEADLOCK_THRESHOLD: 20000000
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RANDOMIZATION: false
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g_tester_length: 0
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SIMICS_RUBY_MULTIPLIER: 1
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OPAL_RUBY_MULTIPLIER: 1
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TRANSACTION_TRACE_ENABLED: false
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USER_MODE_DATA_ONLY: false
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PROFILE_HOT_LINES: false
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PROFILE_ALL_INSTRUCTIONS: false
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PRINT_INSTRUCTION_TRACE: false
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g_DEBUG_CYCLE: 0
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PERFECT_MEMORY_SYSTEM: false
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PERFECT_MEMORY_SYSTEM_LATENCY: 0
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DATA_BLOCK: false
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// Line, page sizes
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g_DATA_BLOCK_BYTES: 64
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g_PAGE_SIZE_BYTES: 8192
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g_REPLACEMENT_POLICY: PSEDUO_LRU
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// For all caches (sic)
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// L1 config
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// 32KB, 4-way SA
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L1_CACHE_ASSOC: 4
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L1_CACHE_NUM_SETS_BITS: 7
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// Single-cycle latency, hits take fastpath
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SEQUENCER_TO_CONTROLLER_LATENCY: 1
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REMOVE_SINGLE_CYCLE_DCACHE_FAST_PATH: false
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// L1->L2 delays
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L1_REQUEST_LATENCY: 1
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L1_RESPONSE_LATENCY: 1
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// L2 parameters
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// 4 MB, 16-way SA
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L2_CACHE_ASSOC: 16
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L2_CACHE_NUM_SETS_BITS: 12
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MAP_L2BANKS_TO_LOWEST_BITS: false
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// Bank latencies
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L2_RESPONSE_LATENCY: 10
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L2_TAG_LATENCY: 5
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// Directory latencies
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// The one that counts, we have perfect dirs
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DIRECTORY_CACHE_LATENCY: 6
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// should not be used, but just in case...
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DIRECTORY_LATENCY: 6
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// Simple network parameters
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// external links
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NETWORK_LINK_LATENCY: 1
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// intra-chip links
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ON_CHIP_LINK_LATENCY: 1
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// General latencies
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RECYCLE_LATENCY: 1
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//Used in MessageBuffer, also MSI_MOSI_CMP dir controller
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// Unused parameters, good to define them to really weird things just in case
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NULL_LATENCY: 100000
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// Only SMP and token CMP protocols
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ISSUE_LATENCY: 100000
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// Only SMP, example protocols
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CACHE_RESPONSE_LATENCY: 100000
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// Only SMP protocols
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COPY_HEAD_LATENCY: 100000
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// In no protocols or ruby code
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L2_RECYCLE_LATENCY: 100000
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// In no protocols or ruby code
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TIMER_LATENCY: 100000
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// Not used
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TBE_RESPONSE_LATENCY: 100000
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// Not used
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PERIODIC_TIMER_WAKEUPS: false
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// Not used
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BLOCK_STC: false
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// Not used
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SINGLE_ACCESS_L2_BANKS: false
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// Not used
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// Main memory latency
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MEMORY_RESPONSE_LATENCY_MINUS_2: 448 //not used in _m, see below
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PROFILE_EXCEPTIONS: false
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PROFILE_XACT: false
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PROFILE_NONXACT: true
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XACT_DEBUG: false
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XACT_DEBUG_LEVEL: 1
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XACT_MEMORY: false
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XACT_ENABLE_TOURMALINE: false
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XACT_NUM_CURRENT: 0
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XACT_LAST_UPDATE: 0
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XACT_ISOLATION_CHECK: false
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PERFECT_FILTER: true
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READ_WRITE_FILTER: Perfect_
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PERFECT_VIRTUAL_FILTER: true
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VIRTUAL_READ_WRITE_FILTER: Perfect_
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PERFECT_SUMMARY_FILTER: true
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SUMMARY_READ_WRITE_FILTER: Perfect_
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XACT_EAGER_CD: true
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XACT_LAZY_VM: false
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XACT_CONFLICT_RES: BASE
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XACT_COMMIT_TOKEN_LATENCY: 0
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XACT_NO_BACKOFF: false
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XACT_LOG_BUFFER_SIZE: 0
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XACT_STORE_PREDICTOR_HISTORY: 0
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XACT_STORE_PREDICTOR_ENTRIES: 0
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XACT_STORE_PREDICTOR_THRESHOLD: 0
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XACT_FIRST_ACCESS_COST: 0
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XACT_FIRST_PAGE_ACCESS_COST: 0
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ENABLE_MAGIC_WAITING: false
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ENABLE_WATCHPOINT: false
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XACT_ENABLE_VIRTUALIZATION_LOGTM_SE: false
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ATMTP_ENABLED: false
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ATMTP_ABORT_ON_NON_XACT_INST: false
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ATMTP_ALLOW_SAVE_RESTORE_IN_XACT: false
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ATMTP_XACT_MAX_STORES: 0
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ATMTP_DEBUG_LEVEL: 0
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XACT_LENGTH: 0
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XACT_SIZE: 0
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ABORT_RETRY_TIME: 0
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// Allowed parallelism in controllers
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L1CACHE_TRANSITIONS_PER_RUBY_CYCLE: 32
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L2CACHE_TRANSITIONS_PER_RUBY_CYCLE: 1000
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DIRECTORY_TRANSITIONS_PER_RUBY_CYCLE: 1000
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g_SEQUENCER_OUTSTANDING_REQUESTS: 16
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//TBEs == MSHRs (global)
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NUMBER_OF_TBES: 128
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NUMBER_OF_L1_TBES: 32
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// unused in CMP protocols
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NUMBER_OF_L2_TBES: 32
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// unused in CMP protocols
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// TSO & WBuffer params (unused)
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FINITE_BUFFERING: false
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FINITE_BUFFER_SIZE: 3
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PROCESSOR_BUFFER_SIZE: 10
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PROTOCOL_BUFFER_SIZE: 32
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TSO: false
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// General network params
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g_endpoint_bandwidth: 10000
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g_adaptive_routing: true
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NUMBER_OF_VIRTUAL_NETWORKS: 5
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FAN_OUT_DEGREE: 4
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// for HIERARCHICAL_SWITCH
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// Detailed Memory Controller Params (only used in _m protocols)
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MEM_BUS_CYCLE_MULTIPLIER: 5
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BANKS_PER_RANK: 8
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RANKS_PER_DIMM: 2
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DIMMS_PER_CHANNEL: 2
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BANK_BIT_0: 8
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RANK_BIT_0: 11
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DIMM_BIT_0: 12
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BANK_QUEUE_SIZE: 12
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BANK_BUSY_TIME: 22
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RANK_RANK_DELAY: 2
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READ_WRITE_DELAY: 3
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BASIC_BUS_BUSY_TIME: 3
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MEM_CTL_LATENCY: 20
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REFRESH_PERIOD: 3120
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TFAW: 0
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//flip a coin to delay requests by one cycle, introduces non-determinism
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MEM_RANDOM_ARBITRATE: 50
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MEM_FIXED_DELAY: 0
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//Configuration-specific parameters
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g_NUM_PROCESSORS: 1
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g_NUM_CHIPS: 1
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g_PROCS_PER_CHIP: 1
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g_NUM_L2_BANKS: 1
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g_NUM_MEMORIES: 4
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g_PRINT_TOPOLOGY: true
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g_GARNET_NETWORK: true
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g_DETAIL_NETWORK: true
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g_FLIT_SIZE: 8
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