2010-08-23 18:18:40 +02:00
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/*
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* Copyright (c) 2010 ARM Limited
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* All rights reserved
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Copyright (c) 2005 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Ali Saidi
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2010-10-01 23:04:00 +02:00
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* Prakash Ramrakhyani
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2010-08-23 18:18:40 +02:00
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*/
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#include "base/trace.hh"
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#include "cpu/intr_control.hh"
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#include "dev/arm/gic.hh"
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#include "dev/platform.hh"
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#include "dev/terminal.hh"
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#include "mem/packet.hh"
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#include "mem/packet_access.hh"
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Gic::Gic(const Params *p)
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: PioDevice(p),distAddr(p->dist_addr), cpuAddr(p->cpu_addr),
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distPioDelay(p->dist_pio_delay), cpuPioDelay(p->cpu_pio_delay),
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enabled(false), itLines(p->it_lines)
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{
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itLinesLog2 = ceilLog2(itLines);
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for (int x = 0; x < 8; x++) {
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cpuEnabled[x] = false;
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cpuPriority[x] = 0;
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cpuBpr[x] = 0;
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2010-10-01 23:04:00 +02:00
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// Initialize cpu highest int
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cpuHighestInt[x] = SPURIOUS_INT;
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2010-08-23 18:18:40 +02:00
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}
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for (int x = 0; x < 32; x++) {
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intEnabled[x] = 0;
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pendingInt[x] = 0;
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activeInt[x] = 0;
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}
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for (int x = 0; x < 1020; x++) {
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intPriority[x] = 0;
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cpuTarget[x] = 0;
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}
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for (int x = 0; x < 64; x++) {
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intConfig[x] = 0;
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}
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}
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Tick
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Gic::read(PacketPtr pkt)
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{
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Addr addr = pkt->getAddr();
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if (addr >= distAddr && addr < distAddr + DIST_SIZE)
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return readDistributor(pkt);
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else if (addr >= cpuAddr && addr < cpuAddr + CPU_SIZE)
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return readCpu(pkt);
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else
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panic("Read to unknown address %#x\n", pkt->getAddr());
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}
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Tick
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Gic::write(PacketPtr pkt)
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{
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Addr addr = pkt->getAddr();
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if (addr >= distAddr && addr < distAddr + DIST_SIZE)
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return writeDistributor(pkt);
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else if (addr >= cpuAddr && addr < cpuAddr + CPU_SIZE)
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return writeCpu(pkt);
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else
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panic("Write to unknown address %#x\n", pkt->getAddr());
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}
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Tick
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Gic::readDistributor(PacketPtr pkt)
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{
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Addr daddr = pkt->getAddr() - distAddr;
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pkt->allocate();
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DPRINTF(Interrupt, "gic distributor read register %#x\n", daddr);
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if (daddr >= ICDISER_ST && daddr < ICDISER_ED + 4) {
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assert((daddr-ICDISER_ST) >> 2 < 32);
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pkt->set<uint32_t>(intEnabled[(daddr-ICDISER_ST)>>2]);
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goto done;
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}
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if (daddr >= ICDICER_ST && daddr < ICDICER_ED + 4) {
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assert((daddr-ICDICER_ST) >> 2 < 32);
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pkt->set<uint32_t>(intEnabled[(daddr-ICDICER_ST)>>2]);
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goto done;
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}
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if (daddr >= ICDISPR_ST && daddr < ICDISPR_ED + 4) {
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assert((daddr-ICDISPR_ST) >> 2 < 32);
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pkt->set<uint32_t>(pendingInt[(daddr-ICDISPR_ST)>>2]);
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goto done;
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}
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if (daddr >= ICDICPR_ST && daddr < ICDICPR_ED + 4) {
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assert((daddr-ICDICPR_ST) >> 2 < 32);
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pkt->set<uint32_t>(pendingInt[(daddr-ICDICPR_ST)>>2]);
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goto done;
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}
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if (daddr >= ICDABR_ST && daddr < ICDABR_ED + 4) {
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assert((daddr-ICDABR_ST) >> 2 < 32);
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pkt->set<uint32_t>(activeInt[(daddr-ICDABR_ST)>>2]);
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goto done;
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}
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if (daddr >= ICDIPR_ST && daddr < ICDIPR_ED + 4) {
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Addr int_num;
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2010-10-01 23:04:00 +02:00
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int_num = daddr - ICDIPR_ST;
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2010-08-23 18:18:40 +02:00
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assert(int_num < 1020);
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2010-10-01 23:04:00 +02:00
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DPRINTF(Interrupt, "Reading interrupt priority at int# %#x \n",int_num);
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switch(pkt->getSize()){
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case 1:
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pkt->set<uint8_t>(intPriority[int_num]);
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break;
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case 2:
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pkt->set<uint16_t>(intPriority[int_num] |
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intPriority[int_num+1] << 8);
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break;
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case 4:
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pkt->set<uint32_t>(intPriority[int_num] |
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intPriority[int_num+1] << 8 |
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intPriority[int_num+2] << 16 |
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intPriority[int_num+3] << 24);
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break;
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default:
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panic("Invalid access size while reading, priority registers in Gic: %d", pkt->getSize());
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}
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2010-08-23 18:18:40 +02:00
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goto done;
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}
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if (daddr >= ICDIPTR_ST && daddr < ICDIPTR_ED + 4) {
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Addr int_num;
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int_num = (daddr-ICDIPTR_ST) << 2;
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assert(int_num < 1020);
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// First 31 interrupts only target single processor
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if (int_num > 31) {
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pkt->set<uint32_t>(cpuTarget[int_num] |
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cpuTarget[int_num+1] << 8 |
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cpuTarget[int_num+2] << 16 |
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cpuTarget[int_num+3] << 24) ;
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} else {
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/** @todo should be processor id */
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pkt->set<uint32_t>(0);
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}
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goto done;
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}
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if (daddr >= ICDICFR_ST && daddr < ICDICFR_ED + 4) {
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assert((daddr-ICDICFR_ST) >> 2 < 64);
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/** @todo software generated interrutps and PPIs
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* can't be configured in some ways
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*/
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pkt->set<uint32_t>(intConfig[(daddr-ICDICFR_ST)>>2]);
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goto done;
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}
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switch(daddr) {
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case ICDDCR:
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pkt->set<uint32_t>(enabled);
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break;
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case ICDICTR:
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/* @todo this needs to refelct the number of CPUs in the system */
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uint32_t tmp;
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tmp = 0 << 5 | // cpu number
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(itLines/32 -1);
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pkt->set<uint32_t>(tmp);
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break;
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default:
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panic("Tried to read Gic distributor at offset %#x\n", daddr);
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break;
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}
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done:
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pkt->makeAtomicResponse();
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return distPioDelay;
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}
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Tick
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Gic::readCpu(PacketPtr pkt)
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{
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Addr daddr = pkt->getAddr() - cpuAddr;
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pkt->allocate();
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DPRINTF(Interrupt, "gic cpu read register %#x\n", daddr);
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switch(daddr) {
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case ICCICR:
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pkt->set<uint32_t>(cpuEnabled[0]);
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break;
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case ICCPMR:
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pkt->set<uint32_t>(cpuPriority[0]);
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break;
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case ICCBPR:
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pkt->set<uint32_t>(cpuBpr[0]);
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break;
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case ICCIAR:
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DPRINTF(Interrupt, "CPU reading IAR = %d\n", cpuHighestInt[0]);
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2010-10-01 23:04:00 +02:00
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if(enabled && cpuEnabled[0]){
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pkt->set<uint32_t>(cpuHighestInt[0]);
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activeInt[intNumToWord(cpuHighestInt[0])] |=
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1 << intNumToBit(cpuHighestInt[0]);
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updateRunPri();
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pendingInt[intNumToWord(cpuHighestInt[0])] &=
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~(1 << intNumToBit(cpuHighestInt[0]));
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cpuHighestInt[0] = SPURIOUS_INT;
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updateIntState(-1);
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platform->intrctrl->clear(0, ArmISA::INT_IRQ, 0);
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} else {
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pkt->set<uint32_t>(SPURIOUS_INT);
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}
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2010-08-23 18:18:40 +02:00
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break;
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case ICCRPR:
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2010-10-01 23:04:00 +02:00
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pkt->set<uint32_t>(iccrpr[0]);
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2010-08-23 18:18:40 +02:00
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break;
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case ICCHPIR:
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pkt->set<uint32_t>(0);
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panic("Need to implement HPIR");
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break;
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default:
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panic("Tried to read Gic cpu at offset %#x\n", daddr);
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break;
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}
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pkt->makeAtomicResponse();
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return cpuPioDelay;
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}
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Tick
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Gic::writeDistributor(PacketPtr pkt)
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{
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Addr daddr = pkt->getAddr() - distAddr;
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pkt->allocate();
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2010-10-01 23:04:00 +02:00
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DPRINTF(Interrupt, "gic distributor write register %#x size %#x\n",
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daddr, pkt->getSize());
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2010-08-23 18:18:40 +02:00
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if (daddr >= ICDISER_ST && daddr < ICDISER_ED + 4) {
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assert((daddr-ICDISER_ST) >> 2 < 32);
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intEnabled[(daddr-ICDISER_ST)>>2] |= pkt->get<uint32_t>();
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goto done;
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}
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if (daddr >= ICDICER_ST && daddr < ICDICER_ED + 4) {
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assert((daddr-ICDICER_ST) >> 2 < 32);
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intEnabled[(daddr-ICDICER_ST)>>2] &= ~pkt->get<uint32_t>();
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goto done;
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}
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if (daddr >= ICDISPR_ST && daddr < ICDISPR_ED + 4) {
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assert((daddr-ICDISPR_ST) >> 2 < 32);
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pendingInt[(daddr-ICDISPR_ST)>>2] |= pkt->get<uint32_t>();
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updateIntState((daddr-ICDISPR_ST)>>2);
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goto done;
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}
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if (daddr >= ICDICPR_ST && daddr < ICDICPR_ED + 4) {
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assert((daddr-ICDICPR_ST) >> 2 < 32);
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pendingInt[(daddr-ICDICPR_ST)>>2] &= ~pkt->get<uint32_t>();
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updateIntState((daddr-ICDICPR_ST)>>2);
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goto done;
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}
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if (daddr >= ICDIPR_ST && daddr < ICDIPR_ED + 4) {
|
2010-10-01 23:04:00 +02:00
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Addr int_num = daddr - ICDIPR_ST;
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2010-08-23 18:18:40 +02:00
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assert(int_num < 1020);
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2010-10-01 23:04:00 +02:00
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uint32_t tmp;
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switch(pkt->getSize()){
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case 1:
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tmp = pkt->get<uint8_t>();
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intPriority[int_num] = tmp & 0xff;
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break;
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case 2:
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tmp = pkt->get<uint16_t>();
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intPriority[int_num] = tmp & 0xff;
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intPriority[int_num + 1] = (tmp >> 8) & 0xff;
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break;
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case 4:
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tmp = pkt->get<uint32_t>();
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intPriority[int_num] = tmp & 0xff;
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intPriority[int_num + 1] = (tmp >> 8) & 0xff;
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intPriority[int_num + 2] = (tmp >> 16) & 0xff;
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intPriority[int_num + 3] = (tmp >> 24) & 0xff;
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break;
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default:
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panic("Invalid access size while writing to, priority registers in Gic: %d", pkt->getSize());
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}
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updateIntState(-1);
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updateRunPri();
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2010-08-23 18:18:40 +02:00
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goto done;
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}
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if (daddr >= ICDIPTR_ST && daddr < ICDIPTR_ED + 4) {
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Addr int_num = (daddr-ICDIPTR_ST) << 2;
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assert(int_num < 1020);
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// First 31 interrupts only target single processor
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if (int_num > 31) {
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uint32_t tmp = pkt->get<uint32_t>();
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cpuTarget[int_num] = tmp & 0xff;
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cpuTarget[int_num+1] = (tmp >> 8) & 0xff;
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cpuTarget[int_num+2] = (tmp >> 16) & 0xff;
|
|
|
|
cpuTarget[int_num+3] = (tmp >> 24) & 0xff;
|
|
|
|
updateIntState((daddr-ICDIPTR_ST)>>2);
|
|
|
|
}
|
|
|
|
goto done;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (daddr >= ICDICFR_ST && daddr < ICDICFR_ED + 4) {
|
|
|
|
assert((daddr-ICDICFR_ST) >> 2 < 64);
|
|
|
|
intConfig[(daddr-ICDICFR_ST)>>2] = pkt->get<uint32_t>();
|
|
|
|
goto done;
|
|
|
|
}
|
|
|
|
|
|
|
|
switch(daddr) {
|
|
|
|
case ICDDCR:
|
|
|
|
enabled = pkt->get<uint32_t>();
|
2010-10-01 23:04:00 +02:00
|
|
|
DPRINTF(Interrupt, "Distributor enable flag set to = %d\n", enabled);
|
2010-08-23 18:18:40 +02:00
|
|
|
break;
|
|
|
|
case ICDSGIR:
|
|
|
|
softInt(pkt->get<uint32_t>());
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
panic("Tried to write Gic distributor at offset %#x\n", daddr);
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
done:
|
|
|
|
pkt->makeAtomicResponse();
|
|
|
|
return distPioDelay;
|
|
|
|
}
|
|
|
|
|
|
|
|
Tick
|
|
|
|
Gic::writeCpu(PacketPtr pkt)
|
|
|
|
{
|
|
|
|
Addr daddr = pkt->getAddr() - cpuAddr;
|
|
|
|
pkt->allocate();
|
|
|
|
|
|
|
|
DPRINTF(Interrupt, "gic cpu write register %#x val: %#x\n",
|
|
|
|
daddr, pkt->get<uint32_t>());
|
|
|
|
|
|
|
|
switch(daddr) {
|
|
|
|
case ICCICR:
|
|
|
|
cpuEnabled[0] = pkt->get<uint32_t>();
|
|
|
|
updateIntState(-1);
|
|
|
|
break;
|
|
|
|
case ICCPMR:
|
|
|
|
cpuPriority[0] = pkt->get<uint32_t>();
|
|
|
|
updateIntState(-1);
|
|
|
|
break;
|
|
|
|
case ICCBPR:
|
|
|
|
cpuBpr[0] = pkt->get<uint32_t>();
|
|
|
|
updateIntState(-1);
|
|
|
|
break;
|
|
|
|
case ICCEOIR:
|
|
|
|
uint32_t tmp;
|
|
|
|
tmp = pkt->get<uint32_t>();
|
|
|
|
if (!(activeInt[intNumToWord(tmp)] & (1 << intNumToBit(tmp))))
|
|
|
|
panic("Done handling interrupt that isn't active?\n");
|
|
|
|
activeInt[intNumToWord(tmp)] &= ~(1 << intNumToBit(tmp));
|
2010-10-01 23:04:00 +02:00
|
|
|
updateRunPri();
|
2010-08-23 18:18:40 +02:00
|
|
|
DPRINTF(Interrupt, "CPU done handling interrupt IAR = %d\n", tmp);
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
panic("Tried to write Gic cpu at offset %#x\n", daddr);
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
pkt->makeAtomicResponse();
|
|
|
|
return cpuPioDelay;
|
|
|
|
}
|
|
|
|
|
|
|
|
void
|
|
|
|
Gic::softInt(SWI swi)
|
|
|
|
{
|
|
|
|
warn("Should be causing software interrupt");
|
|
|
|
}
|
|
|
|
|
|
|
|
void
|
|
|
|
Gic::updateIntState(int hint)
|
|
|
|
{
|
|
|
|
/*@todo use hint to do less work. */
|
2010-10-01 23:04:00 +02:00
|
|
|
int highest_int = SPURIOUS_INT;
|
|
|
|
// Priorities below that set in ICCPMR can be ignored
|
|
|
|
uint8_t highest_pri = cpuPriority[0];
|
2010-08-23 18:18:40 +02:00
|
|
|
|
2010-10-01 23:04:00 +02:00
|
|
|
for (int x = 0; x < (itLines/32) ; x++) {
|
2010-08-23 18:18:40 +02:00
|
|
|
if (intEnabled[x] & pendingInt[x]) {
|
|
|
|
for (int y = 0; y < 32; y++) {
|
|
|
|
if (bits(intEnabled[x], y) & bits(pendingInt[x], y))
|
|
|
|
if (intPriority[x*32+y] < highest_pri) {
|
|
|
|
highest_pri = intPriority[x*32+y];
|
|
|
|
highest_int = x*32 + y;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2010-10-01 23:04:00 +02:00
|
|
|
if (highest_int == SPURIOUS_INT)
|
2010-08-23 18:18:40 +02:00
|
|
|
return;
|
|
|
|
|
|
|
|
cpuHighestInt[0] = highest_int;
|
|
|
|
|
|
|
|
|
|
|
|
/* @todo make this work for more than one cpu, need to handle 1:N, N:N
|
|
|
|
* models */
|
2010-10-01 23:04:00 +02:00
|
|
|
if (enabled && cpuEnabled[0] && (highest_pri < cpuPriority[0])) {
|
2010-08-23 18:18:40 +02:00
|
|
|
/* @todo delay interrupt by some time to deal with calculation delay */
|
|
|
|
/* @todo only interrupt if we've haven't already interrupted for this
|
|
|
|
* int !!!!!!!!!! */
|
|
|
|
DPRINTF(Interrupt, "Posting interrupt %d to cpu0\n", highest_int);
|
|
|
|
platform->intrctrl->post(0, ArmISA::INT_IRQ, 0);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2010-10-01 23:04:00 +02:00
|
|
|
void
|
|
|
|
Gic::updateRunPri()
|
|
|
|
{
|
|
|
|
uint8_t maxPriority = 0xff;
|
|
|
|
for (int i = 0 ; i < itLines ; i++){
|
|
|
|
if ( activeInt[intNumToWord(i)] & (1 << intNumToBit(i))){
|
|
|
|
if (intPriority[i] < maxPriority) maxPriority = intPriority[i];
|
|
|
|
}
|
|
|
|
}
|
|
|
|
iccrpr[0] = maxPriority;
|
|
|
|
}
|
2010-08-23 18:18:40 +02:00
|
|
|
void
|
|
|
|
Gic::sendInt(uint32_t num)
|
|
|
|
{
|
|
|
|
DPRINTF(Interrupt, "Received Interupt number %d\n", num);
|
|
|
|
pendingInt[intNumToWord(num)] |= 1 << intNumToBit(num);
|
|
|
|
updateIntState(intNumToWord(num));
|
|
|
|
|
|
|
|
}
|
|
|
|
|
|
|
|
void
|
|
|
|
Gic::clearInt(uint32_t number)
|
|
|
|
{
|
|
|
|
/* @todo assume edge triggered only at the moment. Nothing to do. */
|
|
|
|
}
|
|
|
|
|
|
|
|
void
|
|
|
|
Gic::addressRanges(AddrRangeList &range_list)
|
|
|
|
{
|
|
|
|
range_list.clear();
|
|
|
|
range_list.push_back(RangeSize(distAddr, DIST_SIZE));
|
|
|
|
range_list.push_back(RangeSize(cpuAddr, CPU_SIZE));
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
void
|
|
|
|
Gic::serialize(std::ostream &os)
|
|
|
|
{
|
|
|
|
panic("Need to implement serialization\n");
|
|
|
|
}
|
|
|
|
|
|
|
|
void
|
|
|
|
Gic::unserialize(Checkpoint *cp, const std::string §ion)
|
|
|
|
{
|
|
|
|
panic("Need to implement serialization\n");
|
|
|
|
}
|
|
|
|
|
|
|
|
Gic *
|
|
|
|
GicParams::create()
|
|
|
|
{
|
|
|
|
return new Gic(this);
|
|
|
|
}
|
2010-10-01 23:04:00 +02:00
|
|
|
|
|
|
|
/* Functions for debugging and testing */
|
|
|
|
void
|
|
|
|
Gic::driveSPI(unsigned int spiVect)
|
|
|
|
{
|
|
|
|
DPRINTF(GIC, "Received SPI Vector:%x Enable: %d\n", spiVect, irqEnable);
|
|
|
|
if( irqEnable && enabled ){
|
|
|
|
pendingInt[1] |= spiVect;
|
|
|
|
updateIntState(-1);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
void
|
|
|
|
Gic::driveIrqEn( bool state)
|
|
|
|
{
|
|
|
|
irqEnable = state;
|
|
|
|
}
|
|
|
|
|
|
|
|
void
|
|
|
|
Gic::driveLegIRQ(bool state)
|
|
|
|
{
|
|
|
|
if (irqEnable && !(!enabled && cpuEnabled[0])){
|
|
|
|
if(state){
|
|
|
|
DPRINTF(GIC, "Driving Legacy Irq\n");
|
|
|
|
platform->intrctrl->post(0, ArmISA::INT_IRQ, 0);
|
|
|
|
}
|
|
|
|
else platform->intrctrl->clear(0, ArmISA::INT_IRQ, 0);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
void
|
|
|
|
Gic::driveLegFIQ(bool state)
|
|
|
|
{
|
|
|
|
if (state)
|
|
|
|
platform->intrctrl->post(0, ArmISA::INT_FIQ, 0);
|
|
|
|
else platform->intrctrl->clear(0, ArmISA::INT_FIQ, 0);
|
|
|
|
}
|