2015-06-01 20:44:17 +02:00
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/*
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2016-04-27 16:34:31 +02:00
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* Copyright (c) 2015-2016 ARM Limited
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2015-06-01 20:44:17 +02:00
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* All rights reserved
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Andreas Sandberg
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*/
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#ifndef __ARCH_ARM_KVM_GIC_HH__
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#define __ARCH_ARM_KVM_GIC_HH__
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#include "arch/arm/system.hh"
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#include "cpu/kvm/device.hh"
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#include "cpu/kvm/vm.hh"
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#include "dev/arm/base_gic.hh"
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#include "dev/platform.hh"
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2016-04-27 16:34:31 +02:00
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/**
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* KVM in-kernel GIC abstraction
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*
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* This class defines a high-level interface to the KVM in-kernel GIC
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* model. It exposes an API that is similar to that of
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* software-emulated GIC models in gem5.
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*/
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class KvmKernelGicV2
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{
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public:
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/**
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* Instantiate a KVM in-kernel GIC model.
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*
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* This constructor instantiates an in-kernel GIC model and wires
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* it up to the virtual memory system.
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*
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* @param vm KVM VM representing this system
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* @param cpu_addr GIC CPU interface base address
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* @param dist_addr GIC distributor base address
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2017-02-14 22:09:18 +01:00
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* @param it_lines Number of interrupt lines to support
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2016-04-27 16:34:31 +02:00
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*/
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2016-04-27 16:34:48 +02:00
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KvmKernelGicV2(KvmVM &vm, Addr cpu_addr, Addr dist_addr,
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unsigned it_lines);
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2016-04-27 16:34:31 +02:00
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virtual ~KvmKernelGicV2();
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KvmKernelGicV2(const KvmKernelGicV2 &other) = delete;
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KvmKernelGicV2(const KvmKernelGicV2 &&other) = delete;
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KvmKernelGicV2 &operator=(const KvmKernelGicV2 &&rhs) = delete;
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KvmKernelGicV2 &operator=(const KvmKernelGicV2 &rhs) = delete;
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public:
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/**
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* @{
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* @name In-kernel GIC API
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*/
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/**
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* Raise a shared peripheral interrupt
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*
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* @param spi SPI number
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*/
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void setSPI(unsigned spi);
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/**
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* Clear a shared peripheral interrupt
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*
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* @param spi SPI number
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*/
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void clearSPI(unsigned spi);
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/**
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* Raise a private peripheral interrupt
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*
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* @param vcpu KVM virtual CPU number
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* @parma ppi PPI interrupt number
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*/
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void setPPI(unsigned vcpu, unsigned ppi);
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/**
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* Clear a private peripheral interrupt
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*
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* @param vcpu KVM virtual CPU number
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* @parma ppi PPI interrupt number
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*/
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void clearPPI(unsigned vcpu, unsigned ppi);
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/** Address range for the CPU interfaces */
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const AddrRange cpuRange;
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/** Address range for the distributor interface */
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const AddrRange distRange;
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/* @} */
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protected:
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/**
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* Update the kernel's VGIC interrupt state
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*
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* @param type Interrupt type (KVM_ARM_IRQ_TYPE_PPI/KVM_ARM_IRQ_TYPE_SPI)
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* @param vcpu CPU id within KVM (ignored for SPIs)
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* @param irq Interrupt number
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* @param high True to signal an interrupt, false to clear it.
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*/
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void setIntState(unsigned type, unsigned vcpu, unsigned irq, bool high);
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/** KVM VM in the parent system */
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KvmVM &vm;
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/** Kernel interface to the GIC */
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KvmDevice kdev;
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};
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struct KvmGicParams;
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2015-06-01 20:44:17 +02:00
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/**
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* In-kernel GIC model.
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*
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* When using a KVM-based CPU model, it is possible to offload GIC
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* emulation to the kernel. This reduces some overheads when the guest
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* accesses the GIC and makes it possible to use in-kernel
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* architected/generic timer emulation.
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*
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* This device uses interfaces with the kernel GicV2 model that is
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* documented in Documentation/virtual/kvm/devices/arm-vgic.txt in the
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* Linux kernel sources.
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*
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* This GIC model has the following known limitations:
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* <ul>
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* <li>Checkpointing is not supported.
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* <li>This model only works with kvm. Simulated CPUs are not
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* supported since this would require the kernel to inject
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* interrupt into the simulated CPU.
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* </ul>
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*
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* @warn This GIC model cannot be used with simulated CPUs!
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*/
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class KvmGic : public BaseGic
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{
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public: // SimObject / Serializable / Drainable
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KvmGic(const KvmGicParams *p);
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~KvmGic();
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2015-10-12 10:07:59 +02:00
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void startup() override { verifyMemoryMode(); }
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void drainResume() override { verifyMemoryMode(); }
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2015-06-01 20:44:17 +02:00
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2015-10-12 10:07:59 +02:00
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void serialize(CheckpointOut &cp) const override;
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2016-04-27 16:34:31 +02:00
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void unserialize(CheckpointIn &cp) override;
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2015-06-01 20:44:17 +02:00
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public: // PioDevice
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AddrRangeList getAddrRanges() const { return addrRanges; }
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2015-10-12 10:07:59 +02:00
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Tick read(PacketPtr pkt) override;
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Tick write(PacketPtr pkt) override;
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2015-06-01 20:44:17 +02:00
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public: // BaseGic
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2015-10-12 10:07:59 +02:00
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void sendInt(uint32_t num) override;
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void clearInt(uint32_t num) override;
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2015-06-01 20:44:17 +02:00
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2015-10-12 10:07:59 +02:00
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void sendPPInt(uint32_t num, uint32_t cpu) override;
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void clearPPInt(uint32_t num, uint32_t cpu) override;
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2015-06-01 20:44:17 +02:00
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protected:
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/**
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* Do memory mode sanity checks
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*
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* This method only really exists to warn users that try to switch
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* to a simulate CPU. There is no fool proof method to detect
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* simulated CPUs, but checking that we're in atomic mode and
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* bypassing caches should be robust enough.
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*/
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void verifyMemoryMode() const;
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/** System this interrupt controller belongs to */
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System &system;
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2016-04-27 16:34:31 +02:00
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/** Kernel GIC device */
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KvmKernelGicV2 kernelGic;
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2015-06-01 20:44:17 +02:00
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/** Union of all memory */
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const AddrRangeList addrRanges;
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};
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#endif // __ARCH_ARM_KVM_GIC_HH__
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