gem5/src/mem/protocol/MOESI_CMP_directory.slicc

MOESI_CMP_directory-msg.sm
MOESI_CMP_directory-L2cache.sm
MOESI_CMP_directory-L1cache.sm
MOESI_CMP_directory-dma.sm
MOESI_CMP_directory-dir.sm
standard_CMP-protocol.sm
ruby: Import ruby and slicc from GEMS We eventually plan to replace the m5 cache hierarchy with the GEMS hierarchy, but for now we will make both live alongside eachother. 2009-05-11 19:38:43 +02:00			`MOESI_CMP_directory-msg.sm`
			`MOESI_CMP_directory-L2cache.sm`
			`MOESI_CMP_directory-L1cache.sm`
slicc: added MOESI_CMP_directory, DMA SequencerMsg, parameterized controllers This changeset contains a lot of different changes that are too mingled to separate. They are: 1. Added MOESI_CMP_directory I made the changes necessary to bring back MOESI_CMP_directory, including adding a DMA controller. I got rid of MOESI_CMP_directory_m and made MOESI_CMP_directory use a memory controller. Added a new configuration for two level protocols in general, and MOESI_CMP_directory in particular. 2. DMA Sequencer uses a generic SequencerMsg I will eventually make the cache Sequencer use this type as well. It doesn't contain an offset field, just a physical address and a length. MI_example has been updated to deal with this. 3. Parameterized Controllers SLICC controllers can now take custom parameters to use for mapping, latencies, etc. Currently, only int parameters are supported. 2009-08-04 19:52:52 +02:00			`MOESI_CMP_directory-dma.sm`
ruby: Import ruby and slicc from GEMS We eventually plan to replace the m5 cache hierarchy with the GEMS hierarchy, but for now we will make both live alongside eachother. 2009-05-11 19:38:43 +02:00			`MOESI_CMP_directory-dir.sm`
			`standard_CMP-protocol.sm`