2016-01-19 20:28:22 +01:00
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/*
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* Copyright (c) 2011-2015 Advanced Micro Devices, Inc.
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* All rights reserved.
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*
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* For use for simulation and test purposes only
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* 3. Neither the name of the copyright holder nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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* Author: Steve Reinhardt
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*/
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#ifndef __SHADER_HH__
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#define __SHADER_HH__
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#include <functional>
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#include <string>
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#include "arch/isa.hh"
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#include "arch/isa_traits.hh"
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#include "base/types.hh"
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#include "cpu/simple/atomic.hh"
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#include "cpu/simple/timing.hh"
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#include "cpu/simple_thread.hh"
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#include "cpu/thread_context.hh"
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#include "cpu/thread_state.hh"
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#include "enums/MemType.hh"
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#include "gpu-compute/compute_unit.hh"
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#include "gpu-compute/gpu_tlb.hh"
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#include "gpu-compute/lds_state.hh"
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#include "gpu-compute/qstruct.hh"
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#include "mem/page_table.hh"
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#include "mem/port.hh"
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#include "mem/request.hh"
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#include "params/Shader.hh"
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#include "sim/faults.hh"
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#include "sim/process.hh"
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#include "sim/sim_object.hh"
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class BaseTLB;
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class GpuDispatcher;
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namespace TheISA
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{
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class GpuTLB;
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}
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static const int LDS_SIZE = 65536;
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// Class Shader: This describes a single shader instance. Most
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// configurations will only have a single shader.
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class Shader : public SimObject
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{
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protected:
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// Shader's clock period in terms of number of ticks of curTime,
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// aka global simulation clock
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Tick clock;
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public:
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typedef ShaderParams Params;
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enum hsail_mode_e {SIMT,VECTOR_SCALAR};
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// clock related functions ; maps to-and-from
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// Simulation ticks and shader clocks.
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Tick frequency() const { return SimClock::Frequency / clock; }
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Tick ticks(int numCycles) const { return (Tick)clock * numCycles; }
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Tick getClock() const { return clock; }
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Tick curCycle() const { return curTick() / clock; }
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Tick tickToCycles(Tick val) const { return val / clock;}
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SimpleThread *cpuThread;
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ThreadContext *gpuTc;
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BaseCPU *cpuPointer;
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class TickEvent : public Event
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{
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private:
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Shader *shader;
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public:
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TickEvent(Shader*);
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void process();
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const char* description() const;
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};
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TickEvent tickEvent;
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// is this simulation going to be timing mode in the memory?
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bool timingSim;
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hsail_mode_e hsail_mode;
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// If set, issue acq packet @ kernel launch
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int impl_kern_boundary_sync;
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// If set, generate a separate packet for acquire/release on
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// ld_acquire/st_release/atomic operations
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int separate_acquire_release;
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// If set, fetch returns may be coissued with instructions
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int coissue_return;
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// If set, always dump all 64 gprs to trace
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int trace_vgpr_all;
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// Number of cu units in the shader
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int n_cu;
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// Number of wavefront slots per cu
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int n_wf;
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// The size of global memory
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int globalMemSize;
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/*
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* Bytes/work-item for call instruction
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* The number of arguments for an hsail function will
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* vary. We simply determine the maximum # of arguments
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* required by any hsail function up front before the
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* simulation (during parsing of the Brig) and record
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* that number here.
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*/
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int funcargs_size;
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// Tracks CU that rr dispatcher should attempt scheduling
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int nextSchedCu;
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// Size of scheduled add queue
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uint32_t sa_n;
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// Pointer to value to be increments
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std::vector<uint32_t*> sa_val;
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// When to do the increment
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std::vector<uint64_t> sa_when;
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// Amount to increment by
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std::vector<int32_t> sa_x;
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// List of Compute Units (CU's)
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std::vector<ComputeUnit*> cuList;
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uint64_t tick_cnt;
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uint64_t box_tick_cnt;
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uint64_t start_tick_cnt;
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GpuDispatcher *dispatcher;
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Shader(const Params *p);
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~Shader();
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virtual void init();
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// Run shader
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void exec();
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// Check to see if shader is busy
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bool busy();
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// Schedule a 32-bit value to be incremented some time in the future
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void ScheduleAdd(uint32_t *val, Tick when, int x);
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bool processTimingPacket(PacketPtr pkt);
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void AccessMem(uint64_t address, void *ptr, uint32_t size, int cu_id,
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MemCmd cmd, bool suppress_func_errors);
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void ReadMem(uint64_t address, void *ptr, uint32_t sz, int cu_id);
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void ReadMem(uint64_t address, void *ptr, uint32_t sz, int cu_id,
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bool suppress_func_errors);
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void WriteMem(uint64_t address, void *ptr, uint32_t sz, int cu_id);
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void WriteMem(uint64_t address, void *ptr, uint32_t sz, int cu_id,
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bool suppress_func_errors);
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void doFunctionalAccess(RequestPtr req, MemCmd cmd, void *data,
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bool suppress_func_errors, int cu_id);
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void
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registerCU(int cu_id, ComputeUnit *compute_unit)
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{
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cuList[cu_id] = compute_unit;
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}
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void handshake(GpuDispatcher *dispatcher);
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bool dispatch_workgroups(NDRange *ndr);
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Addr mmap(int length);
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void functionalTLBAccess(PacketPtr pkt, int cu_id, BaseTLB::Mode mode);
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2016-04-07 16:30:20 +02:00
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void updateContext(int cid);
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2016-01-19 20:28:22 +01:00
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void hostWakeUp(BaseCPU *cpu);
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};
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#endif // __SHADER_HH__
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