2007-10-03 08:00:37 +02:00
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/*
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2010-05-24 07:44:15 +02:00
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* Copyright (c) 2007 The Hewlett-Packard Development Company
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* All rights reserved.
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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2007-10-03 08:00:37 +02:00
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* Copyright (c) 2003-2007 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Gabe Black
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*/
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2008-10-13 07:42:10 +02:00
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#include "arch/x86/decoder.hh"
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2007-10-03 08:00:37 +02:00
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#include "arch/x86/faults.hh"
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#include "base/trace.hh"
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#include "config/full_system.hh"
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#include "cpu/thread_context.hh"
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#if !FULL_SYSTEM
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#include "arch/x86/isa_traits.hh"
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#include "mem/page_table.hh"
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#include "sim/process.hh"
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2007-11-12 23:38:31 +01:00
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#else
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#include "arch/x86/tlb.hh"
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2007-10-03 08:00:37 +02:00
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#endif
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namespace X86ISA
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{
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#if FULL_SYSTEM
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2010-09-14 04:26:03 +02:00
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void X86FaultBase::invoke(ThreadContext * tc, StaticInstPtr inst)
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2007-10-03 08:00:37 +02:00
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{
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2009-02-25 19:17:59 +01:00
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Addr pc = tc->readPC();
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DPRINTF(Faults, "RIP %#x: vector %d: %s\n", pc, vector, describe());
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2008-10-13 07:42:10 +02:00
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using namespace X86ISAInst::RomLabels;
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HandyM5Reg m5reg = tc->readMiscRegNoEffect(MISCREG_M5_REG);
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MicroPC entry;
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if (m5reg.mode == LongMode) {
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2009-02-02 02:09:08 +01:00
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if (isSoft()) {
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entry = extern_label_longModeSoftInterrupt;
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} else {
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entry = extern_label_longModeInterrupt;
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}
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2008-10-13 07:42:10 +02:00
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} else {
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entry = extern_label_legacyModeInterrupt;
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}
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tc->setIntReg(INTREG_MICRO(1), vector);
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2009-02-25 19:17:59 +01:00
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tc->setIntReg(INTREG_MICRO(7), pc);
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2009-02-02 02:08:32 +01:00
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if (errorCode != (uint64_t)(-1)) {
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2009-02-02 02:09:08 +01:00
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if (m5reg.mode == LongMode) {
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entry = extern_label_longModeInterruptWithError;
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} else {
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panic("Legacy mode interrupts with error codes "
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"aren't implementde.\n");
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}
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// Software interrupts shouldn't have error codes. If one does,
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// there would need to be microcode to set it up.
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assert(!isSoft());
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2009-02-02 02:08:32 +01:00
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tc->setIntReg(INTREG_MICRO(15), errorCode);
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}
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2008-10-13 07:42:10 +02:00
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tc->setMicroPC(romMicroPC(entry));
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tc->setNextMicroPC(romMicroPC(entry) + 1);
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2007-10-03 08:00:37 +02:00
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}
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2009-02-25 19:17:59 +01:00
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std::string
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X86FaultBase::describe() const
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{
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std::stringstream ss;
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ccprintf(ss, "%s", mnemonic());
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if (errorCode != (uint64_t)(-1)) {
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ccprintf(ss, "(%#x)", errorCode);
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}
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return ss.str();
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}
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2009-02-02 02:09:08 +01:00
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2010-09-14 04:26:03 +02:00
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void X86Trap::invoke(ThreadContext * tc, StaticInstPtr inst)
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2009-02-02 02:09:08 +01:00
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{
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X86FaultBase::invoke(tc);
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// This is the same as a fault, but it happens -after- the instruction.
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tc->setPC(tc->readNextPC());
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tc->setNextPC(tc->readNextNPC());
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tc->setNextNPC(tc->readNextNPC() + sizeof(MachInst));
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}
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2010-09-14 04:26:03 +02:00
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void X86Abort::invoke(ThreadContext * tc, StaticInstPtr inst)
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2009-02-02 02:09:08 +01:00
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{
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panic("Abort exception!");
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}
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2010-09-14 04:26:03 +02:00
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void PageFault::invoke(ThreadContext * tc, StaticInstPtr inst)
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2009-02-02 02:09:08 +01:00
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{
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HandyM5Reg m5reg = tc->readMiscRegNoEffect(MISCREG_M5_REG);
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X86FaultBase::invoke(tc);
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/*
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* If something bad happens while trying to enter the page fault
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* handler, I'm pretty sure that's a double fault and then all bets are
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* off. That means it should be safe to update this state now.
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*/
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if (m5reg.mode == LongMode) {
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tc->setMiscReg(MISCREG_CR2, addr);
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} else {
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tc->setMiscReg(MISCREG_CR2, (uint32_t)addr);
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}
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}
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2007-11-12 23:38:31 +01:00
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2009-02-25 19:17:59 +01:00
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std::string
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PageFault::describe() const
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{
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std::stringstream ss;
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ccprintf(ss, "%s at %#x", X86FaultBase::describe(), addr);
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return ss.str();
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}
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2009-04-19 11:53:00 +02:00
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void
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2010-09-14 04:26:03 +02:00
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InitInterrupt::invoke(ThreadContext *tc, StaticInstPtr inst)
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2009-04-19 11:53:00 +02:00
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{
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DPRINTF(Faults, "Init interrupt.\n");
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// The otherwise unmodified integer registers should be set to 0.
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for (int index = 0; index < NUM_INTREGS; index++) {
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tc->setIntReg(index, 0);
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}
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CR0 cr0 = tc->readMiscReg(MISCREG_CR0);
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CR0 newCR0 = 1 << 4;
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newCR0.cd = cr0.cd;
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newCR0.nw = cr0.nw;
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tc->setMiscReg(MISCREG_CR0, newCR0);
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tc->setMiscReg(MISCREG_CR2, 0);
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tc->setMiscReg(MISCREG_CR3, 0);
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tc->setMiscReg(MISCREG_CR4, 0);
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tc->setMiscReg(MISCREG_RFLAGS, 0x0000000000000002ULL);
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tc->setMiscReg(MISCREG_EFER, 0);
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SegAttr dataAttr = 0;
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2009-05-29 08:27:56 +02:00
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dataAttr.dpl = 0;
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dataAttr.unusable = 0;
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dataAttr.defaultSize = 0;
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dataAttr.longMode = 0;
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dataAttr.avl = 0;
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dataAttr.granularity = 0;
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dataAttr.present = 1;
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dataAttr.type = 3;
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2009-04-19 11:53:00 +02:00
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dataAttr.writable = 1;
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dataAttr.readable = 1;
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dataAttr.expandDown = 0;
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2009-05-29 08:27:56 +02:00
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dataAttr.system = 1;
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2009-04-19 11:53:00 +02:00
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for (int seg = 0; seg != NUM_SEGMENTREGS; seg++) {
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tc->setMiscReg(MISCREG_SEG_SEL(seg), 0);
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tc->setMiscReg(MISCREG_SEG_BASE(seg), 0);
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tc->setMiscReg(MISCREG_SEG_EFF_BASE(seg), 0);
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tc->setMiscReg(MISCREG_SEG_LIMIT(seg), 0xffff);
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tc->setMiscReg(MISCREG_SEG_ATTR(seg), dataAttr);
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}
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SegAttr codeAttr = 0;
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2009-05-29 08:27:56 +02:00
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codeAttr.dpl = 0;
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codeAttr.unusable = 0;
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codeAttr.defaultSize = 0;
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codeAttr.longMode = 0;
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codeAttr.avl = 0;
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codeAttr.granularity = 0;
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codeAttr.present = 1;
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codeAttr.type = 10;
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2009-04-19 11:53:00 +02:00
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codeAttr.writable = 0;
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codeAttr.readable = 1;
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codeAttr.expandDown = 0;
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2009-05-29 08:27:56 +02:00
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codeAttr.system = 1;
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2009-04-19 11:53:00 +02:00
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tc->setMiscReg(MISCREG_CS, 0xf000);
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tc->setMiscReg(MISCREG_CS_BASE,
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0x00000000ffff0000ULL);
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tc->setMiscReg(MISCREG_CS_EFF_BASE,
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0x00000000ffff0000ULL);
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// This has the base value pre-added.
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tc->setMiscReg(MISCREG_CS_LIMIT, 0xffffffff);
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tc->setMiscReg(MISCREG_CS_ATTR, codeAttr);
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tc->setPC(0x000000000000fff0ULL +
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tc->readMiscReg(MISCREG_CS_BASE));
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tc->setNextPC(tc->readPC() + sizeof(MachInst));
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tc->setMiscReg(MISCREG_TSG_BASE, 0);
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tc->setMiscReg(MISCREG_TSG_LIMIT, 0xffff);
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tc->setMiscReg(MISCREG_IDTR_BASE, 0);
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tc->setMiscReg(MISCREG_IDTR_LIMIT, 0xffff);
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tc->setMiscReg(MISCREG_TSL, 0);
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tc->setMiscReg(MISCREG_TSL_BASE, 0);
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tc->setMiscReg(MISCREG_TSL_LIMIT, 0xffff);
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tc->setMiscReg(MISCREG_TSL_ATTR, 0);
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tc->setMiscReg(MISCREG_TR, 0);
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tc->setMiscReg(MISCREG_TR_BASE, 0);
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tc->setMiscReg(MISCREG_TR_LIMIT, 0xffff);
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tc->setMiscReg(MISCREG_TR_ATTR, 0);
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// This value should be the family/model/stepping of the processor.
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// (page 418). It should be consistent with the value from CPUID, but
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// the actual value probably doesn't matter much.
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tc->setIntReg(INTREG_RDX, 0);
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tc->setMiscReg(MISCREG_DR0, 0);
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tc->setMiscReg(MISCREG_DR1, 0);
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tc->setMiscReg(MISCREG_DR2, 0);
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tc->setMiscReg(MISCREG_DR3, 0);
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tc->setMiscReg(MISCREG_DR6, 0x00000000ffff0ff0ULL);
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tc->setMiscReg(MISCREG_DR7, 0x0000000000000400ULL);
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2009-04-27 01:47:48 +02:00
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// Update the handy M5 Reg.
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tc->setMiscReg(MISCREG_M5_REG, 0);
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2009-04-19 11:53:00 +02:00
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MicroPC entry = X86ISAInst::RomLabels::extern_label_initIntHalt;
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tc->setMicroPC(romMicroPC(entry));
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tc->setNextMicroPC(romMicroPC(entry) + 1);
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}
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2009-04-19 11:56:03 +02:00
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void
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2010-09-14 04:26:03 +02:00
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StartupInterrupt::invoke(ThreadContext *tc, StaticInstPtr inst)
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2009-04-19 11:56:03 +02:00
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{
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DPRINTF(Faults, "Startup interrupt with vector %#x.\n", vector);
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HandyM5Reg m5Reg = tc->readMiscReg(MISCREG_M5_REG);
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if (m5Reg.mode != LegacyMode || m5Reg.submode != RealMode) {
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panic("Startup IPI recived outside of real mode. "
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2009-04-27 01:47:48 +02:00
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"Don't know what to do. %d, %d", m5Reg.mode, m5Reg.submode);
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2009-04-19 11:56:03 +02:00
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}
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tc->setMiscReg(MISCREG_CS, vector << 8);
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tc->setMiscReg(MISCREG_CS_BASE, vector << 12);
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tc->setMiscReg(MISCREG_CS_EFF_BASE, vector << 12);
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// This has the base value pre-added.
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tc->setMiscReg(MISCREG_CS_LIMIT, 0xffff);
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tc->setPC(tc->readMiscReg(MISCREG_CS_BASE));
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tc->setNextPC(tc->readPC() + sizeof(MachInst));
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}
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2010-08-23 18:44:19 +02:00
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#else
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2010-09-14 21:27:30 +02:00
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void
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InvalidOpcode::invoke(ThreadContext * tc, StaticInstPtr inst)
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{
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panic("Unrecognized/invalid instruction executed:\n %s",
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inst->machInst);
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}
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2010-08-23 18:44:19 +02:00
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void
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2010-09-14 04:26:03 +02:00
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PageFault::invoke(ThreadContext * tc, StaticInstPtr inst)
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2010-08-23 18:44:19 +02:00
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{
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PageFaultErrorCode code = errorCode;
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const char *modeStr = "";
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if (code.fetch)
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modeStr = "execute";
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else if (code.write)
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modeStr = "write";
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else
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modeStr = "read";
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panic("Tried to %s unmapped address %#x.\n", modeStr, addr);
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}
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2007-10-03 08:00:37 +02:00
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#endif
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} // namespace X86ISA
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