2011-06-20 03:43:43 +02:00
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---------- Begin Simulation Statistics ----------
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2011-06-20 03:54:53 +02:00
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sim_seconds 0.140230 # Number of seconds simulated
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sim_ticks 140230347500 # Number of ticks simulated
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2011-06-20 03:43:43 +02:00
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sim_freq 1000000000000 # Frequency of simulated ticks
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2011-06-20 03:54:53 +02:00
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host_inst_rate 92522 # Simulator instruction rate (inst/s)
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host_tick_rate 32544608 # Simulator tick rate (ticks/s)
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host_mem_usage 159896 # Number of bytes of host memory used
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host_seconds 4308.87 # Real time elapsed on the host
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sim_insts 398664595 # Number of instructions simulated
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2011-06-20 03:43:43 +02:00
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system.cpu.dtb.fetch_hits 0 # ITB hits
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system.cpu.dtb.fetch_misses 0 # ITB misses
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2011-06-20 03:54:53 +02:00
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system.cpu.dtb.fetch_acv 0 # ITB acv
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system.cpu.dtb.fetch_accesses 0 # ITB accesses
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system.cpu.dtb.read_hits 94755013 # DTB read hits
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system.cpu.dtb.read_misses 21 # DTB read misses
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system.cpu.dtb.read_acv 0 # DTB read access violations
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system.cpu.dtb.read_accesses 94755034 # DTB read accesses
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system.cpu.dtb.write_hits 73522045 # DTB write hits
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system.cpu.dtb.write_misses 35 # DTB write misses
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2011-06-20 03:43:43 +02:00
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system.cpu.dtb.write_acv 0 # DTB write access violations
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2011-06-20 03:54:53 +02:00
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system.cpu.dtb.write_accesses 73522080 # DTB write accesses
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system.cpu.dtb.data_hits 168277058 # DTB hits
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system.cpu.dtb.data_misses 56 # DTB misses
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system.cpu.dtb.data_acv 0 # DTB access violations
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system.cpu.dtb.data_accesses 168277114 # DTB accesses
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system.cpu.itb.fetch_hits 48911022 # ITB hits
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system.cpu.itb.fetch_misses 44512 # ITB misses
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2011-06-20 03:43:43 +02:00
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system.cpu.itb.fetch_acv 0 # ITB acv
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2011-06-20 03:54:53 +02:00
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system.cpu.itb.fetch_accesses 48955534 # ITB accesses
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2011-06-20 03:43:43 +02:00
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system.cpu.itb.read_hits 0 # DTB read hits
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system.cpu.itb.read_misses 0 # DTB read misses
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2011-06-20 03:54:53 +02:00
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system.cpu.itb.read_acv 0 # DTB read access violations
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system.cpu.itb.read_accesses 0 # DTB read accesses
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2011-06-20 03:43:43 +02:00
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system.cpu.itb.write_hits 0 # DTB write hits
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system.cpu.itb.write_misses 0 # DTB write misses
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2011-06-20 03:54:53 +02:00
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system.cpu.itb.write_acv 0 # DTB write access violations
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system.cpu.itb.write_accesses 0 # DTB write accesses
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system.cpu.itb.data_hits 0 # DTB hits
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system.cpu.itb.data_misses 0 # DTB misses
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system.cpu.itb.data_acv 0 # DTB access violations
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system.cpu.itb.data_accesses 0 # DTB accesses
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system.cpu.workload.num_syscalls 215 # Number of system calls
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system.cpu.numCycles 280460696 # number of cpu cycles simulated
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system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
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system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
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system.cpu.contextSwitches 1 # Number of context switches
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system.cpu.threadCycles 280031759 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
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system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode
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system.cpu.timesIdled 6816 # Number of times that the entire CPU went into an idle state and unscheduled itself
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system.cpu.idleCycles 13555694 # Number of cycles cpu's stages were not processed
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system.cpu.runCycles 266905002 # Number of cycles cpu stages are processed.
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system.cpu.activity 95.166633 # Percentage of cycles cpu is active
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system.cpu.comLoads 94754489 # Number of Load instructions committed
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system.cpu.comStores 73520729 # Number of Store instructions committed
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system.cpu.comBranches 44587532 # Number of Branches instructions committed
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system.cpu.comNops 23089775 # Number of Nop instructions committed
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system.cpu.comNonSpec 215 # Number of Non-Speculative instructions committed
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system.cpu.comInts 112239074 # Number of Integer instructions committed
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system.cpu.comFloats 50439198 # Number of Floating Point instructions committed
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system.cpu.committedInsts 398664595 # Number of Instructions Simulated (Per-Thread)
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system.cpu.smtCommittedInsts 0 # Number of SMT Instructions Simulated (Per-Thread)
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system.cpu.committedInsts_total 398664595 # Number of Instructions Simulated (Total)
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system.cpu.cpi 0.703500 # CPI: Cycles Per Instruction (Per-Thread)
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system.cpu.smt_cpi no_value # CPI: Total SMT-CPI
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system.cpu.cpi_total 0.703500 # CPI: Total CPI of All Threads
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system.cpu.ipc 1.421463 # IPC: Instructions Per Cycle (Per-Thread)
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system.cpu.smt_ipc no_value # IPC: Total SMT-IPC
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system.cpu.ipc_total 1.421463 # IPC: Total IPC of All Threads
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system.cpu.branch_predictor.lookups 53559776 # Number of BP lookups
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system.cpu.branch_predictor.condPredicted 30675983 # Number of conditional branches predicted
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system.cpu.branch_predictor.condIncorrect 15431294 # Number of conditional branches incorrect
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system.cpu.branch_predictor.BTBLookups 36114910 # Number of BTB lookups
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system.cpu.branch_predictor.BTBHits 15774675 # Number of BTB hits
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system.cpu.branch_predictor.usedRAS 8007515 # Number of times the RAS was used to get a target.
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system.cpu.branch_predictor.RASInCorrect 19 # Number of incorrect RAS predictions.
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system.cpu.branch_predictor.BTBHitPct 43.679120 # BTB Hit Percentage
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system.cpu.branch_predictor.predictedTaken 29804615 # Number of Branches Predicted As Taken (True).
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system.cpu.branch_predictor.predictedNotTaken 23755161 # Number of Branches Predicted As Not Taken (False).
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system.cpu.regfile_manager.intRegFileReads 280315566 # Number of Reads from Int. Register File
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system.cpu.regfile_manager.intRegFileWrites 159335859 # Number of Writes to Int. Register File
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system.cpu.regfile_manager.intRegFileAccesses 439651425 # Total Accesses (Read+Write) to the Int. Register File
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system.cpu.regfile_manager.floatRegFileReads 119618904 # Number of Reads from FP Register File
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system.cpu.regfile_manager.floatRegFileWrites 100196481 # Number of Writes to FP Register File
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system.cpu.regfile_manager.floatRegFileAccesses 219815385 # Total Accesses (Read+Write) to the FP Register File
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system.cpu.regfile_manager.regForwards 100663476 # Number of Registers Read Through Forwarding Logic
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system.cpu.agen_unit.agens 168393095 # Number of Address Generations
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system.cpu.execution_unit.predictedTakenIncorrect 14667100 # Number of Branches Incorrectly Predicted As Taken.
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system.cpu.execution_unit.predictedNotTakenIncorrect 763535 # Number of Branches Incorrectly Predicted As Not Taken).
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system.cpu.execution_unit.mispredicted 15430635 # Number of Branches Incorrectly Predicted
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system.cpu.execution_unit.predicted 29156916 # Number of Branches Incorrectly Predicted
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system.cpu.execution_unit.mispredictPct 34.607496 # Percentage of Incorrect Branches Predicts
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system.cpu.execution_unit.executions 205476801 # Number of Instructions Executed.
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system.cpu.mult_div_unit.multiplies 2124324 # Number of Multipy Operations Executed
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system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed
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system.cpu.stage0.idleCycles 78228073 # Number of cycles 0 instructions are processed.
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system.cpu.stage0.runCycles 202232623 # Number of cycles 1+ instructions are processed.
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system.cpu.stage0.utilization 72.107296 # Percentage of cycles stage was utilized (processing insts).
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system.cpu.stage1.idleCycles 107968598 # Number of cycles 0 instructions are processed.
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system.cpu.stage1.runCycles 172492098 # Number of cycles 1+ instructions are processed.
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system.cpu.stage1.utilization 61.503127 # Percentage of cycles stage was utilized (processing insts).
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system.cpu.stage2.idleCycles 103201194 # Number of cycles 0 instructions are processed.
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system.cpu.stage2.runCycles 177259502 # Number of cycles 1+ instructions are processed.
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system.cpu.stage2.utilization 63.202974 # Percentage of cycles stage was utilized (processing insts).
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system.cpu.stage3.idleCycles 181732278 # Number of cycles 0 instructions are processed.
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system.cpu.stage3.runCycles 98728418 # Number of cycles 1+ instructions are processed.
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system.cpu.stage3.utilization 35.202230 # Percentage of cycles stage was utilized (processing insts).
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system.cpu.stage4.idleCycles 90865904 # Number of cycles 0 instructions are processed.
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system.cpu.stage4.runCycles 189594792 # Number of cycles 1+ instructions are processed.
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system.cpu.stage4.utilization 67.601199 # Percentage of cycles stage was utilized (processing insts).
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system.cpu.icache.replacements 1967 # number of replacements
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system.cpu.icache.tagsinuse 1829.231960 # Cycle average of tags in use
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system.cpu.icache.total_refs 48906646 # Total number of references to valid blocks.
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system.cpu.icache.sampled_refs 3894 # Sample count of references to valid blocks.
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system.cpu.icache.avg_refs 12559.487930 # Average number of references to valid blocks.
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system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu.icache.occ_blocks::0 1829.231960 # Average occupied blocks per context
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system.cpu.icache.occ_percent::0 0.893180 # Average percentage of cache occupancy
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system.cpu.icache.ReadReq_hits 48906646 # number of ReadReq hits
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system.cpu.icache.demand_hits 48906646 # number of demand (read+write) hits
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system.cpu.icache.overall_hits 48906646 # number of overall hits
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system.cpu.icache.ReadReq_misses 4375 # number of ReadReq misses
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system.cpu.icache.demand_misses 4375 # number of demand (read+write) misses
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system.cpu.icache.overall_misses 4375 # number of overall misses
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system.cpu.icache.ReadReq_miss_latency 214226000 # number of ReadReq miss cycles
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system.cpu.icache.demand_miss_latency 214226000 # number of demand (read+write) miss cycles
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system.cpu.icache.overall_miss_latency 214226000 # number of overall miss cycles
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system.cpu.icache.ReadReq_accesses 48911021 # number of ReadReq accesses(hits+misses)
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system.cpu.icache.demand_accesses 48911021 # number of demand (read+write) accesses
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system.cpu.icache.overall_accesses 48911021 # number of overall (read+write) accesses
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system.cpu.icache.ReadReq_miss_rate 0.000089 # miss rate for ReadReq accesses
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system.cpu.icache.demand_miss_rate 0.000089 # miss rate for demand accesses
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system.cpu.icache.overall_miss_rate 0.000089 # miss rate for overall accesses
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system.cpu.icache.ReadReq_avg_miss_latency 48965.942857 # average ReadReq miss latency
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system.cpu.icache.demand_avg_miss_latency 48965.942857 # average overall miss latency
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system.cpu.icache.overall_avg_miss_latency 48965.942857 # average overall miss latency
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system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
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system.cpu.icache.blocked_cycles::no_targets 45000 # number of cycles access was blocked
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system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
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system.cpu.icache.blocked::no_targets 1 # number of cycles access was blocked
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system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
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system.cpu.icache.avg_blocked_cycles::no_targets 45000 # average number of cycles each access was blocked
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system.cpu.icache.fast_writes 0 # number of fast writes performed
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system.cpu.icache.cache_copies 0 # number of cache copies performed
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system.cpu.icache.writebacks 0 # number of writebacks
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system.cpu.icache.ReadReq_mshr_hits 481 # number of ReadReq MSHR hits
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system.cpu.icache.demand_mshr_hits 481 # number of demand (read+write) MSHR hits
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system.cpu.icache.overall_mshr_hits 481 # number of overall MSHR hits
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system.cpu.icache.ReadReq_mshr_misses 3894 # number of ReadReq MSHR misses
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system.cpu.icache.demand_mshr_misses 3894 # number of demand (read+write) MSHR misses
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system.cpu.icache.overall_mshr_misses 3894 # number of overall MSHR misses
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system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
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system.cpu.icache.ReadReq_mshr_miss_latency 185204000 # number of ReadReq MSHR miss cycles
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system.cpu.icache.demand_mshr_miss_latency 185204000 # number of demand (read+write) MSHR miss cycles
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system.cpu.icache.overall_mshr_miss_latency 185204000 # number of overall MSHR miss cycles
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system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
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system.cpu.icache.ReadReq_mshr_miss_rate 0.000080 # mshr miss rate for ReadReq accesses
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system.cpu.icache.demand_mshr_miss_rate 0.000080 # mshr miss rate for demand accesses
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system.cpu.icache.overall_mshr_miss_rate 0.000080 # mshr miss rate for overall accesses
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system.cpu.icache.ReadReq_avg_mshr_miss_latency 47561.376477 # average ReadReq mshr miss latency
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system.cpu.icache.demand_avg_mshr_miss_latency 47561.376477 # average overall mshr miss latency
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system.cpu.icache.overall_avg_mshr_miss_latency 47561.376477 # average overall mshr miss latency
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system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
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system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
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system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
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system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.dcache.replacements 764 # number of replacements
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system.cpu.dcache.tagsinuse 3284.909965 # Cycle average of tags in use
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system.cpu.dcache.total_refs 168261959 # Total number of references to valid blocks.
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system.cpu.dcache.sampled_refs 4152 # Sample count of references to valid blocks.
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system.cpu.dcache.avg_refs 40525.519990 # Average number of references to valid blocks.
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system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu.dcache.occ_blocks::0 3284.909965 # Average occupied blocks per context
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system.cpu.dcache.occ_percent::0 0.801980 # Average percentage of cache occupancy
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system.cpu.dcache.ReadReq_hits 94753265 # number of ReadReq hits
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system.cpu.dcache.WriteReq_hits 73508694 # number of WriteReq hits
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system.cpu.dcache.demand_hits 168261959 # number of demand (read+write) hits
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system.cpu.dcache.overall_hits 168261959 # number of overall hits
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system.cpu.dcache.ReadReq_misses 1224 # number of ReadReq misses
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system.cpu.dcache.WriteReq_misses 12035 # number of WriteReq misses
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system.cpu.dcache.demand_misses 13259 # number of demand (read+write) misses
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system.cpu.dcache.overall_misses 13259 # number of overall misses
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system.cpu.dcache.ReadReq_miss_latency 63822000 # number of ReadReq miss cycles
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system.cpu.dcache.WriteReq_miss_latency 626725500 # number of WriteReq miss cycles
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system.cpu.dcache.demand_miss_latency 690547500 # number of demand (read+write) miss cycles
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system.cpu.dcache.overall_miss_latency 690547500 # number of overall miss cycles
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system.cpu.dcache.ReadReq_accesses 94754489 # number of ReadReq accesses(hits+misses)
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system.cpu.dcache.WriteReq_accesses 73520729 # number of WriteReq accesses(hits+misses)
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system.cpu.dcache.demand_accesses 168275218 # number of demand (read+write) accesses
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system.cpu.dcache.overall_accesses 168275218 # number of overall (read+write) accesses
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system.cpu.dcache.ReadReq_miss_rate 0.000013 # miss rate for ReadReq accesses
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system.cpu.dcache.WriteReq_miss_rate 0.000164 # miss rate for WriteReq accesses
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system.cpu.dcache.demand_miss_rate 0.000079 # miss rate for demand accesses
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system.cpu.dcache.overall_miss_rate 0.000079 # miss rate for overall accesses
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system.cpu.dcache.ReadReq_avg_miss_latency 52142.156863 # average ReadReq miss latency
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system.cpu.dcache.WriteReq_avg_miss_latency 52075.238887 # average WriteReq miss latency
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system.cpu.dcache.demand_avg_miss_latency 52081.416396 # average overall miss latency
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system.cpu.dcache.overall_avg_miss_latency 52081.416396 # average overall miss latency
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system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
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system.cpu.dcache.blocked_cycles::no_targets 82468000 # number of cycles access was blocked
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system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
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system.cpu.dcache.blocked::no_targets 1848 # number of cycles access was blocked
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|
|
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.dcache.avg_blocked_cycles::no_targets 44625.541126 # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
|
|
|
|
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
|
|
|
|
system.cpu.dcache.writebacks 649 # number of writebacks
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_hits 274 # number of ReadReq MSHR hits
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_hits 8833 # number of WriteReq MSHR hits
|
|
|
|
|
system.cpu.dcache.demand_mshr_hits 9107 # number of demand (read+write) MSHR hits
|
|
|
|
|
system.cpu.dcache.overall_mshr_hits 9107 # number of overall MSHR hits
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_misses 950 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_misses 3202 # number of WriteReq MSHR misses
|
|
|
|
|
system.cpu.dcache.demand_mshr_misses 4152 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.dcache.overall_mshr_misses 4152 # number of overall MSHR misses
|
|
|
|
|
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency 46179500 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency 169543500 # number of WriteReq MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.demand_mshr_miss_latency 215723000 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.overall_mshr_miss_latency 215723000 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate 0.000010 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate 0.000044 # mshr miss rate for WriteReq accesses
|
|
|
|
|
system.cpu.dcache.demand_mshr_miss_rate 0.000025 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.dcache.overall_mshr_miss_rate 0.000025 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 48610 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 52949.250468 # average WriteReq mshr miss latency
|
|
|
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency 51956.406551 # average overall mshr miss latency
|
|
|
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency 51956.406551 # average overall mshr miss latency
|
|
|
|
|
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
|
|
|
|
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
|
|
|
|
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
|
|
|
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
|
|
|
system.cpu.l2cache.replacements 13 # number of replacements
|
|
|
|
|
system.cpu.l2cache.tagsinuse 3899.405791 # Cycle average of tags in use
|
|
|
|
|
system.cpu.l2cache.total_refs 727 # Total number of references to valid blocks.
|
|
|
|
|
system.cpu.l2cache.sampled_refs 4719 # Sample count of references to valid blocks.
|
|
|
|
|
system.cpu.l2cache.avg_refs 0.154058 # Average number of references to valid blocks.
|
|
|
|
|
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
|
|
|
system.cpu.l2cache.occ_blocks::0 3528.869361 # Average occupied blocks per context
|
|
|
|
|
system.cpu.l2cache.occ_blocks::1 370.536429 # Average occupied blocks per context
|
|
|
|
|
system.cpu.l2cache.occ_percent::0 0.107693 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.l2cache.occ_percent::1 0.011308 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.l2cache.ReadReq_hits 656 # number of ReadReq hits
|
|
|
|
|
system.cpu.l2cache.Writeback_hits 649 # number of Writeback hits
|
|
|
|
|
system.cpu.l2cache.ReadExReq_hits 60 # number of ReadExReq hits
|
|
|
|
|
system.cpu.l2cache.demand_hits 716 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.l2cache.overall_hits 716 # number of overall hits
|
|
|
|
|
system.cpu.l2cache.ReadReq_misses 4185 # number of ReadReq misses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_misses 3145 # number of ReadExReq misses
|
|
|
|
|
system.cpu.l2cache.demand_misses 7330 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.l2cache.overall_misses 7330 # number of overall misses
|
|
|
|
|
system.cpu.l2cache.ReadReq_miss_latency 219146000 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadExReq_miss_latency 164975000 # number of ReadExReq miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_miss_latency 384121000 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_miss_latency 384121000 # number of overall miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadReq_accesses 4841 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.Writeback_accesses 649 # number of Writeback accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.ReadExReq_accesses 3205 # number of ReadExReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.demand_accesses 8046 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.overall_accesses 8046 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_miss_rate 0.864491 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_miss_rate 0.981279 # miss rate for ReadExReq accesses
|
|
|
|
|
system.cpu.l2cache.demand_miss_rate 0.911012 # miss rate for demand accesses
|
|
|
|
|
system.cpu.l2cache.overall_miss_rate 0.911012 # miss rate for overall accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency 52364.635603 # average ReadReq miss latency
|
|
|
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency 52456.279809 # average ReadExReq miss latency
|
|
|
|
|
system.cpu.l2cache.demand_avg_miss_latency 52403.956344 # average overall miss latency
|
|
|
|
|
system.cpu.l2cache.overall_avg_miss_latency 52403.956344 # average overall miss latency
|
2011-06-20 03:43:43 +02:00
|
|
|
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
2011-06-20 03:54:53 +02:00
|
|
|
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
2011-06-20 03:43:43 +02:00
|
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
2011-06-20 03:54:53 +02:00
|
|
|
system.cpu.l2cache.writebacks 0 # number of writebacks
|
2011-06-20 03:43:43 +02:00
|
|
|
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
|
|
|
|
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
2011-06-20 03:54:53 +02:00
|
|
|
system.cpu.l2cache.ReadReq_mshr_misses 4185 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_mshr_misses 3145 # number of ReadExReq MSHR misses
|
|
|
|
|
system.cpu.l2cache.demand_mshr_misses 7330 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.l2cache.overall_mshr_misses 7330 # number of overall MSHR misses
|
2011-06-20 03:43:43 +02:00
|
|
|
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
2011-06-20 03:54:53 +02:00
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency 168185500 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency 126767000 # number of ReadExReq MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_mshr_miss_latency 294952500 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_mshr_miss_latency 294952500 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.864491 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.981279 # mshr miss rate for ReadExReq accesses
|
|
|
|
|
system.cpu.l2cache.demand_mshr_miss_rate 0.911012 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.l2cache.overall_mshr_miss_rate 0.911012 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40187.694146 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40307.472178 # average ReadExReq mshr miss latency
|
|
|
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency 40239.085948 # average overall mshr miss latency
|
|
|
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency 40239.085948 # average overall mshr miss latency
|
|
|
|
|
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
|
|
|
|
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
2011-06-20 03:43:43 +02:00
|
|
|
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
2011-06-20 03:54:53 +02:00
|
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
2011-06-20 03:43:43 +02:00
|
|
|
|
|
|
|
|
---------- End Simulation Statistics ----------
|
