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gem5/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simout

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ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
stats: Update for UDelayEvent quiesce change
2015-10-10 23:45:41 +02:00
gem5 compiled Oct 10 2015 11:28:39
gem5 started Oct 10 2015 11:45:23
gem5 executing on artery, pid 26655
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-dual -re /home/joel/research/gem5/gem5/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-dual
stats: update a few stats from long O3 runs Very small changes to iew.predictedNotTakenIncorrect and iew.branchMispredicts. Looks like similar updates were committed on April 3 (changeset 235ff1c046df), but only for the quick tests.
2015-04-21 00:09:43 +02:00
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
Global frequency set at 1000000000000 ticks per second
stats: Update for UDelayEvent quiesce change
2015-10-10 23:45:41 +02:00
info: kernel located at: /home/joel/research/gem5/full_system_files/binaries/vmlinux.aarch32.ll_20131205.0-gem5
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
info: Using bootloader at address 0x10
info: Using kernel entry physical address at 0x80008000
stats: Update for UDelayEvent quiesce change
2015-10-10 23:45:41 +02:00
info: Loading DTB file: /home/joel/research/gem5/full_system_files/binaries/vexpress.aarch32.ll_20131205.0-gem5.2cpu.dtb at address 0x88000000
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
info: Entering event queue @ 0. Starting simulation...
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
stats: Update for UDelayEvent quiesce change
2015-10-10 23:45:41 +02:00
Exiting @ tick 2627260787000 because m5_exit instruction encountered
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