2009-04-06 03:53:15 +02:00
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// -*- mode:c++ -*-
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2010-06-02 19:58:04 +02:00
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// Copyright (c) 2010 ARM Limited
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// All rights reserved
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//
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// The license below extends only to copyright in the software and shall
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// not be construed as granting a license to any other intellectual
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// property including but not limited to intellectual property relating
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// to a hardware implementation of the functionality of the software
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// licensed hereunder. You may use the software subject to the license
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// terms below provided that you ensure that this notice is replicated
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// unmodified and in its entirety in all distributions of the software,
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// modified or unmodified, in source code or in binary form.
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//
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2009-04-06 03:53:15 +02:00
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// Copyright (c) 2007-2008 The Florida State University
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are
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// met: redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer;
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// redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in the
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// documentation and/or other materials provided with the distribution;
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// neither the name of the copyright holders nor the names of its
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// contributors may be used to endorse or promote products derived from
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// this software without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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//
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// Authors: Stephen Hines
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////////////////////////////////////////////////////////////////////
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//
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// Floating Point operate instructions
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//
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def template FPAExecute {{
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Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const
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{
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Fault fault = NoFault;
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%(fp_enable_check)s;
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%(op_decl)s;
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%(op_rd)s;
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2009-06-21 18:37:41 +02:00
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if (%(predicate_test)s) {
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%(code)s;
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if (fault == NoFault) {
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%(op_wb)s;
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}
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2009-04-06 03:53:15 +02:00
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}
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return fault;
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}
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}};
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def template FloatDoubleDecode {{
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{
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ArmStaticInst *i = NULL;
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switch (OPCODE_19 << 1 | OPCODE_7)
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{
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case 0:
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i = (ArmStaticInst *)new %(class_name)sS(machInst);
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break;
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case 1:
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i = (ArmStaticInst *)new %(class_name)sD(machInst);
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break;
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case 2:
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case 3:
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default:
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panic("Cannot decode float/double nature of the instruction");
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}
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return i;
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}
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}};
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// Primary format for float point operate instructions:
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def format FloatOp(code, *flags) {{
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orig_code = code
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cblk = code
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2009-06-22 02:14:51 +02:00
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iop = InstObjParams(name, Name, 'PredOp',
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2009-06-21 18:37:41 +02:00
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{"code": cblk,
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"predicate_test": predicateTest},
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flags)
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2009-04-06 03:53:15 +02:00
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header_output = BasicDeclare.subst(iop)
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decoder_output = BasicConstructor.subst(iop)
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exec_output = FPAExecute.subst(iop)
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sng_cblk = code
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2009-06-22 02:14:51 +02:00
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sng_iop = InstObjParams(name, Name+'S', 'PredOp',
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2009-06-21 18:37:41 +02:00
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{"code": sng_cblk,
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"predicate_test": predicateTest},
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flags)
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2009-04-06 03:53:15 +02:00
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header_output += BasicDeclare.subst(sng_iop)
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decoder_output += BasicConstructor.subst(sng_iop)
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exec_output += FPAExecute.subst(sng_iop)
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dbl_code = re.sub(r'\.sf', '.df', orig_code)
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dbl_cblk = dbl_code
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2009-06-22 02:14:51 +02:00
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dbl_iop = InstObjParams(name, Name+'D', 'PredOp',
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2009-06-21 18:37:41 +02:00
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{"code": dbl_cblk,
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"predicate_test": predicateTest},
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flags)
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2009-04-06 03:53:15 +02:00
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header_output += BasicDeclare.subst(dbl_iop)
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decoder_output += BasicConstructor.subst(dbl_iop)
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exec_output += FPAExecute.subst(dbl_iop)
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decode_block = FloatDoubleDecode.subst(iop)
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}};
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let {{
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calcFPCcCode = '''
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uint16_t _in, _iz, _ic, _iv;
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_in = %(fReg1)s < %(fReg2)s;
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_iz = %(fReg1)s == %(fReg2)s;
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_ic = %(fReg1)s >= %(fReg2)s;
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_iv = (isnan(%(fReg1)s) || isnan(%(fReg2)s)) & 1;
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2009-11-08 11:08:40 +01:00
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CondCodes = _in << 31 | _iz << 30 | _ic << 29 | _iv << 28 |
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(CondCodes & 0x0FFFFFFF);
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2009-04-06 03:53:15 +02:00
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'''
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}};
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def format FloatCmp(fReg1, fReg2, *flags) {{
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code = calcFPCcCode % vars()
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2009-06-22 02:14:51 +02:00
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iop = InstObjParams(name, Name, 'PredOp',
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2009-06-21 18:37:41 +02:00
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{"code": code,
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"predicate_test": predicateTest},
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flags)
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2009-04-06 03:53:15 +02:00
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header_output = BasicDeclare.subst(iop)
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decoder_output = BasicConstructor.subst(iop)
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decode_block = BasicDecode.subst(iop)
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exec_output = FPAExecute.subst(iop)
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}};
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2010-06-02 19:58:13 +02:00
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let {{
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header_output = '''
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StaticInstPtr
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decodeExtensionRegLoadStore(ExtMachInst machInst);
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'''
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decoder_output = '''
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StaticInstPtr
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decodeExtensionRegLoadStore(ExtMachInst machInst)
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2010-06-02 19:58:04 +02:00
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{
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const uint32_t opcode = bits(machInst, 24, 20);
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const uint32_t offset = bits(machInst, 7, 0);
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2010-06-02 19:58:12 +02:00
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const bool single = (bits(machInst, 8) == 0);
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2010-06-02 19:58:04 +02:00
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const IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 19, 16);
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RegIndex vd;
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if (single) {
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vd = (RegIndex)(uint32_t)((bits(machInst, 15, 12) << 1) |
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bits(machInst, 22));
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} else {
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vd = (RegIndex)(uint32_t)((bits(machInst, 15, 12) << 1) |
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(bits(machInst, 22) << 5));
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}
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switch (bits(opcode, 4, 3)) {
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case 0x0:
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2010-06-02 19:58:12 +02:00
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if (bits(opcode, 4, 1) == 0x2 &&
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!(machInst.thumb == 1 && bits(machInst, 28) == 1) &&
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!(machInst.thumb == 0 && machInst.condCode == 0xf)) {
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if ((bits(machInst, 7, 4) & 0xd) != 1) {
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break;
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}
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const IntRegIndex rt =
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(IntRegIndex)(uint32_t)bits(machInst, 15, 12);
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const IntRegIndex rt2 =
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(IntRegIndex)(uint32_t)bits(machInst, 19, 16);
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const bool op = bits(machInst, 20);
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uint32_t vm;
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2010-06-02 19:58:12 +02:00
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if (single) {
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2010-06-02 19:58:12 +02:00
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vm = (bits(machInst, 3, 0) << 1) | bits(machInst, 5);
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} else {
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vm = (bits(machInst, 3, 0) << 1) |
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(bits(machInst, 5) << 5);
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}
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if (op) {
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return new Vmov2Core2Reg(machInst, rt, rt2,
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(IntRegIndex)vm);
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} else {
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return new Vmov2Reg2Core(machInst, (IntRegIndex)vm,
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rt, rt2);
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}
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2010-06-02 19:58:04 +02:00
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}
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break;
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case 0x1:
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switch (bits(opcode, 1, 0)) {
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case 0x0:
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return new VLdmStm(machInst, rn, vd, single,
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true, false, false, offset);
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case 0x1:
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return new VLdmStm(machInst, rn, vd, single,
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true, false, true, offset);
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case 0x2:
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return new VLdmStm(machInst, rn, vd, single,
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true, true, false, offset);
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case 0x3:
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// If rn == sp, then this is called vpop.
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return new VLdmStm(machInst, rn, vd, single,
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true, true, true, offset);
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}
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case 0x2:
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if (bits(opcode, 1, 0) == 0x2) {
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// If rn == sp, then this is called vpush.
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return new VLdmStm(machInst, rn, vd, single,
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false, true, false, offset);
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} else if (bits(opcode, 1, 0) == 0x3) {
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return new VLdmStm(machInst, rn, vd, single,
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false, true, true, offset);
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}
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// Fall through on purpose
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case 0x3:
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2010-06-02 19:58:12 +02:00
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const bool up = (bits(machInst, 23) == 1);
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const uint32_t imm = bits(machInst, 7, 0) << 2;
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RegIndex vd;
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if (single) {
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vd = (RegIndex)(uint32_t)((bits(machInst, 15, 12) << 1) |
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(bits(machInst, 22)));
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} else {
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vd = (RegIndex)(uint32_t)((bits(machInst, 15, 12) << 1) |
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(bits(machInst, 22) << 5));
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}
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2010-06-02 19:58:04 +02:00
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if (bits(opcode, 1, 0) == 0x0) {
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2010-06-02 19:58:12 +02:00
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if (single) {
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if (up) {
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return new %(vstr_us)s(machInst, vd, rn, up, imm);
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} else {
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return new %(vstr_s)s(machInst, vd, rn, up, imm);
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}
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} else {
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if (up) {
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return new %(vstr_ud)s(machInst, vd, vd + 1,
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rn, up, imm);
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} else {
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return new %(vstr_d)s(machInst, vd, vd + 1,
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rn, up, imm);
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}
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}
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2010-06-02 19:58:04 +02:00
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} else if (bits(opcode, 1, 0) == 0x1) {
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2010-06-02 19:58:12 +02:00
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if (single) {
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if (up) {
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return new %(vldr_us)s(machInst, vd, rn, up, imm);
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} else {
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return new %(vldr_s)s(machInst, vd, rn, up, imm);
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}
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} else {
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if (up) {
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return new %(vldr_ud)s(machInst, vd, vd + 1,
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rn, up, imm);
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} else {
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return new %(vldr_d)s(machInst, vd, vd + 1,
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rn, up, imm);
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}
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}
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2010-06-02 19:58:04 +02:00
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}
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}
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return new Unknown(machInst);
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}
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2010-06-02 19:58:12 +02:00
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''' % {
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"vldr_us" : "VLDR_" + loadImmClassName(False, True, False),
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"vldr_s" : "VLDR_" + loadImmClassName(False, False, False),
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"vldr_ud" : "VLDR_" + loadDoubleImmClassName(False, True, False),
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2010-06-02 19:58:12 +02:00
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"vldr_d" : "VLDR_" + loadDoubleImmClassName(False, False, False),
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"vstr_us" : "VSTR_" + storeImmClassName(False, True, False),
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"vstr_s" : "VSTR_" + storeImmClassName(False, False, False),
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"vstr_ud" : "VSTR_" + storeDoubleImmClassName(False, True, False),
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"vstr_d" : "VSTR_" + storeDoubleImmClassName(False, False, False)
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2010-06-02 19:58:12 +02:00
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}
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2010-06-02 19:58:04 +02:00
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}};
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2010-06-02 19:58:11 +02:00
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2010-06-02 19:58:13 +02:00
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def format ExtensionRegLoadStore() {{
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2010-06-02 19:58:11 +02:00
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decode_block = '''
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2010-06-02 19:58:13 +02:00
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return decodeExtensionRegLoadStore(machInst);
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'''
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}};
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let {{
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header_output = '''
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StaticInstPtr
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decodeShortFpTransfer(ExtMachInst machInst);
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'''
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decoder_output = '''
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StaticInstPtr
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decodeShortFpTransfer(ExtMachInst machInst)
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2010-06-02 19:58:11 +02:00
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{
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const uint32_t l = bits(machInst, 20);
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const uint32_t c = bits(machInst, 8);
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const uint32_t a = bits(machInst, 23, 21);
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const uint32_t b = bits(machInst, 6, 5);
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if ((machInst.thumb == 1 && bits(machInst, 28) == 1) ||
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(machInst.thumb == 0 && machInst.condCode == 0xf)) {
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return new Unknown(machInst);
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}
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if (l == 0 && c == 0) {
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if (a == 0) {
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2010-06-02 19:58:12 +02:00
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const uint32_t vn = (bits(machInst, 19, 16) << 1) |
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bits(machInst, 7);
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const IntRegIndex rt =
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(IntRegIndex)(uint32_t)bits(machInst, 15, 12);
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if (bits(machInst, 20) == 1) {
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return new VmovRegCoreW(machInst, rt, (IntRegIndex)vn);
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} else {
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return new VmovCoreRegW(machInst, (IntRegIndex)vn, rt);
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}
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2010-06-02 19:58:11 +02:00
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} else if (a == 0x7) {
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2010-06-02 19:58:11 +02:00
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const IntRegIndex rt =
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|
|
(IntRegIndex)(uint32_t)bits(machInst, 15, 12);
|
|
|
|
uint32_t specReg = bits(machInst, 19, 16);
|
|
|
|
switch (specReg) {
|
|
|
|
case 0:
|
|
|
|
specReg = MISCREG_FPSID;
|
|
|
|
break;
|
|
|
|
case 1:
|
|
|
|
specReg = MISCREG_FPSCR;
|
|
|
|
break;
|
|
|
|
case 8:
|
|
|
|
specReg = MISCREG_FPEXC;
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
return new Unknown(machInst);
|
|
|
|
}
|
|
|
|
return new Vmsr(machInst, (IntRegIndex)specReg, rt);
|
2010-06-02 19:58:11 +02:00
|
|
|
}
|
|
|
|
} else if (l == 0 && c == 1) {
|
|
|
|
if (bits(a, 2) == 0) {
|
2010-06-02 19:58:12 +02:00
|
|
|
uint32_t vd = (bits(machInst, 7) << 5) |
|
|
|
|
(bits(machInst, 19, 16) << 1);
|
|
|
|
uint32_t index, size;
|
|
|
|
const IntRegIndex rt =
|
|
|
|
(IntRegIndex)(uint32_t)bits(machInst, 15, 12);
|
|
|
|
if (bits(machInst, 22) == 1) {
|
|
|
|
size = 8;
|
|
|
|
index = (bits(machInst, 21) << 2) |
|
|
|
|
bits(machInst, 6, 5);
|
|
|
|
} else if (bits(machInst, 5) == 1) {
|
|
|
|
size = 16;
|
|
|
|
index = (bits(machInst, 21) << 1) |
|
|
|
|
bits(machInst, 6);
|
|
|
|
} else if (bits(machInst, 6) == 0) {
|
|
|
|
size = 32;
|
|
|
|
index = bits(machInst, 21);
|
|
|
|
} else {
|
|
|
|
return new Unknown(machInst);
|
|
|
|
}
|
|
|
|
if (index >= (32 / size)) {
|
|
|
|
index -= (32 / size);
|
|
|
|
vd++;
|
|
|
|
}
|
|
|
|
switch (size) {
|
|
|
|
case 8:
|
|
|
|
return new VmovCoreRegB(machInst, (IntRegIndex)vd,
|
|
|
|
rt, index);
|
|
|
|
case 16:
|
|
|
|
return new VmovCoreRegH(machInst, (IntRegIndex)vd,
|
|
|
|
rt, index);
|
|
|
|
case 32:
|
|
|
|
return new VmovCoreRegW(machInst, (IntRegIndex)vd, rt);
|
|
|
|
}
|
2010-06-02 19:58:11 +02:00
|
|
|
} else if (bits(b, 1) == 0) {
|
|
|
|
// A8-594
|
|
|
|
return new WarnUnimplemented("vdup", machInst);
|
|
|
|
}
|
|
|
|
} else if (l == 1 && c == 0) {
|
|
|
|
if (a == 0) {
|
2010-06-02 19:58:12 +02:00
|
|
|
const uint32_t vn = (bits(machInst, 19, 16) << 1) |
|
|
|
|
bits(machInst, 7);
|
|
|
|
const IntRegIndex rt =
|
|
|
|
(IntRegIndex)(uint32_t)bits(machInst, 15, 12);
|
|
|
|
if (bits(machInst, 20) == 1) {
|
|
|
|
return new VmovRegCoreW(machInst, rt, (IntRegIndex)vn);
|
|
|
|
} else {
|
|
|
|
return new VmovCoreRegW(machInst, (IntRegIndex)vn, rt);
|
|
|
|
}
|
2010-06-02 19:58:11 +02:00
|
|
|
} else if (a == 7) {
|
2010-06-02 19:58:11 +02:00
|
|
|
const IntRegIndex rt =
|
|
|
|
(IntRegIndex)(uint32_t)bits(machInst, 15, 12);
|
|
|
|
uint32_t specReg = bits(machInst, 19, 16);
|
|
|
|
switch (specReg) {
|
|
|
|
case 0:
|
|
|
|
specReg = MISCREG_FPSID;
|
|
|
|
break;
|
|
|
|
case 1:
|
|
|
|
specReg = MISCREG_FPSCR;
|
|
|
|
break;
|
|
|
|
case 6:
|
|
|
|
specReg = MISCREG_MVFR1;
|
|
|
|
break;
|
|
|
|
case 7:
|
|
|
|
specReg = MISCREG_MVFR0;
|
|
|
|
break;
|
|
|
|
case 8:
|
|
|
|
specReg = MISCREG_FPEXC;
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
return new Unknown(machInst);
|
|
|
|
}
|
|
|
|
return new Vmrs(machInst, rt, (IntRegIndex)specReg);
|
2010-06-02 19:58:11 +02:00
|
|
|
}
|
|
|
|
} else {
|
2010-06-02 19:58:12 +02:00
|
|
|
uint32_t vd = (bits(machInst, 7) << 5) |
|
|
|
|
(bits(machInst, 19, 16) << 1);
|
|
|
|
uint32_t index, size;
|
|
|
|
const IntRegIndex rt =
|
|
|
|
(IntRegIndex)(uint32_t)bits(machInst, 15, 12);
|
|
|
|
const bool u = (bits(machInst, 23) == 1);
|
|
|
|
if (bits(machInst, 22) == 1) {
|
|
|
|
size = 8;
|
|
|
|
index = (bits(machInst, 21) << 2) |
|
|
|
|
bits(machInst, 6, 5);
|
|
|
|
} else if (bits(machInst, 5) == 1) {
|
|
|
|
size = 16;
|
|
|
|
index = (bits(machInst, 21) << 1) |
|
|
|
|
bits(machInst, 6);
|
|
|
|
} else if (bits(machInst, 6) == 0 && !u) {
|
|
|
|
size = 32;
|
|
|
|
index = bits(machInst, 21);
|
|
|
|
} else {
|
|
|
|
return new Unknown(machInst);
|
|
|
|
}
|
|
|
|
if (index >= (32 / size)) {
|
|
|
|
index -= (32 / size);
|
|
|
|
vd++;
|
|
|
|
}
|
|
|
|
switch (size) {
|
|
|
|
case 8:
|
|
|
|
if (u) {
|
|
|
|
return new VmovRegCoreUB(machInst, rt,
|
|
|
|
(IntRegIndex)vd, index);
|
|
|
|
} else {
|
|
|
|
return new VmovRegCoreSB(machInst, rt,
|
|
|
|
(IntRegIndex)vd, index);
|
|
|
|
}
|
|
|
|
case 16:
|
|
|
|
if (u) {
|
|
|
|
return new VmovRegCoreUH(machInst, rt,
|
|
|
|
(IntRegIndex)vd, index);
|
|
|
|
} else {
|
|
|
|
return new VmovRegCoreSH(machInst, rt,
|
|
|
|
(IntRegIndex)vd, index);
|
|
|
|
}
|
|
|
|
case 32:
|
|
|
|
return new VmovRegCoreW(machInst, rt, (IntRegIndex)vd);
|
|
|
|
}
|
2010-06-02 19:58:11 +02:00
|
|
|
}
|
|
|
|
return new Unknown(machInst);
|
|
|
|
}
|
|
|
|
'''
|
|
|
|
}};
|
2010-06-02 19:58:13 +02:00
|
|
|
|
|
|
|
def format ShortFpTransfer() {{
|
|
|
|
decode_block = '''
|
|
|
|
return decodeShortFpTransfer(machInst);
|
|
|
|
'''
|
|
|
|
}};
|
2010-06-02 19:58:14 +02:00
|
|
|
|
|
|
|
let {{
|
|
|
|
header_output = '''
|
|
|
|
StaticInstPtr
|
|
|
|
decodeVfpData(ExtMachInst machInst);
|
|
|
|
'''
|
|
|
|
decoder_output = '''
|
|
|
|
StaticInstPtr
|
|
|
|
decodeVfpData(ExtMachInst machInst)
|
|
|
|
{
|
|
|
|
const uint32_t opc1 = bits(machInst, 23, 20);
|
|
|
|
const uint32_t opc2 = bits(machInst, 19, 16);
|
|
|
|
const uint32_t opc3 = bits(machInst, 7, 6);
|
|
|
|
//const uint32_t opc4 = bits(machInst, 3, 0);
|
|
|
|
switch (opc1 & 0xb /* 1011 */) {
|
|
|
|
case 0x0:
|
2010-06-02 19:58:14 +02:00
|
|
|
if (bits(machInst, 6) == 0) {
|
|
|
|
uint32_t vd;
|
|
|
|
uint32_t vm;
|
|
|
|
uint32_t vn;
|
|
|
|
if (bits(machInst, 8) == 0) {
|
|
|
|
vd = bits(machInst, 22) | (bits(machInst, 15, 12) << 1);
|
|
|
|
vm = bits(machInst, 5) | (bits(machInst, 3, 0) << 1);
|
|
|
|
vn = bits(machInst, 7) | (bits(machInst, 19, 16) << 1);
|
|
|
|
return new VmlaS(machInst, (IntRegIndex)vd,
|
|
|
|
(IntRegIndex)vn, (IntRegIndex)vm);
|
|
|
|
} else {
|
|
|
|
vd = (bits(machInst, 22) << 5) |
|
|
|
|
(bits(machInst, 15, 12) << 1);
|
|
|
|
vm = (bits(machInst, 5) << 5) |
|
|
|
|
(bits(machInst, 3, 0) << 1);
|
|
|
|
vn = (bits(machInst, 7) << 5) |
|
|
|
|
(bits(machInst, 19, 16) << 1);
|
|
|
|
return new VmlaD(machInst, (IntRegIndex)vd,
|
|
|
|
(IntRegIndex)vn, (IntRegIndex)vm);
|
|
|
|
}
|
|
|
|
} else {
|
|
|
|
uint32_t vd;
|
|
|
|
uint32_t vm;
|
|
|
|
uint32_t vn;
|
|
|
|
if (bits(machInst, 8) == 0) {
|
|
|
|
vd = bits(machInst, 22) | (bits(machInst, 15, 12) << 1);
|
|
|
|
vm = bits(machInst, 5) | (bits(machInst, 3, 0) << 1);
|
|
|
|
vn = bits(machInst, 7) | (bits(machInst, 19, 16) << 1);
|
|
|
|
return new VmlsS(machInst, (IntRegIndex)vd,
|
|
|
|
(IntRegIndex)vn, (IntRegIndex)vm);
|
|
|
|
} else {
|
|
|
|
vd = (bits(machInst, 22) << 5) |
|
|
|
|
(bits(machInst, 15, 12) << 1);
|
|
|
|
vm = (bits(machInst, 5) << 5) |
|
|
|
|
(bits(machInst, 3, 0) << 1);
|
|
|
|
vn = (bits(machInst, 7) << 5) |
|
|
|
|
(bits(machInst, 19, 16) << 1);
|
|
|
|
return new VmlsD(machInst, (IntRegIndex)vd,
|
|
|
|
(IntRegIndex)vn, (IntRegIndex)vm);
|
|
|
|
}
|
|
|
|
}
|
2010-06-02 19:58:14 +02:00
|
|
|
case 0x2:
|
|
|
|
if ((opc3 & 0x1) == 0) {
|
2010-06-02 19:58:14 +02:00
|
|
|
uint32_t vd;
|
|
|
|
uint32_t vm;
|
|
|
|
uint32_t vn;
|
|
|
|
if (bits(machInst, 8) == 0) {
|
|
|
|
vd = bits(machInst, 22) | (bits(machInst, 15, 12) << 1);
|
|
|
|
vm = bits(machInst, 5) | (bits(machInst, 3, 0) << 1);
|
|
|
|
vn = bits(machInst, 7) | (bits(machInst, 19, 16) << 1);
|
|
|
|
return new VmulS(machInst, (IntRegIndex)vd,
|
|
|
|
(IntRegIndex)vn, (IntRegIndex)vm);
|
|
|
|
} else {
|
|
|
|
vd = (bits(machInst, 22) << 5) |
|
|
|
|
(bits(machInst, 15, 12) << 1);
|
|
|
|
vm = (bits(machInst, 5) << 5) |
|
|
|
|
(bits(machInst, 3, 0) << 1);
|
|
|
|
vn = (bits(machInst, 7) << 5) |
|
|
|
|
(bits(machInst, 19, 16) << 1);
|
|
|
|
return new VmulD(machInst, (IntRegIndex)vd,
|
|
|
|
(IntRegIndex)vn, (IntRegIndex)vm);
|
|
|
|
}
|
2010-06-02 19:58:14 +02:00
|
|
|
}
|
|
|
|
case 0x1:
|
|
|
|
return new WarnUnimplemented("vnmla, vnmls, vnmul", machInst);
|
|
|
|
case 0x3:
|
|
|
|
if ((opc3 & 0x1) == 0) {
|
2010-06-02 19:58:14 +02:00
|
|
|
uint32_t vd;
|
|
|
|
uint32_t vm;
|
|
|
|
uint32_t vn;
|
|
|
|
if (bits(machInst, 8) == 0) {
|
|
|
|
vd = bits(machInst, 22) | (bits(machInst, 15, 12) << 1);
|
|
|
|
vm = bits(machInst, 5) | (bits(machInst, 3, 0) << 1);
|
|
|
|
vn = bits(machInst, 7) | (bits(machInst, 19, 16) << 1);
|
|
|
|
return new VaddS(machInst, (IntRegIndex)vd,
|
|
|
|
(IntRegIndex)vn, (IntRegIndex)vm);
|
|
|
|
} else {
|
|
|
|
vd = (bits(machInst, 22) << 5) |
|
|
|
|
(bits(machInst, 15, 12) << 1);
|
|
|
|
vm = (bits(machInst, 5) << 5) |
|
|
|
|
(bits(machInst, 3, 0) << 1);
|
|
|
|
vn = (bits(machInst, 7) << 5) |
|
|
|
|
(bits(machInst, 19, 16) << 1);
|
|
|
|
return new VaddD(machInst, (IntRegIndex)vd,
|
|
|
|
(IntRegIndex)vn, (IntRegIndex)vm);
|
|
|
|
}
|
2010-06-02 19:58:14 +02:00
|
|
|
} else {
|
2010-06-02 19:58:14 +02:00
|
|
|
uint32_t vd;
|
|
|
|
uint32_t vm;
|
|
|
|
uint32_t vn;
|
|
|
|
if (bits(machInst, 8) == 0) {
|
|
|
|
vd = bits(machInst, 22) | (bits(machInst, 15, 12) << 1);
|
|
|
|
vm = bits(machInst, 5) | (bits(machInst, 3, 0) << 1);
|
|
|
|
vn = bits(machInst, 7) | (bits(machInst, 19, 16) << 1);
|
|
|
|
return new VsubS(machInst, (IntRegIndex)vd,
|
|
|
|
(IntRegIndex)vn, (IntRegIndex)vm);
|
|
|
|
} else {
|
|
|
|
vd = (bits(machInst, 22) << 5) |
|
|
|
|
(bits(machInst, 15, 12) << 1);
|
|
|
|
vm = (bits(machInst, 5) << 5) |
|
|
|
|
(bits(machInst, 3, 0) << 1);
|
|
|
|
vn = (bits(machInst, 7) << 5) |
|
|
|
|
(bits(machInst, 19, 16) << 1);
|
|
|
|
return new VsubD(machInst, (IntRegIndex)vd,
|
|
|
|
(IntRegIndex)vn, (IntRegIndex)vm);
|
|
|
|
}
|
2010-06-02 19:58:14 +02:00
|
|
|
}
|
|
|
|
case 0x8:
|
|
|
|
if ((opc3 & 0x1) == 0) {
|
2010-06-02 19:58:14 +02:00
|
|
|
uint32_t vd;
|
|
|
|
uint32_t vm;
|
|
|
|
uint32_t vn;
|
|
|
|
if (bits(machInst, 8) == 0) {
|
|
|
|
vd = bits(machInst, 22) | (bits(machInst, 15, 12) << 1);
|
|
|
|
vm = bits(machInst, 5) | (bits(machInst, 3, 0) << 1);
|
|
|
|
vn = bits(machInst, 7) | (bits(machInst, 19, 16) << 1);
|
|
|
|
return new VdivS(machInst, (IntRegIndex)vd,
|
|
|
|
(IntRegIndex)vn, (IntRegIndex)vm);
|
|
|
|
} else {
|
|
|
|
vd = (bits(machInst, 22) << 5) |
|
|
|
|
(bits(machInst, 15, 12) << 1);
|
|
|
|
vm = (bits(machInst, 5) << 5) |
|
|
|
|
(bits(machInst, 3, 0) << 1);
|
|
|
|
vn = (bits(machInst, 7) << 5) |
|
|
|
|
(bits(machInst, 19, 16) << 1);
|
|
|
|
return new VdivD(machInst, (IntRegIndex)vd,
|
|
|
|
(IntRegIndex)vn, (IntRegIndex)vm);
|
|
|
|
}
|
2010-06-02 19:58:14 +02:00
|
|
|
}
|
|
|
|
break;
|
|
|
|
case 0xb:
|
|
|
|
if ((opc3 & 0x1) == 0) {
|
|
|
|
uint32_t vd;
|
|
|
|
const uint32_t baseImm =
|
|
|
|
bits(machInst, 3, 0) | (bits(machInst, 19, 16) << 4);
|
|
|
|
if (bits(machInst, 8) == 0) {
|
|
|
|
vd = bits(machInst, 22) | (bits(machInst, 15, 12) << 1);
|
|
|
|
uint32_t imm = vfp_modified_imm(baseImm, false);
|
|
|
|
return new VmovImmS(machInst, (IntRegIndex)vd, imm);
|
|
|
|
} else {
|
|
|
|
vd = (bits(machInst, 22) << 5) |
|
|
|
|
(bits(machInst, 15, 12) << 1);
|
|
|
|
uint64_t imm = vfp_modified_imm(baseImm, true);
|
|
|
|
return new VmovImmD(machInst, (IntRegIndex)vd, imm);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
switch (opc2) {
|
|
|
|
case 0x0:
|
|
|
|
if (opc3 == 1) {
|
|
|
|
uint32_t vd;
|
|
|
|
uint32_t vm;
|
|
|
|
if (bits(machInst, 8) == 0) {
|
|
|
|
vd = bits(machInst, 22) | (bits(machInst, 15, 12) << 1);
|
|
|
|
vm = bits(machInst, 5) | (bits(machInst, 3, 0) << 1);
|
|
|
|
return new VmovRegS(machInst,
|
|
|
|
(IntRegIndex)vd, (IntRegIndex)vm);
|
|
|
|
} else {
|
|
|
|
vd = (bits(machInst, 22) << 5) |
|
|
|
|
(bits(machInst, 15, 12) << 1);
|
|
|
|
vm = (bits(machInst, 5) << 5) |
|
|
|
|
(bits(machInst, 3, 0) << 1);
|
|
|
|
return new VmovRegD(machInst,
|
|
|
|
(IntRegIndex)vd, (IntRegIndex)vm);
|
|
|
|
}
|
|
|
|
} else {
|
2010-06-02 19:58:14 +02:00
|
|
|
uint32_t vd;
|
|
|
|
uint32_t vm;
|
|
|
|
if (bits(machInst, 8) == 0) {
|
|
|
|
vd = bits(machInst, 22) | (bits(machInst, 15, 12) << 1);
|
|
|
|
vm = bits(machInst, 5) | (bits(machInst, 3, 0) << 1);
|
|
|
|
return new VabsS(machInst,
|
|
|
|
(IntRegIndex)vd, (IntRegIndex)vm);
|
|
|
|
} else {
|
|
|
|
vd = (bits(machInst, 22) << 5) |
|
|
|
|
(bits(machInst, 15, 12) << 1);
|
|
|
|
vm = (bits(machInst, 5) << 5) |
|
|
|
|
(bits(machInst, 3, 0) << 1);
|
|
|
|
return new VabsD(machInst,
|
|
|
|
(IntRegIndex)vd, (IntRegIndex)vm);
|
|
|
|
}
|
2010-06-02 19:58:14 +02:00
|
|
|
}
|
|
|
|
case 0x1:
|
|
|
|
if (opc3 == 1) {
|
2010-06-02 19:58:14 +02:00
|
|
|
uint32_t vd;
|
|
|
|
uint32_t vm;
|
|
|
|
if (bits(machInst, 8) == 0) {
|
|
|
|
vd = bits(machInst, 22) | (bits(machInst, 15, 12) << 1);
|
|
|
|
vm = bits(machInst, 5) | (bits(machInst, 3, 0) << 1);
|
|
|
|
return new VnegS(machInst,
|
|
|
|
(IntRegIndex)vd, (IntRegIndex)vm);
|
|
|
|
} else {
|
|
|
|
vd = (bits(machInst, 22) << 5) |
|
|
|
|
(bits(machInst, 15, 12) << 1);
|
|
|
|
vm = (bits(machInst, 5) << 5) |
|
|
|
|
(bits(machInst, 3, 0) << 1);
|
|
|
|
return new VnegD(machInst,
|
|
|
|
(IntRegIndex)vd, (IntRegIndex)vm);
|
|
|
|
}
|
2010-06-02 19:58:14 +02:00
|
|
|
} else {
|
2010-06-02 19:58:14 +02:00
|
|
|
uint32_t vd;
|
|
|
|
uint32_t vm;
|
|
|
|
if (bits(machInst, 8) == 0) {
|
|
|
|
vd = bits(machInst, 22) | (bits(machInst, 15, 12) << 1);
|
|
|
|
vm = bits(machInst, 5) | (bits(machInst, 3, 0) << 1);
|
|
|
|
return new VsqrtS(machInst,
|
|
|
|
(IntRegIndex)vd, (IntRegIndex)vm);
|
|
|
|
} else {
|
|
|
|
vd = (bits(machInst, 22) << 5) |
|
|
|
|
(bits(machInst, 15, 12) << 1);
|
|
|
|
vm = (bits(machInst, 5) << 5) |
|
|
|
|
(bits(machInst, 3, 0) << 1);
|
|
|
|
return new VsqrtD(machInst,
|
|
|
|
(IntRegIndex)vd, (IntRegIndex)vm);
|
|
|
|
}
|
2010-06-02 19:58:14 +02:00
|
|
|
}
|
|
|
|
case 0x2:
|
|
|
|
case 0x3:
|
|
|
|
// Between half and single precision.
|
|
|
|
return new WarnUnimplemented("vcvtb, vcvtt", machInst);
|
|
|
|
case 0x4:
|
|
|
|
case 0x5:
|
|
|
|
return new WarnUnimplemented("vcmp, vcmpe", machInst);
|
|
|
|
case 0x7:
|
|
|
|
if (opc3 == 0x3) {
|
|
|
|
// Between double and single precision.
|
|
|
|
return new WarnUnimplemented("vcvt", machInst);
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
case 0x8:
|
|
|
|
// Between FP and int.
|
|
|
|
return new WarnUnimplemented("vcvt, vcvtr", machInst);
|
|
|
|
case 0xa:
|
|
|
|
case 0xb:
|
|
|
|
// Between FP and fixed point.
|
|
|
|
return new WarnUnimplemented("vcvt", machInst);
|
|
|
|
case 0xc:
|
|
|
|
case 0xd:
|
|
|
|
// Between FP and int.
|
|
|
|
return new WarnUnimplemented("vcvt, vcvtr", machInst);
|
|
|
|
case 0xe:
|
|
|
|
case 0xf:
|
|
|
|
// Between FP and fixed point.
|
|
|
|
return new WarnUnimplemented("vcvt", machInst);
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
return new Unknown(machInst);
|
|
|
|
}
|
|
|
|
'''
|
|
|
|
}};
|
|
|
|
|
|
|
|
def format VfpData() {{
|
|
|
|
decode_block = '''
|
|
|
|
return decodeVfpData(machInst);
|
|
|
|
'''
|
|
|
|
}};
|