410 lines
15 KiB
C++
410 lines
15 KiB
C++
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/*
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* Copyright (c) 2003-2005 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Gabe Black
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* Ali Saidi
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*/
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#ifndef __ARCH_SPARC_MISCREGFILE_HH__
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#define __ARCH_SPARC_MISCREGFILE_HH__
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#include "arch/sparc/faults.hh"
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#include "arch/sparc/isa_traits.hh"
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#include "arch/sparc/types.hh"
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#include <string>
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namespace SparcISA
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{
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//These functions map register indices to names
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std::string getMiscRegName(RegIndex);
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const int AsrStart = 0;
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const int PrStart = 32;
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const int HprStart = 64;
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const int MiscStart = 96;
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enum MiscRegIndex
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{
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/** Ancillary State Registers */
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MISCREG_Y = AsrStart + 0,
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MISCREG_CCR = AsrStart + 2,
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MISCREG_ASI = AsrStart + 3,
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MISCREG_TICK = AsrStart + 4,
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MISCREG_FPRS = AsrStart + 6,
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MISCREG_PCR = AsrStart + 16,
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MISCREG_PIC = AsrStart + 17,
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MISCREG_GSR = AsrStart + 19,
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MISCREG_SOFTINT_SET = AsrStart + 20,
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MISCREG_SOFTINT_CLR = AsrStart + 21,
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MISCREG_SOFTINT = AsrStart + 22,
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MISCREG_TICK_CMPR = AsrStart + 23,
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MISCREG_STICK = AsrStart + 24,
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MISCREG_STICK_CMPR = AsrStart + 25,
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/** Privilged Registers */
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MISCREG_TPC = PrStart + 0,
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MISCREG_TNPC = PrStart + 1,
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MISCREG_TSTATE = PrStart + 2,
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MISCREG_TT = PrStart + 3,
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MISCREG_PRIVTICK = PrStart + 4,
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MISCREG_TBA = PrStart + 5,
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MISCREG_PSTATE = PrStart + 6,
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MISCREG_TL = PrStart + 7,
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MISCREG_PIL = PrStart + 8,
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MISCREG_CWP = PrStart + 9,
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MISCREG_CANSAVE = PrStart + 10,
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MISCREG_CANRESTORE = PrStart + 11,
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MISCREG_CLEANWIN = PrStart + 12,
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MISCREG_OTHERWIN = PrStart + 13,
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MISCREG_WSTATE = PrStart + 14,
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MISCREG_GL = PrStart + 16,
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/** Hyper privileged registers */
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MISCREG_HPSTATE = HprStart + 0,
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MISCREG_HTSTATE = HprStart + 1,
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MISCREG_HINTP = HprStart + 3,
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MISCREG_HTBA = HprStart + 5,
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MISCREG_HVER = HprStart + 6,
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MISCREG_STRAND_STS_REG = HprStart + 16,
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MISCREG_HSTICK_CMPR = HprStart + 31,
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/** Floating Point Status Register */
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MISCREG_FSR = MiscStart + 0
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};
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// The control registers, broken out into fields
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class MiscRegFile
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{
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private:
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/* ASR Registers */
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union {
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uint64_t y; // Y (used in obsolete multiplication)
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struct {
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uint64_t value:32; // The actual value stored in y
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uint64_t :32; // reserved bits
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} yFields;
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};
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union {
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uint8_t ccr; // Condition Code Register
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struct {
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union {
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uint8_t icc:4; // 32-bit condition codes
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struct {
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uint8_t c:1; // Carry
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uint8_t v:1; // Overflow
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uint8_t z:1; // Zero
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uint8_t n:1; // Negative
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} iccFields;
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};
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union {
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uint8_t xcc:4; // 64-bit condition codes
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struct {
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uint8_t c:1; // Carry
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uint8_t v:1; // Overflow
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uint8_t z:1; // Zero
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uint8_t n:1; // Negative
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} xccFields;
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};
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} ccrFields;
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};
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uint8_t asi; // Address Space Identifier
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union {
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uint64_t tick; // Hardware clock-tick counter
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struct {
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int64_t counter:63; // Clock-tick count
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uint64_t npt:1; // Non-priveleged trap
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} tickFields;
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};
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union {
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uint8_t fprs; // Floating-Point Register State
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struct {
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uint8_t dl:1; // Dirty lower
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uint8_t du:1; // Dirty upper
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uint8_t fef:1; // FPRS enable floating-Point
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} fprsFields;
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};
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union {
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uint64_t gsr; //General Status Register
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struct {
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uint64_t mask:32;
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uint64_t :4;
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uint64_t im:1;
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uint64_t irnd:2;
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uint64_t :17;
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uint64_t scale:5;
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uint64_t align:3;
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} gsrFields;
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};
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union {
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uint64_t softint;
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struct {
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uint64_t tm:1;
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uint64_t int_level:14;
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uint64_t sm:1;
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} softintFields;
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};
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union {
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uint64_t tick_cmpr; // Hardware tick compare registers
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struct {
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uint64_t tick_cmpr:63; // Clock-tick count
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uint64_t int_dis:1; // Non-priveleged trap
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} tick_cmprFields;
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};
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union {
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uint64_t stick; // Hardware clock-tick counter
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struct {
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int64_t :63; // Not used, storage in SparcSystem
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uint64_t npt:1; // Non-priveleged trap
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} stickFields;
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};
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union {
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uint64_t stick_cmpr; // Hardware tick compare registers
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struct {
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uint64_t tick_cmpr:63; // Clock-tick count
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uint64_t int_dis:1; // Non-priveleged trap
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} stick_cmprFields;
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};
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/* Privileged Registers */
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uint64_t tpc[MaxTL]; // Trap Program Counter (value from
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// previous trap level)
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uint64_t tnpc[MaxTL]; // Trap Next Program Counter (value from
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// previous trap level)
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union {
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uint64_t tstate[MaxTL]; // Trap State
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struct {
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//Values are from previous trap level
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uint64_t cwp:5; // Current Window Pointer
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uint64_t :3; // Reserved bits
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uint64_t pstate:13; // Process State
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uint64_t :3; // Reserved bits
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uint64_t asi:8; // Address Space Identifier
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uint64_t ccr:8; // Condition Code Register
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uint64_t gl:8; // Global level
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} tstateFields[MaxTL];
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};
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uint16_t tt[MaxTL]; // Trap Type (Type of trap which occured
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// on the previous level)
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uint64_t tba; // Trap Base Address
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union {
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uint16_t pstate; // Process State Register
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struct {
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uint16_t :1; // reserved
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uint16_t ie:1; // Interrupt enable
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uint16_t priv:1; // Privelege mode
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uint16_t am:1; // Address mask
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uint16_t pef:1; // PSTATE enable floating-point
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uint16_t :1; // reserved2
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uint16_t mm:2; // Memory Model
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uint16_t tle:1; // Trap little-endian
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uint16_t cle:1; // Current little-endian
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} pstateFields;
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};
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uint8_t tl; // Trap Level
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uint8_t pil; // Process Interrupt Register
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uint8_t cwp; // Current Window Pointer
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uint8_t cansave; // Savable windows
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uint8_t canrestore; // Restorable windows
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uint8_t cleanwin; // Clean windows
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uint8_t otherwin; // Other windows
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union {
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uint8_t wstate; // Window State
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struct {
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uint8_t normal:3; // Bits TT<4:2> are set to on a normal
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// register window trap
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uint8_t other:3; // Bits TT<4:2> are set to on an "otherwin"
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// register window trap
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} wstateFields;
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};
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uint8_t gl; // Global level register
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/** Hyperprivileged Registers */
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union {
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uint64_t hpstate; // Hyperprivileged State Register
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struct {
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uint8_t tlz: 1;
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uint8_t :1;
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uint8_t hpriv:1;
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uint8_t :2;
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uint8_t red:1;
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uint8_t :4;
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uint8_t ibe:1;
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uint8_t id:1;
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} hpstateFields;
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};
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uint64_t htstate[MaxTL]; // Hyperprivileged Trap State Register
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uint64_t hintp;
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uint64_t htba; // Hyperprivileged Trap Base Address register
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union {
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uint64_t hstick_cmpr; // Hardware tick compare registers
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struct {
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uint64_t tick_cmpr:63; // Clock-tick count
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uint64_t int_dis:1; // Non-priveleged trap
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} hstick_cmprFields;
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};
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uint64_t strandStatusReg; // Per strand status register
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/** Floating point misc registers. */
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union {
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uint64_t fsr; // Floating-Point State Register
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struct {
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union {
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uint64_t cexc:5; // Current excpetion
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struct {
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uint64_t nxc:1; // Inexact
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uint64_t dzc:1; // Divide by zero
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uint64_t ufc:1; // Underflow
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uint64_t ofc:1; // Overflow
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uint64_t nvc:1; // Invalid operand
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} cexcFields;
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};
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union {
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uint64_t aexc:5; // Accrued exception
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struct {
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uint64_t nxc:1; // Inexact
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uint64_t dzc:1; // Divide by zero
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uint64_t ufc:1; // Underflow
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uint64_t ofc:1; // Overflow
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uint64_t nvc:1; // Invalid operand
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} aexcFields;
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};
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uint64_t fcc0:2; // Floating-Point condtion codes
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uint64_t :1; // Reserved bits
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uint64_t qne:1; // Deferred trap queue not empty
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// with no queue, it should read 0
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uint64_t ftt:3; // Floating-Point trap type
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uint64_t ver:3; // Version (of the FPU)
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uint64_t :2; // Reserved bits
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uint64_t ns:1; // Nonstandard floating point
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union {
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uint64_t tem:5; // Trap Enable Mask
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struct {
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uint64_t nxm:1; // Inexact
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uint64_t dzm:1; // Divide by zero
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uint64_t ufm:1; // Underflow
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uint64_t ofm:1; // Overflow
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uint64_t nvm:1; // Invalid operand
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} temFields;
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};
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uint64_t :2; // Reserved bits
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uint64_t rd:2; // Rounding direction
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uint64_t fcc1:2; // Floating-Point condition codes
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uint64_t fcc2:2; // Floating-Point condition codes
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uint64_t fcc3:2; // Floating-Point condition codes
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uint64_t :26; // Reserved bits
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} fsrFields;
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};
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// These need to check the int_dis field and if 0 then
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// set appropriate bit in softint and checkinterrutps on the cpu
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#if FULL_SYSTEM
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/** Process a tick compare event and generate an interrupt on the cpu if
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* appropriate. */
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void processTickCompare(ThreadContext *tc);
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void processSTickCompare(ThreadContext *tc);
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void processHSTickCompare(ThreadContext *tc);
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typedef CpuEventWrapper<MiscRegFile,
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&MiscRegFile::processTickCompare> TickCompareEvent;
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TickCompareEvent *tickCompare;
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typedef CpuEventWrapper<MiscRegFile,
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&MiscRegFile::processSTickCompare> STickCompareEvent;
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STickCompareEvent *sTickCompare;
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typedef CpuEventWrapper<MiscRegFile,
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&MiscRegFile::processHSTickCompare> HSTickCompareEvent;
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HSTickCompareEvent *hSTickCompare;
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/** Fullsystem only register version of ReadRegWithEffect() */
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MiscReg readFSRegWithEffect(int miscReg, Fault &fault, ThreadContext *tc);
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/** Fullsystem only register version of SetRegWithEffect() */
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Fault setFSRegWithEffect(int miscReg, const MiscReg &val,
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ThreadContext * tc);
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#endif
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public:
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void reset();
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||
|
|
MiscRegFile()
|
||
|
|
{
|
||
|
|
reset();
|
||
|
|
}
|
||
|
|
|
||
|
|
/** read a value out of an either an SE or FS IPR. No checking is done
|
||
|
|
* about SE vs. FS as this is mostly used to copy the regfile. Thus more
|
||
|
|
* register are copied that are necessary for FS. However this prevents
|
||
|
|
* a bunch of ifdefs and is rarely called so is not performance
|
||
|
|
* criticial. */
|
||
|
|
MiscReg readReg(int miscReg);
|
||
|
|
|
||
|
|
/** Read a value from an IPR. Only the SE iprs are here and the rest
|
||
|
|
* are are readFSRegWithEffect (which is called by readRegWithEffect()).
|
||
|
|
* Checking is done for permission based on state bits in the miscreg
|
||
|
|
* file. */
|
||
|
|
MiscReg readRegWithEffect(int miscReg, Fault &fault, ThreadContext *tc);
|
||
|
|
|
||
|
|
/** write a value into an either an SE or FS IPR. No checking is done
|
||
|
|
* about SE vs. FS as this is mostly used to copy the regfile. Thus more
|
||
|
|
* register are copied that are necessary for FS. However this prevents
|
||
|
|
* a bunch of ifdefs and is rarely called so is not performance
|
||
|
|
* criticial.*/
|
||
|
|
Fault setReg(int miscReg, const MiscReg &val);
|
||
|
|
|
||
|
|
/** Write a value into an IPR. Only the SE iprs are here and the rest
|
||
|
|
* are are setFSRegWithEffect (which is called by setRegWithEffect()).
|
||
|
|
* Checking is done for permission based on state bits in the miscreg
|
||
|
|
* file. */
|
||
|
|
Fault setRegWithEffect(int miscReg,
|
||
|
|
const MiscReg &val, ThreadContext * tc);
|
||
|
|
|
||
|
|
void serialize(std::ostream & os);
|
||
|
|
|
||
|
|
void unserialize(Checkpoint * cp, const std::string & section);
|
||
|
|
|
||
|
|
void copyMiscRegs(ThreadContext * tc);
|
||
|
|
|
||
|
|
protected:
|
||
|
|
|
||
|
|
bool isHyperPriv() { return hpstateFields.hpriv; }
|
||
|
|
bool isPriv() { return hpstateFields.hpriv || pstateFields.priv; }
|
||
|
|
bool isNonPriv() { return !isPriv(); }
|
||
|
|
};
|
||
|
|
}
|
||
|
|
|
||
|
|
#endif
|