112 lines
3.8 KiB
C
112 lines
3.8 KiB
C
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/*****************************************************************************
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* McPAT
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* SOFTWARE LICENSE AGREEMENT
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* Copyright 2012 Hewlett-Packard Development Company, L.P.
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* All Rights Reserved
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.”
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*
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***************************************************************************/
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#ifndef __INTERCONNECT_H__
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#define __INTERCONNECT_H__
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#include "assert.h"
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#include "basic_circuit.h"
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#include "basic_components.h"
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#include "cacti_interface.h"
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#include "component.h"
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#include "parameter.h"
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#include "subarray.h"
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#include "wire.h"
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// leakge power includes entire htree in a bank (when uca_tree == false)
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// leakge power includes only part to one bank when uca_tree == true
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class interconnect : public Component
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{
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public:
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interconnect(
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string name_,
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enum Device_ty device_ty_,
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double base_w, double base_h, int data_w, double len,
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const InputParameter *configure_interface, int start_wiring_level_,
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bool pipelinable_ = false,
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double route_over_perc_ =0.5,
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bool opt_local_=true,
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enum Core_type core_ty_=Inorder,
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enum Wire_type wire_model=Global,
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double width_s=1.0, double space_s=1.0,
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TechnologyParameter::DeviceType *dt = &(g_tp.peri_global)
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);
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~interconnect() {};
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void compute();
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string name;
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enum Device_ty device_ty;
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double in_rise_time, out_rise_time;
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InputParameter l_ip;
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uca_org_t local_result;
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Area no_device_under_wire_area;
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void set_in_rise_time(double rt)
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{
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in_rise_time = rt;
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}
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void leakage_feedback(double temperature);
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double max_unpipelined_link_delay;
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powerDef power_bit;
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double wire_bw;
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double init_wire_bw; // bus width at root
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double base_width;
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double base_height;
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int data_width;
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enum Wire_type wt;
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double width_scaling, space_scaling;
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int start_wiring_level;
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double length;
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double min_w_nmos;
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double min_w_pmos;
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double latency, throughput;
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bool latency_overflow;
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bool throughput_overflow;
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double interconnect_latency;
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double interconnect_throughput;
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bool opt_local;
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enum Core_type core_ty;
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bool pipelinable;
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double route_over_perc;
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int num_pipe_stages;
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private:
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TechnologyParameter::DeviceType *deviceType;
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};
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#endif
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