2006-03-04 09:09:23 +01:00
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/*
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2007-11-15 20:21:01 +01:00
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* Copyright (c) 2004-2005 The Regents of The University of Michigan
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* All rights reserved.
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2007-11-13 22:58:16 +01:00
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*
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2007-11-15 20:21:01 +01:00
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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2006-03-04 09:09:23 +01:00
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*
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2007-11-15 20:21:01 +01:00
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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2006-03-04 09:09:23 +01:00
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*
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2007-11-15 20:21:01 +01:00
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* Authors: Gabe Black
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* Ali Saidi
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* Korey Sewell
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2006-03-04 09:09:23 +01:00
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*/
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2006-03-15 23:04:50 +01:00
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#include "arch/mips/isa_traits.hh"
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2006-03-04 09:09:23 +01:00
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#include "arch/mips/process.hh"
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2009-09-17 21:59:43 +02:00
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2006-03-12 22:27:52 +01:00
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#include "base/loader/object_file.hh"
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2009-12-31 21:30:51 +01:00
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#include "base/loader/elf_object.hh"
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2006-03-12 22:27:52 +01:00
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#include "base/misc.hh"
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2006-06-06 23:32:21 +02:00
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#include "cpu/thread_context.hh"
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2009-09-17 21:59:43 +02:00
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#include "mem/page_table.hh"
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#include "sim/process.hh"
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#include "sim/process_impl.hh"
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2006-03-15 23:04:50 +01:00
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#include "sim/system.hh"
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2006-03-04 09:09:23 +01:00
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2006-03-12 11:57:34 +01:00
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using namespace std;
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2006-03-15 23:04:50 +01:00
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using namespace MipsISA;
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2006-03-12 11:57:34 +01:00
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2007-10-17 03:04:01 +02:00
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MipsLiveProcess::MipsLiveProcess(LiveProcessParams * params,
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ObjectFile *objFile)
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: LiveProcess(params, objFile)
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2006-03-15 23:04:50 +01:00
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{
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2006-06-09 09:57:25 +02:00
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// Set up stack. On MIPS, stack starts at the top of kuseg
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// user address space. MIPS stack grows down from here
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2006-07-23 19:39:42 +02:00
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stack_base = 0x7FFFFFFF;
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2006-03-15 23:04:50 +01:00
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2006-06-09 09:57:25 +02:00
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// Set pointer for next thread stack. Reserve 8M for main stack.
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next_thread_stack_base = stack_base - (8 * 1024 * 1024);
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// Set up break point (Top of Heap)
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2006-03-15 23:04:50 +01:00
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brk_point = objFile->dataBase() + objFile->dataSize() + objFile->bssSize();
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brk_point = roundUp(brk_point, VMPageSize);
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2009-12-31 21:30:51 +01:00
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// Set up region for mmaps. Start it 1GB above the top of the heap.
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mmap_start = mmap_end = brk_point + 0x40000000L;
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2006-03-15 23:04:50 +01:00
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}
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void
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MipsLiveProcess::startup()
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{
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2009-09-17 21:59:43 +02:00
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Process::startup();
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2009-12-31 21:30:51 +01:00
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argsInit<uint32_t>(VMPageSize);
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2006-03-15 23:04:50 +01:00
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}
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2009-02-27 18:22:14 +01:00
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2009-12-31 21:30:51 +01:00
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template<class IntType>
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2009-09-17 21:59:43 +02:00
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void
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2009-12-31 21:30:51 +01:00
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MipsLiveProcess::argsInit(int pageSize)
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2009-09-17 21:59:43 +02:00
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{
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2009-12-31 21:30:51 +01:00
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int intSize = sizeof(IntType);
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Process::startup();
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2009-09-17 21:59:43 +02:00
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// load object file into target memory
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objFile->loadSections(initVirtMem);
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2009-12-31 21:30:51 +01:00
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typedef AuxVector<IntType> auxv_t;
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std::vector<auxv_t> auxv;
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ElfObject * elfObject = dynamic_cast<ElfObject *>(objFile);
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if (elfObject)
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{
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// Set the system page size
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auxv.push_back(auxv_t(M5_AT_PAGESZ, MipsISA::VMPageSize));
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// Set the frequency at which time() increments
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auxv.push_back(auxv_t(M5_AT_CLKTCK, 100));
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// For statically linked executables, this is the virtual
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// address of the program header tables if they appear in the
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// executable image.
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auxv.push_back(auxv_t(M5_AT_PHDR, elfObject->programHeaderTable()));
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DPRINTF(Loader, "auxv at PHDR %08p\n", elfObject->programHeaderTable());
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// This is the size of a program header entry from the elf file.
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auxv.push_back(auxv_t(M5_AT_PHENT, elfObject->programHeaderSize()));
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// This is the number of program headers from the original elf file.
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auxv.push_back(auxv_t(M5_AT_PHNUM, elfObject->programHeaderCount()));
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//The entry point to the program
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auxv.push_back(auxv_t(M5_AT_ENTRY, objFile->entryPoint()));
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//Different user and group IDs
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auxv.push_back(auxv_t(M5_AT_UID, uid()));
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auxv.push_back(auxv_t(M5_AT_EUID, euid()));
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auxv.push_back(auxv_t(M5_AT_GID, gid()));
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auxv.push_back(auxv_t(M5_AT_EGID, egid()));
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}
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// Calculate how much space we need for arg & env & auxv arrays.
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2009-09-17 21:59:43 +02:00
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int argv_array_size = intSize * (argv.size() + 1);
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int envp_array_size = intSize * (envp.size() + 1);
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2009-12-31 21:30:51 +01:00
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int auxv_array_size = intSize * 2 * (auxv.size() + 1);
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2009-09-17 21:59:43 +02:00
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int arg_data_size = 0;
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for (vector<string>::size_type i = 0; i < argv.size(); ++i) {
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arg_data_size += argv[i].size() + 1;
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}
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int env_data_size = 0;
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for (vector<string>::size_type i = 0; i < envp.size(); ++i) {
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env_data_size += envp[i].size() + 1;
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}
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int space_needed =
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2009-12-31 21:30:51 +01:00
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argv_array_size +
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envp_array_size +
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auxv_array_size +
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arg_data_size +
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env_data_size;
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2009-09-17 21:59:43 +02:00
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// set bottom of stack
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stack_min = stack_base - space_needed;
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// align it
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stack_min = roundDown(stack_min, pageSize);
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stack_size = stack_base - stack_min;
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// map memory
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pTable->allocate(stack_min, roundUp(stack_size, pageSize));
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// map out initial stack contents
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2009-12-31 21:30:51 +01:00
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IntType argv_array_base = stack_min + intSize; // room for argc
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IntType envp_array_base = argv_array_base + argv_array_size;
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IntType auxv_array_base = envp_array_base + envp_array_size;
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IntType arg_data_base = auxv_array_base + auxv_array_size;
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IntType env_data_base = arg_data_base + arg_data_size;
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2009-09-17 21:59:43 +02:00
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// write contents to stack
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2009-12-31 21:30:51 +01:00
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IntType argc = argv.size();
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2009-09-17 21:59:43 +02:00
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2009-12-31 21:30:51 +01:00
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argc = htog((IntType)argc);
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2009-09-17 21:59:43 +02:00
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initVirtMem->writeBlob(stack_min, (uint8_t*)&argc, intSize);
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copyStringArray(argv, argv_array_base, arg_data_base, initVirtMem);
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copyStringArray(envp, envp_array_base, env_data_base, initVirtMem);
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2009-12-31 21:30:51 +01:00
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// Copy the aux vector
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for (typename vector<auxv_t>::size_type x = 0; x < auxv.size(); x++) {
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initVirtMem->writeBlob(auxv_array_base + x * 2 * intSize,
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(uint8_t*)&(auxv[x].a_type), intSize);
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initVirtMem->writeBlob(auxv_array_base + (x * 2 + 1) * intSize,
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(uint8_t*)&(auxv[x].a_val), intSize);
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}
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// Write out the terminating zeroed auxilliary vector
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for (unsigned i = 0; i < 2; i++) {
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const IntType zero = 0;
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const Addr addr = auxv_array_base + 2 * intSize * (auxv.size() + i);
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initVirtMem->writeBlob(addr, (uint8_t*)&zero, intSize);
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}
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2009-09-17 21:59:43 +02:00
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ThreadContext *tc = system->getThreadContext(contextIds[0]);
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setSyscallArg(tc, 0, argc);
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setSyscallArg(tc, 1, argv_array_base);
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tc->setIntReg(StackPointerReg, stack_min);
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Addr prog_entry = objFile->entryPoint();
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tc->setPC(prog_entry);
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tc->setNextPC(prog_entry + sizeof(MachInst));
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tc->setNextNPC(prog_entry + (2 * sizeof(MachInst)));
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}
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2009-02-27 18:22:14 +01:00
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MipsISA::IntReg
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2009-10-30 08:44:55 +01:00
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MipsLiveProcess::getSyscallArg(ThreadContext *tc, int &i)
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2009-02-27 18:22:14 +01:00
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{
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assert(i < 6);
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2009-10-30 08:44:55 +01:00
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return tc->readIntReg(FirstArgumentReg + i++);
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2009-02-27 18:22:14 +01:00
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}
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void
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MipsLiveProcess::setSyscallArg(ThreadContext *tc,
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int i, MipsISA::IntReg val)
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{
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assert(i < 6);
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tc->setIntReg(FirstArgumentReg + i, val);
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}
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void
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MipsLiveProcess::setSyscallReturn(ThreadContext *tc,
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SyscallReturn return_value)
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{
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if (return_value.successful()) {
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// no error
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tc->setIntReg(SyscallSuccessReg, 0);
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tc->setIntReg(ReturnValueReg, return_value.value());
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} else {
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// got an error, return details
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tc->setIntReg(SyscallSuccessReg, (IntReg) -1);
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tc->setIntReg(ReturnValueReg, -return_value.value());
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}
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}
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