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gem5/src/mem/mem_object.hh

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Inital split up of the header files for the new memory system. Still need to fill in some of the include files, and other data types. But this will be the starting point. mem/bus.hh: Inital crack at a bus object that has ports. Still need to clean up the include file issues. mem/mem_object.hh: Decleration of a base memory object. Derives from simobject and adds a function to get the port associated with the object. mem/packet.hh: Inital crack at the packet decleration. Still need to clean up the include file issues. mem/port.hh: Inital crack at the port decleration. Still need to clean up the include file issues. mem/request.hh: Inital crack at the request decleration. Still need to clean up the include file issues. --HG-- extra : convert_revision : f17967d430458f91866a4639ab0cab45d835bb55
2006-01-31 18:12:49 +01:00
/*
MEM: Introduce the master/slave port sub-classes in C++ This patch introduces the notion of a master and slave port in the C++ code, thus bringing the previous classification from the Python classes into the corresponding simulation objects and memory objects. The patch enables us to classify behaviours into the two bins and add assumptions and enfore compliance, also simplifying the two interfaces. As a starting point, isSnooping is confined to a master port, and getAddrRanges to slave ports. More of these specilisations are to come in later patches. The getPort function is not getMasterPort and getSlavePort, and returns a port reference rather than a pointer as NULL would never be a valid return value. The default implementation of these two functions is placed in MemObject, and calls fatal. The one drawback with this specific patch is that it requires some code duplication, e.g. QueuedPort becomes QueuedMasterPort and QueuedSlavePort, and BusPort becomes BusMasterPort and BusSlavePort (avoiding multiple inheritance). With the later introduction of the port interfaces, moving the functionality outside the port itself, a lot of the duplicated code will disappear again.
2012-03-30 15:40:11 +02:00
* Copyright (c) 2012 ARM Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
* not be construed as granting a license to any other intellectual
* property including but not limited to intellectual property relating
* to a hardware implementation of the functionality of the software
* licensed hereunder. You may use the software subject to the license
* terms below provided that you ensure that this notice is replicated
* unmodified and in its entirety in all distributions of the software,
* modified or unmodified, in source code or in binary form.
*
Inital split up of the header files for the new memory system. Still need to fill in some of the include files, and other data types. But this will be the starting point. mem/bus.hh: Inital crack at a bus object that has ports. Still need to clean up the include file issues. mem/mem_object.hh: Decleration of a base memory object. Derives from simobject and adds a function to get the port associated with the object. mem/packet.hh: Inital crack at the packet decleration. Still need to clean up the include file issues. mem/port.hh: Inital crack at the port decleration. Still need to clean up the include file issues. mem/request.hh: Inital crack at the request decleration. Still need to clean up the include file issues. --HG-- extra : convert_revision : f17967d430458f91866a4639ab0cab45d835bb55
2006-01-31 18:12:49 +01:00
* Copyright (c) 2002-2005 The Regents of The University of Michigan
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met: redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer;
* redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution;
* neither the name of the copyright holders nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
Updated Authors from bk prs info --HG-- extra : convert_revision : 77f475b156d81c03a2811818fa23593d5615c685
2006-06-01 01:26:56 +02:00
*
* Authors: Ron Dreslinski
MEM: Introduce the master/slave port sub-classes in C++ This patch introduces the notion of a master and slave port in the C++ code, thus bringing the previous classification from the Python classes into the corresponding simulation objects and memory objects. The patch enables us to classify behaviours into the two bins and add assumptions and enfore compliance, also simplifying the two interfaces. As a starting point, isSnooping is confined to a master port, and getAddrRanges to slave ports. More of these specilisations are to come in later patches. The getPort function is not getMasterPort and getSlavePort, and returns a port reference rather than a pointer as NULL would never be a valid return value. The default implementation of these two functions is placed in MemObject, and calls fatal. The one drawback with this specific patch is that it requires some code duplication, e.g. QueuedPort becomes QueuedMasterPort and QueuedSlavePort, and BusPort becomes BusMasterPort and BusSlavePort (avoiding multiple inheritance). With the later introduction of the port interfaces, moving the functionality outside the port itself, a lot of the duplicated code will disappear again.
2012-03-30 15:40:11 +02:00
* Andreas Hansson
Inital split up of the header files for the new memory system. Still need to fill in some of the include files, and other data types. But this will be the starting point. mem/bus.hh: Inital crack at a bus object that has ports. Still need to clean up the include file issues. mem/mem_object.hh: Decleration of a base memory object. Derives from simobject and adds a function to get the port associated with the object. mem/packet.hh: Inital crack at the packet decleration. Still need to clean up the include file issues. mem/port.hh: Inital crack at the port decleration. Still need to clean up the include file issues. mem/request.hh: Inital crack at the request decleration. Still need to clean up the include file issues. --HG-- extra : convert_revision : f17967d430458f91866a4639ab0cab45d835bb55
2006-01-31 18:12:49 +01:00
*/
/**
* @file
MEM: Introduce the master/slave port sub-classes in C++ This patch introduces the notion of a master and slave port in the C++ code, thus bringing the previous classification from the Python classes into the corresponding simulation objects and memory objects. The patch enables us to classify behaviours into the two bins and add assumptions and enfore compliance, also simplifying the two interfaces. As a starting point, isSnooping is confined to a master port, and getAddrRanges to slave ports. More of these specilisations are to come in later patches. The getPort function is not getMasterPort and getSlavePort, and returns a port reference rather than a pointer as NULL would never be a valid return value. The default implementation of these two functions is placed in MemObject, and calls fatal. The one drawback with this specific patch is that it requires some code duplication, e.g. QueuedPort becomes QueuedMasterPort and QueuedSlavePort, and BusPort becomes BusMasterPort and BusSlavePort (avoiding multiple inheritance). With the later introduction of the port interfaces, moving the functionality outside the port itself, a lot of the duplicated code will disappear again.
2012-03-30 15:40:11 +02:00
* MemObject declaration.
Inital split up of the header files for the new memory system. Still need to fill in some of the include files, and other data types. But this will be the starting point. mem/bus.hh: Inital crack at a bus object that has ports. Still need to clean up the include file issues. mem/mem_object.hh: Decleration of a base memory object. Derives from simobject and adds a function to get the port associated with the object. mem/packet.hh: Inital crack at the packet decleration. Still need to clean up the include file issues. mem/port.hh: Inital crack at the port decleration. Still need to clean up the include file issues. mem/request.hh: Inital crack at the request decleration. Still need to clean up the include file issues. --HG-- extra : convert_revision : f17967d430458f91866a4639ab0cab45d835bb55
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*/
#ifndef __MEM_MEM_OBJECT_HH__
#define __MEM_MEM_OBJECT_HH__
Add proper includes --HG-- extra : convert_revision : c5f909d00b6025cd8f14544f7e2c9c50610c0cd3
2006-01-31 20:15:33 +01:00
#include "mem/port.hh"
Major changes to how SimObjects are created and initialized. Almost all creation and initialization now happens in python. Parameter objects are generated and initialized by python. The .ini file is now solely for debugging purposes and is not used in construction of the objects in any way. --HG-- extra : convert_revision : 7e722873e417cb3d696f2e34c35ff488b7bff4ed
2007-07-24 06:51:38 +02:00
#include "params/MemObject.hh"
Clock: Move the clock and related functions to ClockedObject This patch moves the clock of the CPU, bus, and numerous devices to the new class ClockedObject, that sits in between the SimObject and MemObject in the class hierarchy. Although there are currently a fair amount of MemObjects that do not make use of the clock, they potentially should do so, e.g. the caches should at some point have the same clock as the CPU, potentially with a 1:n ratio. This patch does not introduce any new clock objects or object hierarchies (clusters, clock domains etc), but is still a step in the direction of having a more structured approach clock domains. The most contentious part of this patch is the serialisation of clocks that some of the modules (but not all) did previously. This serialisation should not be needed as the clock is set through the parameters even when restoring from the checkpoint. In other words, the state is "stored" in the Python code that creates the modules. The nextCycle methods are also simplified and the clock phase parameter of the CPU is removed (this could be part of a clock object once they are introduced).
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#include "sim/clocked_object.hh"
Inital split up of the header files for the new memory system. Still need to fill in some of the include files, and other data types. But this will be the starting point. mem/bus.hh: Inital crack at a bus object that has ports. Still need to clean up the include file issues. mem/mem_object.hh: Decleration of a base memory object. Derives from simobject and adds a function to get the port associated with the object. mem/packet.hh: Inital crack at the packet decleration. Still need to clean up the include file issues. mem/port.hh: Inital crack at the port decleration. Still need to clean up the include file issues. mem/request.hh: Inital crack at the request decleration. Still need to clean up the include file issues. --HG-- extra : convert_revision : f17967d430458f91866a4639ab0cab45d835bb55
2006-01-31 18:12:49 +01:00
/**
Clock: Move the clock and related functions to ClockedObject This patch moves the clock of the CPU, bus, and numerous devices to the new class ClockedObject, that sits in between the SimObject and MemObject in the class hierarchy. Although there are currently a fair amount of MemObjects that do not make use of the clock, they potentially should do so, e.g. the caches should at some point have the same clock as the CPU, potentially with a 1:n ratio. This patch does not introduce any new clock objects or object hierarchies (clusters, clock domains etc), but is still a step in the direction of having a more structured approach clock domains. The most contentious part of this patch is the serialisation of clocks that some of the modules (but not all) did previously. This serialisation should not be needed as the clock is set through the parameters even when restoring from the checkpoint. In other words, the state is "stored" in the Python code that creates the modules. The nextCycle methods are also simplified and the clock phase parameter of the CPU is removed (this could be part of a clock object once they are introduced).
2012-08-21 11:49:01 +02:00
* The MemObject class extends the ClockedObject with accessor functions
MEM: Introduce the master/slave port sub-classes in C++ This patch introduces the notion of a master and slave port in the C++ code, thus bringing the previous classification from the Python classes into the corresponding simulation objects and memory objects. The patch enables us to classify behaviours into the two bins and add assumptions and enfore compliance, also simplifying the two interfaces. As a starting point, isSnooping is confined to a master port, and getAddrRanges to slave ports. More of these specilisations are to come in later patches. The getPort function is not getMasterPort and getSlavePort, and returns a port reference rather than a pointer as NULL would never be a valid return value. The default implementation of these two functions is placed in MemObject, and calls fatal. The one drawback with this specific patch is that it requires some code duplication, e.g. QueuedPort becomes QueuedMasterPort and QueuedSlavePort, and BusPort becomes BusMasterPort and BusSlavePort (avoiding multiple inheritance). With the later introduction of the port interfaces, moving the functionality outside the port itself, a lot of the duplicated code will disappear again.
2012-03-30 15:40:11 +02:00
* to get its master and slave ports.
Inital split up of the header files for the new memory system. Still need to fill in some of the include files, and other data types. But this will be the starting point. mem/bus.hh: Inital crack at a bus object that has ports. Still need to clean up the include file issues. mem/mem_object.hh: Decleration of a base memory object. Derives from simobject and adds a function to get the port associated with the object. mem/packet.hh: Inital crack at the packet decleration. Still need to clean up the include file issues. mem/port.hh: Inital crack at the port decleration. Still need to clean up the include file issues. mem/request.hh: Inital crack at the request decleration. Still need to clean up the include file issues. --HG-- extra : convert_revision : f17967d430458f91866a4639ab0cab45d835bb55
2006-01-31 18:12:49 +01:00
*/
Clock: Move the clock and related functions to ClockedObject This patch moves the clock of the CPU, bus, and numerous devices to the new class ClockedObject, that sits in between the SimObject and MemObject in the class hierarchy. Although there are currently a fair amount of MemObjects that do not make use of the clock, they potentially should do so, e.g. the caches should at some point have the same clock as the CPU, potentially with a 1:n ratio. This patch does not introduce any new clock objects or object hierarchies (clusters, clock domains etc), but is still a step in the direction of having a more structured approach clock domains. The most contentious part of this patch is the serialisation of clocks that some of the modules (but not all) did previously. This serialisation should not be needed as the clock is set through the parameters even when restoring from the checkpoint. In other words, the state is "stored" in the Python code that creates the modules. The nextCycle methods are also simplified and the clock phase parameter of the CPU is removed (this could be part of a clock object once they are introduced).
2012-08-21 11:49:01 +02:00
class MemObject : public ClockedObject
Inital split up of the header files for the new memory system. Still need to fill in some of the include files, and other data types. But this will be the starting point. mem/bus.hh: Inital crack at a bus object that has ports. Still need to clean up the include file issues. mem/mem_object.hh: Decleration of a base memory object. Derives from simobject and adds a function to get the port associated with the object. mem/packet.hh: Inital crack at the packet decleration. Still need to clean up the include file issues. mem/port.hh: Inital crack at the port decleration. Still need to clean up the include file issues. mem/request.hh: Inital crack at the request decleration. Still need to clean up the include file issues. --HG-- extra : convert_revision : f17967d430458f91866a4639ab0cab45d835bb55
2006-01-31 18:12:49 +01:00
{
Many changes that make the new mem system compile. Now to convert the rest of the tree to use the new mem system. mem/mem_object.hh: Create constrtor so it compiles mem/packet.hh: Fix typedefs so they compile, add in a few more headers for compilation mem/page_table.cc: convert to new mem system so it compiles mem/page_table.hh: fix it to the version that had asid support. Make it compile in the new system mem/physical.cc: Fix some compilation bugs mem/physical.hh: Add a type that made compile fail mem/port.hh: Fix a spelling error that messed up compilation mem/request.hh: fix typedefs and forward declerations so it compiles --HG-- extra : convert_revision : 580fb1ba31ada799ff0122601b8b5a8d994bb8af
2006-02-15 20:21:09 +01:00
public:
Major changes to how SimObjects are created and initialized. Almost all creation and initialization now happens in python. Parameter objects are generated and initialized by python. The .ini file is now solely for debugging purposes and is not used in construction of the objects in any way. --HG-- extra : convert_revision : 7e722873e417cb3d696f2e34c35ff488b7bff4ed
2007-07-24 06:51:38 +02:00
typedef MemObjectParams Params;
params: Get rid of the remnants of the old style parameter configuration stuff.
2008-08-11 21:22:17 +02:00
const Params *params() const
{ return dynamic_cast<const Params *>(_params); }
Major changes to how SimObjects are created and initialized. Almost all creation and initialization now happens in python. Parameter objects are generated and initialized by python. The .ini file is now solely for debugging purposes and is not used in construction of the objects in any way. --HG-- extra : convert_revision : 7e722873e417cb3d696f2e34c35ff488b7bff4ed
2007-07-24 06:51:38 +02:00
params: Get rid of the remnants of the old style parameter configuration stuff.
2008-08-11 21:22:17 +02:00
MemObject(const Params *params);
params: Deprecate old-style constructors; update most SimObject constructors. SimObjects not yet updated: - Process and subclasses - BaseCPU and subclasses The SimObject(const std::string &name) constructor was removed. Subclasses that still rely on that behavior must call the parent initializer as : SimObject(makeParams(name)) --HG-- extra : convert_revision : d6faddde76e7c3361ebdbd0a7b372a40941c12ed
2007-08-30 21:16:59 +02:00
MEM: Introduce the master/slave port sub-classes in C++ This patch introduces the notion of a master and slave port in the C++ code, thus bringing the previous classification from the Python classes into the corresponding simulation objects and memory objects. The patch enables us to classify behaviours into the two bins and add assumptions and enfore compliance, also simplifying the two interfaces. As a starting point, isSnooping is confined to a master port, and getAddrRanges to slave ports. More of these specilisations are to come in later patches. The getPort function is not getMasterPort and getSlavePort, and returns a port reference rather than a pointer as NULL would never be a valid return value. The default implementation of these two functions is placed in MemObject, and calls fatal. The one drawback with this specific patch is that it requires some code duplication, e.g. QueuedPort becomes QueuedMasterPort and QueuedSlavePort, and BusPort becomes BusMasterPort and BusSlavePort (avoiding multiple inheritance). With the later introduction of the port interfaces, moving the functionality outside the port itself, a lot of the duplicated code will disappear again.
2012-03-30 15:40:11 +02:00
/**
Port: Add protocol-agnostic ports in the port hierarchy This patch adds an additional level of ports in the inheritance hierarchy, separating out the protocol-specific and protocl-agnostic parts. All the functionality related to the binding of ports is now confined to use BaseMaster/BaseSlavePorts, and all the protocol-specific parts stay in the Master/SlavePort. In the future it will be possible to add other protocol-specific implementations. The functions used in the binding of ports, i.e. getMaster/SlavePort now use the base classes, and the index parameter is updated to use the PortID typedef with the symbolic InvalidPortID as the default.
2012-10-15 14:12:35 +02:00
* Get a master port with a given name and index. This is used at
* binding time and returns a reference to a protocol-agnostic
* base master port.
MEM: Introduce the master/slave port sub-classes in C++ This patch introduces the notion of a master and slave port in the C++ code, thus bringing the previous classification from the Python classes into the corresponding simulation objects and memory objects. The patch enables us to classify behaviours into the two bins and add assumptions and enfore compliance, also simplifying the two interfaces. As a starting point, isSnooping is confined to a master port, and getAddrRanges to slave ports. More of these specilisations are to come in later patches. The getPort function is not getMasterPort and getSlavePort, and returns a port reference rather than a pointer as NULL would never be a valid return value. The default implementation of these two functions is placed in MemObject, and calls fatal. The one drawback with this specific patch is that it requires some code duplication, e.g. QueuedPort becomes QueuedMasterPort and QueuedSlavePort, and BusPort becomes BusMasterPort and BusSlavePort (avoiding multiple inheritance). With the later introduction of the port interfaces, moving the functionality outside the port itself, a lot of the duplicated code will disappear again.
2012-03-30 15:40:11 +02:00
*
* @param if_name Port name
* @param idx Index in the case of a VectorPort
*
* @return A reference to the given port
*/
Port: Add protocol-agnostic ports in the port hierarchy This patch adds an additional level of ports in the inheritance hierarchy, separating out the protocol-specific and protocl-agnostic parts. All the functionality related to the binding of ports is now confined to use BaseMaster/BaseSlavePorts, and all the protocol-specific parts stay in the Master/SlavePort. In the future it will be possible to add other protocol-specific implementations. The functions used in the binding of ports, i.e. getMaster/SlavePort now use the base classes, and the index parameter is updated to use the PortID typedef with the symbolic InvalidPortID as the default.
2012-10-15 14:12:35 +02:00
virtual BaseMasterPort& getMasterPort(const std::string& if_name,
PortID idx = InvalidPortID);
MEM: Introduce the master/slave port sub-classes in C++ This patch introduces the notion of a master and slave port in the C++ code, thus bringing the previous classification from the Python classes into the corresponding simulation objects and memory objects. The patch enables us to classify behaviours into the two bins and add assumptions and enfore compliance, also simplifying the two interfaces. As a starting point, isSnooping is confined to a master port, and getAddrRanges to slave ports. More of these specilisations are to come in later patches. The getPort function is not getMasterPort and getSlavePort, and returns a port reference rather than a pointer as NULL would never be a valid return value. The default implementation of these two functions is placed in MemObject, and calls fatal. The one drawback with this specific patch is that it requires some code duplication, e.g. QueuedPort becomes QueuedMasterPort and QueuedSlavePort, and BusPort becomes BusMasterPort and BusSlavePort (avoiding multiple inheritance). With the later introduction of the port interfaces, moving the functionality outside the port itself, a lot of the duplicated code will disappear again.
2012-03-30 15:40:11 +02:00
/**
Port: Add protocol-agnostic ports in the port hierarchy This patch adds an additional level of ports in the inheritance hierarchy, separating out the protocol-specific and protocl-agnostic parts. All the functionality related to the binding of ports is now confined to use BaseMaster/BaseSlavePorts, and all the protocol-specific parts stay in the Master/SlavePort. In the future it will be possible to add other protocol-specific implementations. The functions used in the binding of ports, i.e. getMaster/SlavePort now use the base classes, and the index parameter is updated to use the PortID typedef with the symbolic InvalidPortID as the default.
2012-10-15 14:12:35 +02:00
* Get a slave port with a given name and index. This is used at
* binding time and returns a reference to a protocol-agnostic
* base master port.
MEM: Introduce the master/slave port sub-classes in C++ This patch introduces the notion of a master and slave port in the C++ code, thus bringing the previous classification from the Python classes into the corresponding simulation objects and memory objects. The patch enables us to classify behaviours into the two bins and add assumptions and enfore compliance, also simplifying the two interfaces. As a starting point, isSnooping is confined to a master port, and getAddrRanges to slave ports. More of these specilisations are to come in later patches. The getPort function is not getMasterPort and getSlavePort, and returns a port reference rather than a pointer as NULL would never be a valid return value. The default implementation of these two functions is placed in MemObject, and calls fatal. The one drawback with this specific patch is that it requires some code duplication, e.g. QueuedPort becomes QueuedMasterPort and QueuedSlavePort, and BusPort becomes BusMasterPort and BusSlavePort (avoiding multiple inheritance). With the later introduction of the port interfaces, moving the functionality outside the port itself, a lot of the duplicated code will disappear again.
2012-03-30 15:40:11 +02:00
*
* @param if_name Port name
* @param idx Index in the case of a VectorPort
*
* @return A reference to the given port
*/
Port: Add protocol-agnostic ports in the port hierarchy This patch adds an additional level of ports in the inheritance hierarchy, separating out the protocol-specific and protocl-agnostic parts. All the functionality related to the binding of ports is now confined to use BaseMaster/BaseSlavePorts, and all the protocol-specific parts stay in the Master/SlavePort. In the future it will be possible to add other protocol-specific implementations. The functions used in the binding of ports, i.e. getMaster/SlavePort now use the base classes, and the index parameter is updated to use the PortID typedef with the symbolic InvalidPortID as the default.
2012-10-15 14:12:35 +02:00
virtual BaseSlavePort& getSlavePort(const std::string& if_name,
PortID idx = InvalidPortID);
Inital split up of the header files for the new memory system. Still need to fill in some of the include files, and other data types. But this will be the starting point. mem/bus.hh: Inital crack at a bus object that has ports. Still need to clean up the include file issues. mem/mem_object.hh: Decleration of a base memory object. Derives from simobject and adds a function to get the port associated with the object. mem/packet.hh: Inital crack at the packet decleration. Still need to clean up the include file issues. mem/port.hh: Inital crack at the port decleration. Still need to clean up the include file issues. mem/request.hh: Inital crack at the request decleration. Still need to clean up the include file issues. --HG-- extra : convert_revision : f17967d430458f91866a4639ab0cab45d835bb55
2006-01-31 18:12:49 +01:00
};
#endif //__MEM_MEM_OBJECT_HH__
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