system.cpu.workload.num_syscalls 400 # Number of system calls
system.cpu.numCycles 260765781 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 172317810 # Number of instructions committed
system.cpu.committedOps 181650743 # Number of ops (including micro ops) committed
system.cpu.discardedOps 11583006 # Number of ops (including micro ops) which were discarded before commit
system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching
system.cpu.cpi 1.513284 # CPI: cycles per instruction
system.cpu.ipc 0.660815 # IPC: instructions per cycle
system.cpu.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
system.cpu.op_class_0::IntAlu 138988213 76.51% 76.51% # Class of committed instruction
system.cpu.op_class_0::IntMult 908940 0.50% 77.01% # Class of committed instruction
system.cpu.op_class_0::IntDiv 0 0.00% 77.01% # Class of committed instruction
system.cpu.op_class_0::FloatAdd 0 0.00% 77.01% # Class of committed instruction
system.cpu.op_class_0::FloatCmp 0 0.00% 77.01% # Class of committed instruction
system.cpu.op_class_0::FloatCvt 0 0.00% 77.01% # Class of committed instruction
system.cpu.op_class_0::FloatMult 0 0.00% 77.01% # Class of committed instruction
system.cpu.op_class_0::FloatDiv 0 0.00% 77.01% # Class of committed instruction
system.cpu.op_class_0::FloatSqrt 0 0.00% 77.01% # Class of committed instruction
system.cpu.op_class_0::SimdAdd 0 0.00% 77.01% # Class of committed instruction
system.cpu.op_class_0::SimdAddAcc 0 0.00% 77.01% # Class of committed instruction
system.cpu.op_class_0::SimdAlu 0 0.00% 77.01% # Class of committed instruction
system.cpu.op_class_0::SimdCmp 0 0.00% 77.01% # Class of committed instruction
system.cpu.op_class_0::SimdCvt 0 0.00% 77.01% # Class of committed instruction
system.cpu.op_class_0::SimdMisc 0 0.00% 77.01% # Class of committed instruction
system.cpu.op_class_0::SimdMult 0 0.00% 77.01% # Class of committed instruction
system.cpu.op_class_0::SimdMultAcc 0 0.00% 77.01% # Class of committed instruction
system.cpu.op_class_0::SimdShift 0 0.00% 77.01% # Class of committed instruction
system.cpu.op_class_0::SimdShiftAcc 0 0.00% 77.01% # Class of committed instruction
system.cpu.op_class_0::SimdSqrt 0 0.00% 77.01% # Class of committed instruction
system.cpu.op_class_0::SimdFloatAdd 32754 0.02% 77.03% # Class of committed instruction
system.cpu.op_class_0::SimdFloatAlu 0 0.00% 77.03% # Class of committed instruction
system.cpu.op_class_0::SimdFloatCmp 154829 0.09% 77.12% # Class of committed instruction
system.cpu.op_class_0::SimdFloatCvt 238880 0.13% 77.25% # Class of committed instruction
system.cpu.op_class_0::SimdFloatDiv 76016 0.04% 77.29% # Class of committed instruction
system.cpu.op_class_0::SimdFloatMisc 437591 0.24% 77.53% # Class of committed instruction
system.cpu.op_class_0::SimdFloatMult 200806 0.11% 77.64% # Class of committed instruction
system.cpu.op_class_0::SimdFloatMultAcc 71617 0.04% 77.68% # Class of committed instruction
system.cpu.op_class_0::SimdFloatSqrt 318 0.00% 77.68% # Class of committed instruction
system.cpu.op_class_0::MemRead 27896144 15.36% 93.04% # Class of committed instruction
system.cpu.op_class_0::MemWrite 12644635 6.96% 100.00% # Class of committed instruction
system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
system.cpu.op_class_0::total 181650743 # Class of committed instruction
system.cpu.tickCycles 254551967 # Number of cycles that the object actually ticked
system.cpu.idleCycles 6213814 # Total number of cycles that the object has spent stopped
system.cpu.dcache.tags.replacements 42 # number of replacements
system.cpu.dcache.tags.tagsinuse 1378.689350 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 40754473 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 1811 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 22503.850359 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data 1378.689350 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.336594 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.336594 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 1769 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0 18 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1 38 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2 83 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::3 271 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::4 1359 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 0.431885 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 81515639 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 81515639 # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data 28346557 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 28346557 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 12362640 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 12362640 # number of WriteReq hits
system.cpu.dcache.SoftPFReq_hits::cpu.data 462 # number of SoftPFReq hits
system.cpu.dcache.SoftPFReq_hits::total 462 # number of SoftPFReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data 22407 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total 22407 # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data 22407 # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total 22407 # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data 40709197 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 40709197 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 40709659 # number of overall hits
system.cpu.dcache.overall_hits::total 40709659 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 793 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 793 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 1647 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 1647 # number of WriteReq misses
system.cpu.dcache.SoftPFReq_misses::cpu.data 1 # number of SoftPFReq misses
system.cpu.dcache.SoftPFReq_misses::total 1 # number of SoftPFReq misses
system.cpu.dcache.demand_misses::cpu.data 2440 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 2440 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 2441 # number of overall misses
system.cpu.dcache.overall_misses::total 2441 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 59629000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 59629000 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 126003000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 126003000 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 185632000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 185632000 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 185632000 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 185632000 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 28347350 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 28347350 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 12364287 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 12364287 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::cpu.data 463 # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::total 463 # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 22407 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total 22407 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data 22407 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total 22407 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 40711637 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 40711637 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 40712100 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 40712100 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000028 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.000028 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000133 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.000133 # miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.002160 # miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::total 0.002160 # miss rate for SoftPFReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.000060 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.000060 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.000060 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.000060 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 75194.199243 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 75194.199243 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 76504.553734 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 76504.553734 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 76078.688525 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 76078.688525 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 76047.521508 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 76047.521508 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.writebacks::writebacks 16 # number of writebacks
system.cpu.dcache.writebacks::total 16 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 82 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 82 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 548 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 548 # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data 630 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 630 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 630 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 630 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 711 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 711 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1099 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 1099 # number of WriteReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1 # number of SoftPFReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::total 1 # number of SoftPFReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 1810 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 1810 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 1811 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 1811 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 52555500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 52555500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 85213000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 85213000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 70000 # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 70000 # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 137768500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 137768500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 137838500 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 137838500 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000025 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000089 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000089 # mshr miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.002160 # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.002160 # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000044 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.000044 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000044 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.000044 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 73917.721519 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 73917.721519 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 77536.851683 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 77536.851683 # average WriteReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 70000 # average SoftPFReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 70000 # average SoftPFReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 76115.193370 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 76115.193370 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 76111.816676 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 76111.816676 # average overall mshr miss latency
system.cpu.icache.tags.replacements 2881 # number of replacements
system.cpu.icache.tags.tagsinuse 1423.942746 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 70779397 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 4677 # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs 15133.503742 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst 1423.942746 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.695285 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.695285 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024 1796 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0 51 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1 59 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::2 496 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::3 122 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::4 1068 # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024 0.876953 # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses 141572827 # Number of tag accesses
system.cpu.icache.tags.data_accesses 141572827 # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst 70779397 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 70779397 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 70779397 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 70779397 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 70779397 # number of overall hits
system.cpu.icache.overall_hits::total 70779397 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 4678 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 4678 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 4678 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 4678 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 4678 # number of overall misses
system.cpu.icache.overall_misses::total 4678 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 198432500 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 198432500 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 198432500 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 198432500 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 198432500 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 198432500 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 70784075 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 70784075 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 70784075 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 70784075 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 70784075 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 70784075 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000066 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.000066 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.000066 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.000066 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.000066 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.000066 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 42418.234288 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 42418.234288 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 42418.234288 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 42418.234288 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 42418.234288 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 42418.234288 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.writebacks::writebacks 2881 # number of writebacks
system.cpu.icache.writebacks::total 2881 # number of writebacks
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 4678 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 4678 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 4678 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 4678 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 4678 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 4678 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 193755500 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 193755500 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 193755500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 193755500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 193755500 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 193755500 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000066 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000066 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000066 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.000066 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000066 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.000066 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 41418.448055 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 41418.448055 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 41418.448055 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 41418.448055 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 41418.448055 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 41418.448055 # average overall mshr miss latency
system.cpu.l2cache.tags.replacements 0 # number of replacements
system.cpu.l2cache.tags.tagsinuse 1999.548128 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 5178 # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs 2783 # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs 1.860582 # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks 3.029345 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst 1506.706963 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 489.811820 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks 0.000092 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.045981 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data 0.014948 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total 0.061021 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1024 2783 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 37 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 68 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 526 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 149 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2003 # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.084930 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 76554 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 76554 # Number of data accesses
system.cpu.l2cache.WritebackDirty_hits::writebacks 16 # number of WritebackDirty hits
system.cpu.l2cache.WritebackDirty_hits::total 16 # number of WritebackDirty hits
system.cpu.l2cache.WritebackClean_hits::writebacks 2559 # number of WritebackClean hits
system.cpu.l2cache.WritebackClean_hits::total 2559 # number of WritebackClean hits
system.cpu.l2cache.ReadExReq_hits::cpu.data 8 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total 8 # number of ReadExReq hits
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 2517 # number of ReadCleanReq hits
system.cpu.l2cache.ReadCleanReq_hits::total 2517 # number of ReadCleanReq hits
system.cpu.l2cache.ReadSharedReq_hits::cpu.data 81 # number of ReadSharedReq hits
system.cpu.l2cache.ReadSharedReq_hits::total 81 # number of ReadSharedReq hits
system.cpu.l2cache.demand_hits::cpu.inst 2517 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data 89 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 2606 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst 2517 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data 89 # number of overall hits
system.cpu.l2cache.overall_hits::total 2606 # number of overall hits
system.cpu.l2cache.ReadExReq_misses::cpu.data 1091 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 1091 # number of ReadExReq misses
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 2161 # number of ReadCleanReq misses
system.cpu.l2cache.ReadCleanReq_misses::total 2161 # number of ReadCleanReq misses
system.cpu.l2cache.ReadSharedReq_misses::cpu.data 631 # number of ReadSharedReq misses
system.cpu.l2cache.ReadSharedReq_misses::total 631 # number of ReadSharedReq misses
system.cpu.l2cache.demand_misses::cpu.inst 2161 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 1722 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 3883 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst 2161 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 1722 # number of overall misses
system.cpu.l2cache.overall_misses::total 3883 # number of overall misses
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 83479000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 83479000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 159937500 # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::total 159937500 # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 50622000 # number of ReadSharedReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::total 50622000 # number of ReadSharedReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 159937500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 134101000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 294038500 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 159937500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 134101000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 294038500 # number of overall miss cycles
system.cpu.l2cache.WritebackDirty_accesses::writebacks 16 # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackDirty_accesses::total 16 # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::writebacks 2559 # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::total 2559 # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data 1099 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 1099 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 4678 # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::total 4678 # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 712 # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::total 712 # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst 4678 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 1811 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 6489 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 4678 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 1811 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 6489 # number of overall (read+write) accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.992721 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 0.992721 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.461950 # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.461950 # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.886236 # miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.886236 # miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.461950 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.950856 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.598397 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.461950 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.950856 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.598397 # miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 76516.040330 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 76516.040330 # average ReadExReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 74010.874595 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 74010.874595 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 80225.039620 # average ReadSharedReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 80225.039620 # average ReadSharedReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74010.874595 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 77875.145180 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 75724.568633 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74010.874595 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77875.145180 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 75724.568633 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 2 # number of ReadCleanReq MSHR hits
system.cpu.l2cache.ReadCleanReq_mshr_hits::total 2 # number of ReadCleanReq MSHR hits
system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 14 # number of ReadSharedReq MSHR hits
system.cpu.l2cache.ReadSharedReq_mshr_hits::total 14 # number of ReadSharedReq MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.inst 2 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.data 14 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::total 16 # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.inst 2 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.data 14 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::total 16 # number of overall MSHR hits
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1091 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 1091 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 2159 # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::total 2159 # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 617 # number of ReadSharedReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::total 617 # number of ReadSharedReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 2159 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 1708 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 3867 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 2159 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 1708 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 3867 # number of overall MSHR misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 72569000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 72569000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 138134000 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 138134000 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 43490000 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 43490000 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 138134000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 116059000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 254193000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 138134000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 116059000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 254193000 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.992721 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.992721 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.461522 # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.461522 # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.866573 # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.866573 # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.461522 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.943125 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.595932 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.461522 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.943125 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.595932 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 66516.040330 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 66516.040330 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 63980.546549 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 63980.546549 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70486.223663 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70486.223663 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 63980.546549 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67950.234192 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65733.902250 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 63980.546549 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67950.234192 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65733.902250 # average overall mshr miss latency
system.cpu.toL2Bus.snoop_filter.tot_requests 9412 # Total number of requests made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_requests 3057 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 328 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.trans_dist::ReadResp 5389 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackDirty 16 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackClean 2881 # Transaction distribution
system.cpu.toL2Bus.trans_dist::CleanEvict 26 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 1099 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 1099 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadCleanReq 4678 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadSharedReq 712 # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 12236 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3664 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 15900 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 483712 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 116928 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total 600640 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops 0 # Total snoops (count)