system.cpu.workload.num_syscalls 389 # Number of system calls
system.cpu.numCycles 103811269 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 91903089 # Number of instructions committed
system.cpu.committedOps 91903089 # Number of ops (including micro ops) committed
system.cpu.discardedOps 2181586 # Number of ops (including micro ops) which were discarded before commit
system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching
system.cpu.cpi 1.129573 # CPI: cycles per instruction
system.cpu.ipc 0.885290 # IPC: instructions per cycle
system.cpu.op_class_0::No_OpClass 7723353 8.40% 8.40% # Class of committed instruction
system.cpu.op_class_0::IntAlu 51001454 55.49% 63.90% # Class of committed instruction
system.cpu.op_class_0::IntMult 458252 0.50% 64.40% # Class of committed instruction
system.cpu.op_class_0::IntDiv 0 0.00% 64.40% # Class of committed instruction
system.cpu.op_class_0::FloatAdd 2732553 2.97% 67.37% # Class of committed instruction
system.cpu.op_class_0::FloatCmp 104605 0.11% 67.48% # Class of committed instruction
system.cpu.op_class_0::FloatCvt 2333953 2.54% 70.02% # Class of committed instruction
system.cpu.op_class_0::FloatMult 296445 0.32% 70.35% # Class of committed instruction
system.cpu.op_class_0::FloatDiv 754822 0.82% 71.17% # Class of committed instruction
system.cpu.op_class_0::FloatSqrt 318 0.00% 71.17% # Class of committed instruction
system.cpu.op_class_0::SimdAdd 0 0.00% 71.17% # Class of committed instruction
system.cpu.op_class_0::SimdAddAcc 0 0.00% 71.17% # Class of committed instruction
system.cpu.op_class_0::SimdAlu 0 0.00% 71.17% # Class of committed instruction
system.cpu.op_class_0::SimdCmp 0 0.00% 71.17% # Class of committed instruction
system.cpu.op_class_0::SimdCvt 0 0.00% 71.17% # Class of committed instruction
system.cpu.op_class_0::SimdMisc 0 0.00% 71.17% # Class of committed instruction
system.cpu.op_class_0::SimdMult 0 0.00% 71.17% # Class of committed instruction
system.cpu.op_class_0::SimdMultAcc 0 0.00% 71.17% # Class of committed instruction
system.cpu.op_class_0::SimdShift 0 0.00% 71.17% # Class of committed instruction
system.cpu.op_class_0::SimdShiftAcc 0 0.00% 71.17% # Class of committed instruction
system.cpu.op_class_0::SimdSqrt 0 0.00% 71.17% # Class of committed instruction
system.cpu.op_class_0::SimdFloatAdd 0 0.00% 71.17% # Class of committed instruction
system.cpu.op_class_0::SimdFloatAlu 0 0.00% 71.17% # Class of committed instruction
system.cpu.op_class_0::SimdFloatCmp 0 0.00% 71.17% # Class of committed instruction
system.cpu.op_class_0::SimdFloatCvt 0 0.00% 71.17% # Class of committed instruction
system.cpu.op_class_0::SimdFloatDiv 0 0.00% 71.17% # Class of committed instruction
system.cpu.op_class_0::SimdFloatMisc 0 0.00% 71.17% # Class of committed instruction
system.cpu.op_class_0::SimdFloatMult 0 0.00% 71.17% # Class of committed instruction
system.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 71.17% # Class of committed instruction
system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 71.17% # Class of committed instruction
system.cpu.op_class_0::MemRead 19996208 21.76% 92.93% # Class of committed instruction
system.cpu.op_class_0::MemWrite 6501126 7.07% 100.00% # Class of committed instruction
system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
system.cpu.op_class_0::total 91903089 # Class of committed instruction
system.cpu.tickCycles 102098443 # Number of cycles that the object actually ticked
system.cpu.idleCycles 1712826 # Total number of cycles that the object has spent stopped
system.cpu.dcache.tags.replacements 157 # number of replacements
system.cpu.dcache.tags.tagsinuse 1447.414267 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 26572424 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 2230 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 11915.885202 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data 1447.414267 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.353373 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.353373 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 2073 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0 19 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1 43 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2 227 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::3 405 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::4 1379 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 0.506104 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 53153936 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 53153936 # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data 20074229 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 20074229 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 6498195 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 6498195 # number of WriteReq hits
system.cpu.dcache.demand_hits::cpu.data 26572424 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 26572424 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 26572424 # number of overall hits
system.cpu.dcache.overall_hits::total 26572424 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 521 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 521 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 2908 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 2908 # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data 3429 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 3429 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 3429 # number of overall misses
system.cpu.dcache.overall_misses::total 3429 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 40464500 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 40464500 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 214055500 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 214055500 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 254520000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 254520000 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 254520000 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 254520000 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 20074750 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 20074750 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 6501103 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 6501103 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 26575853 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 26575853 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 26575853 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 26575853 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000026 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.000026 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000447 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.000447 # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.000129 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.000129 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.000129 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.000129 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 77666.986564 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 77666.986564 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 73609.181568 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 73609.181568 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 74225.721785 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 74225.721785 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 74225.721785 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 74225.721785 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.writebacks::writebacks 107 # number of writebacks
system.cpu.dcache.writebacks::total 107 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 36 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 36 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1163 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 1163 # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data 1199 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 1199 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 1199 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 1199 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 485 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 485 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1745 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 1745 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 2230 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 2230 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 2230 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 2230 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 36953000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 36953000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 131397000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 131397000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 168350000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 168350000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 168350000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 168350000 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000024 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000024 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000268 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000268 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000084 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.000084 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000084 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.000084 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 76191.752577 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 76191.752577 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 75299.140401 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 75299.140401 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 75493.273543 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 75493.273543 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 75493.273543 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 75493.273543 # average overall mshr miss latency
system.cpu.icache.tags.replacements 13853 # number of replacements
system.cpu.icache.tags.tagsinuse 1642.330146 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 22935687 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 15818 # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs 1449.973891 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst 1642.330146 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.801919 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.801919 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024 1965 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0 54 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1 143 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::2 672 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::3 150 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::4 946 # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024 0.959473 # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses 45918830 # Number of tag accesses
system.cpu.icache.tags.data_accesses 45918830 # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst 22935687 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 22935687 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 22935687 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 22935687 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 22935687 # number of overall hits
system.cpu.icache.overall_hits::total 22935687 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 15819 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 15819 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 15819 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 15819 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 15819 # number of overall misses
system.cpu.icache.overall_misses::total 15819 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 406827000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 406827000 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 406827000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 406827000 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 406827000 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 406827000 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 22951506 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 22951506 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 22951506 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 22951506 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 22951506 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 22951506 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000689 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.000689 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.000689 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.000689 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.000689 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.000689 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 25717.618054 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 25717.618054 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 25717.618054 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 25717.618054 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 25717.618054 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 25717.618054 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.writebacks::writebacks 13853 # number of writebacks
system.cpu.icache.writebacks::total 13853 # number of writebacks
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 15819 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 15819 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 15819 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 15819 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 15819 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 15819 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 391009000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 391009000 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 391009000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 391009000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 391009000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 391009000 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000689 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000689 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000689 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.000689 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000689 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.000689 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 24717.681269 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 24717.681269 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 24717.681269 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 24717.681269 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 24717.681269 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 24717.681269 # average overall mshr miss latency
system.cpu.l2cache.tags.replacements 0 # number of replacements
system.cpu.l2cache.tags.tagsinuse 2479.710860 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 26619 # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs 3667 # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs 7.259067 # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks 17.780381 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst 2101.965355 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 359.965124 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks 0.000543 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.064147 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data 0.010985 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total 0.075675 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1024 3667 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 65 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 142 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 770 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 183 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2507 # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.111908 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 261876 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 261876 # Number of data accesses
system.cpu.l2cache.WritebackDirty_hits::writebacks 107 # number of WritebackDirty hits
system.cpu.l2cache.WritebackDirty_hits::total 107 # number of WritebackDirty hits
system.cpu.l2cache.WritebackClean_hits::writebacks 13853 # number of WritebackClean hits
system.cpu.l2cache.WritebackClean_hits::total 13853 # number of WritebackClean hits
system.cpu.l2cache.ReadExReq_hits::cpu.data 26 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total 26 # number of ReadExReq hits
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 12649 # number of ReadCleanReq hits
system.cpu.l2cache.ReadCleanReq_hits::total 12649 # number of ReadCleanReq hits
system.cpu.l2cache.ReadSharedReq_hits::cpu.data 53 # number of ReadSharedReq hits
system.cpu.l2cache.ReadSharedReq_hits::total 53 # number of ReadSharedReq hits
system.cpu.l2cache.demand_hits::cpu.inst 12649 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data 79 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 12728 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst 12649 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data 79 # number of overall hits
system.cpu.l2cache.overall_hits::total 12728 # number of overall hits
system.cpu.l2cache.ReadExReq_misses::cpu.data 1719 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 1719 # number of ReadExReq misses
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 3169 # number of ReadCleanReq misses
system.cpu.l2cache.ReadCleanReq_misses::total 3169 # number of ReadCleanReq misses
system.cpu.l2cache.ReadSharedReq_misses::cpu.data 432 # number of ReadSharedReq misses
system.cpu.l2cache.ReadSharedReq_misses::total 432 # number of ReadSharedReq misses
system.cpu.l2cache.demand_misses::cpu.inst 3169 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 2151 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 5320 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst 3169 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 2151 # number of overall misses
system.cpu.l2cache.overall_misses::total 5320 # number of overall misses
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 128506000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 128506000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 234465500 # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::total 234465500 # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 35663000 # number of ReadSharedReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::total 35663000 # number of ReadSharedReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 234465500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 164169000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 398634500 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 234465500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 164169000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 398634500 # number of overall miss cycles
system.cpu.l2cache.WritebackDirty_accesses::writebacks 107 # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackDirty_accesses::total 107 # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::writebacks 13853 # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::total 13853 # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data 1745 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 1745 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 15818 # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::total 15818 # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 485 # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::total 485 # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst 15818 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 2230 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 18048 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 15818 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 2230 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 18048 # number of overall (read+write) accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.985100 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 0.985100 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.200341 # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.200341 # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.890722 # miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.890722 # miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.200341 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.964574 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.294770 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.200341 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.964574 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.294770 # miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74756.253636 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74756.253636 # average ReadExReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 73987.219943 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 73987.219943 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 82553.240741 # average ReadSharedReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 82553.240741 # average ReadSharedReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 73987.219943 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76322.175732 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 74931.296992 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 73987.219943 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76322.175732 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 74931.296992 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1719 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 1719 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 3169 # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::total 3169 # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 432 # number of ReadSharedReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::total 432 # number of ReadSharedReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 3169 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 2151 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 5320 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 3169 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 2151 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 5320 # number of overall MSHR misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 111316000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 111316000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 202775500 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 202775500 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 31343000 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 31343000 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 202775500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 142659000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 345434500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 202775500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 142659000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 345434500 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.985100 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.985100 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.200341 # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.200341 # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.890722 # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.890722 # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.200341 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.964574 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.294770 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.200341 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.964574 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.294770 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64756.253636 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64756.253636 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 63987.219943 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 63987.219943 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 72553.240741 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 72553.240741 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 63987.219943 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 66322.175732 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 64931.296992 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 63987.219943 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 66322.175732 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 64931.296992 # average overall mshr miss latency
system.cpu.toL2Bus.snoop_filter.tot_requests 32058 # Total number of requests made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_requests 14010 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.trans_dist::ReadResp 16303 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackDirty 107 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackClean 13853 # Transaction distribution
system.cpu.toL2Bus.trans_dist::CleanEvict 50 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 1745 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 1745 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadCleanReq 15818 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadSharedReq 485 # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 45489 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4617 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 50106 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1898944 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 149568 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total 2048512 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops 0 # Total snoops (count)