system.cpu.workload.num_syscalls 29 # Number of system calls
system.cpu.numCycles 2417555389 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 1826378509 # Number of instructions committed
system.cpu.committedOps 1826378509 # Number of ops (including micro ops) committed
system.cpu.discardedOps 51811935 # Number of ops (including micro ops) which were discarded before commit
system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching
system.cpu.cpi 1.323688 # CPI: cycles per instruction
system.cpu.ipc 0.755465 # IPC: instructions per cycle
system.cpu.op_class_0::No_OpClass 83736345 4.58% 4.58% # Class of committed instruction
system.cpu.op_class_0::IntAlu 1129914150 61.87% 66.45% # Class of committed instruction
system.cpu.op_class_0::IntMult 75 0.00% 66.45% # Class of committed instruction
system.cpu.op_class_0::IntDiv 0 0.00% 66.45% # Class of committed instruction
system.cpu.op_class_0::FloatAdd 805244 0.04% 66.50% # Class of committed instruction
system.cpu.op_class_0::FloatCmp 13 0.00% 66.50% # Class of committed instruction
system.cpu.op_class_0::FloatCvt 100 0.00% 66.50% # Class of committed instruction
system.cpu.op_class_0::FloatMult 11 0.00% 66.50% # Class of committed instruction
system.cpu.op_class_0::FloatDiv 24 0.00% 66.50% # Class of committed instruction
system.cpu.op_class_0::FloatSqrt 0 0.00% 66.50% # Class of committed instruction
system.cpu.op_class_0::SimdAdd 0 0.00% 66.50% # Class of committed instruction
system.cpu.op_class_0::SimdAddAcc 0 0.00% 66.50% # Class of committed instruction
system.cpu.op_class_0::SimdAlu 0 0.00% 66.50% # Class of committed instruction
system.cpu.op_class_0::SimdCmp 0 0.00% 66.50% # Class of committed instruction
system.cpu.op_class_0::SimdCvt 0 0.00% 66.50% # Class of committed instruction
system.cpu.op_class_0::SimdMisc 0 0.00% 66.50% # Class of committed instruction
system.cpu.op_class_0::SimdMult 0 0.00% 66.50% # Class of committed instruction
system.cpu.op_class_0::SimdMultAcc 0 0.00% 66.50% # Class of committed instruction
system.cpu.op_class_0::SimdShift 0 0.00% 66.50% # Class of committed instruction
system.cpu.op_class_0::SimdShiftAcc 0 0.00% 66.50% # Class of committed instruction
system.cpu.op_class_0::SimdSqrt 0 0.00% 66.50% # Class of committed instruction
system.cpu.op_class_0::SimdFloatAdd 0 0.00% 66.50% # Class of committed instruction
system.cpu.op_class_0::SimdFloatAlu 0 0.00% 66.50% # Class of committed instruction
system.cpu.op_class_0::SimdFloatCmp 0 0.00% 66.50% # Class of committed instruction
system.cpu.op_class_0::SimdFloatCvt 0 0.00% 66.50% # Class of committed instruction
system.cpu.op_class_0::SimdFloatDiv 0 0.00% 66.50% # Class of committed instruction
system.cpu.op_class_0::SimdFloatMisc 0 0.00% 66.50% # Class of committed instruction
system.cpu.op_class_0::SimdFloatMult 0 0.00% 66.50% # Class of committed instruction
system.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 66.50% # Class of committed instruction
system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 66.50% # Class of committed instruction
system.cpu.op_class_0::MemRead 449492741 24.61% 91.11% # Class of committed instruction
system.cpu.op_class_0::MemWrite 162429806 8.89% 100.00% # Class of committed instruction
system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
system.cpu.op_class_0::total 1826378509 # Class of committed instruction
system.cpu.tickCycles 2075251932 # Number of cycles that the object actually ticked
system.cpu.idleCycles 342303457 # Total number of cycles that the object has spent stopped
system.cpu.dcache.tags.replacements 9121974 # number of replacements
system.cpu.dcache.tags.tagsinuse 4080.726355 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 601538856 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 9126070 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 65.914337 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 16821281500 # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data 4080.726355 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.996271 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.996271 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0 56 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1 1562 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2 2407 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::3 71 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 1231275880 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 1231275880 # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data 443056865 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 443056865 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 158481991 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 158481991 # number of WriteReq hits
system.cpu.dcache.demand_hits::cpu.data 601538856 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 601538856 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 601538856 # number of overall hits
system.cpu.dcache.overall_hits::total 601538856 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 7289538 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 7289538 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 2246511 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 2246511 # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data 9536049 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 9536049 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 9536049 # number of overall misses
system.cpu.dcache.overall_misses::total 9536049 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 185480529000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 185480529000 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 108417025500 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 108417025500 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 293897554500 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 293897554500 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 293897554500 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 293897554500 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 450346403 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 450346403 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 160728502 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 160728502 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 611074905 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 611074905 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 611074905 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 611074905 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.016187 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.016187 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.013977 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.013977 # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.015605 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.015605 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.015605 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.015605 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 25444.757816 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 25444.757816 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 48260.180119 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 48260.180119 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 30819.635522 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 30819.635522 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 30819.635522 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 30819.635522 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.writebacks::writebacks 3686603 # number of writebacks
system.cpu.dcache.writebacks::total 3686603 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 50808 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 50808 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 359171 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 359171 # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data 409979 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 409979 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 409979 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 409979 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7238730 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 7238730 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1887340 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 1887340 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 9126070 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 9126070 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 9126070 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 9126070 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 177011068000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 177011068000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 83258719000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 83258719000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 260269787000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 260269787000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 260269787000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 260269787000 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.016074 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.016074 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.011742 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.011742 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.014934 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.014934 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.014934 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.014934 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 24453.332007 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 24453.332007 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44114.319095 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44114.319095 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28519.372194 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 28519.372194 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 28519.372194 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 28519.372194 # average overall mshr miss latency
system.cpu.icache.tags.replacements 3 # number of replacements
system.cpu.icache.tags.tagsinuse 750.173547 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 597988654 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 958 # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs 624205.275574 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst 750.173547 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.366296 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.366296 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024 955 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0 81 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::4 874 # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024 0.466309 # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses 1195980182 # Number of tag accesses
system.cpu.icache.tags.data_accesses 1195980182 # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst 597988654 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 597988654 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 597988654 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 597988654 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 597988654 # number of overall hits
system.cpu.icache.overall_hits::total 597988654 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 958 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 958 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 958 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 958 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 958 # number of overall misses
system.cpu.icache.overall_misses::total 958 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 76338000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 76338000 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 76338000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 76338000 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 76338000 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 76338000 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 597989612 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 597989612 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 597989612 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 597989612 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 597989612 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 597989612 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000002 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.000002 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.000002 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.000002 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.000002 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.000002 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 79684.759916 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 79684.759916 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 79684.759916 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 79684.759916 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 79684.759916 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 79684.759916 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.writebacks::writebacks 3 # number of writebacks
system.cpu.icache.writebacks::total 3 # number of writebacks
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 958 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 958 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 958 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 958 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 958 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 958 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 75380000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 75380000 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 75380000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 75380000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 75380000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 75380000 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000002 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.000002 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.000002 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 78684.759916 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 78684.759916 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 78684.759916 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 78684.759916 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 78684.759916 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 78684.759916 # average overall mshr miss latency
system.cpu.l2cache.tags.replacements 1920891 # number of replacements
system.cpu.l2cache.tags.tagsinuse 30765.315888 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 14409692 # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs 1950696 # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs 7.386949 # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle 89219766000 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks 14798.392410 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst 42.817395 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 15924.106083 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks 0.451611 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.001307 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data 0.485965 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total 0.938883 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1024 29805 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 155 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 36 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1217 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 12865 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 15532 # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.909576 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 149830076 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 149830076 # Number of data accesses
system.cpu.l2cache.WritebackDirty_hits::writebacks 3686603 # number of WritebackDirty hits
system.cpu.l2cache.WritebackDirty_hits::total 3686603 # number of WritebackDirty hits
system.cpu.l2cache.WritebackClean_hits::writebacks 3 # number of WritebackClean hits
system.cpu.l2cache.WritebackClean_hits::total 3 # number of WritebackClean hits
system.cpu.l2cache.ReadExReq_hits::cpu.data 1106830 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total 1106830 # number of ReadExReq hits
system.cpu.l2cache.ReadSharedReq_hits::cpu.data 6066582 # number of ReadSharedReq hits
system.cpu.l2cache.ReadSharedReq_hits::total 6066582 # number of ReadSharedReq hits
system.cpu.l2cache.demand_hits::cpu.data 7173412 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 7173412 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.data 7173412 # number of overall hits
system.cpu.l2cache.overall_hits::total 7173412 # number of overall hits
system.cpu.l2cache.ReadExReq_misses::cpu.data 780510 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 780510 # number of ReadExReq misses
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 958 # number of ReadCleanReq misses
system.cpu.l2cache.ReadCleanReq_misses::total 958 # number of ReadCleanReq misses
system.cpu.l2cache.ReadSharedReq_misses::cpu.data 1172148 # number of ReadSharedReq misses
system.cpu.l2cache.ReadSharedReq_misses::total 1172148 # number of ReadSharedReq misses
system.cpu.l2cache.demand_misses::cpu.inst 958 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 1952658 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 1953616 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst 958 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 1952658 # number of overall misses
system.cpu.l2cache.overall_misses::total 1953616 # number of overall misses
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 68734828000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 68734828000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 73941000 # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::total 73941000 # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 102426227000 # number of ReadSharedReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::total 102426227000 # number of ReadSharedReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 73941000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 171161055000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 171234996000 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 73941000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 171161055000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 171234996000 # number of overall miss cycles
system.cpu.l2cache.WritebackDirty_accesses::writebacks 3686603 # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackDirty_accesses::total 3686603 # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::writebacks 3 # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::total 3 # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data 1887340 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 1887340 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 958 # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::total 958 # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 7238730 # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::total 7238730 # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst 958 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 9126070 # number of demand (read+write) accesses
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system.cpu.l2cache.overall_accesses::cpu.inst 958 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 9126070 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 9127028 # number of overall (read+write) accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.413550 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 0.413550 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 1 # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::total 1 # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.161927 # miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.161927 # miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 1 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.213965 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.214047 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.213965 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.214047 # miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 88063.994055 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 88063.994055 # average ReadExReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 77182.672234 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 77182.672234 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 87383.356880 # average ReadSharedReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 87383.356880 # average ReadSharedReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 77182.672234 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 87655.418921 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 87650.283372 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 77182.672234 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 87655.418921 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 87650.283372 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.writebacks::writebacks 1022139 # number of writebacks
system.cpu.l2cache.writebacks::total 1022139 # number of writebacks
system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 242 # number of CleanEvict MSHR misses
system.cpu.l2cache.CleanEvict_mshr_misses::total 242 # number of CleanEvict MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 780510 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 780510 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 958 # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::total 958 # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 1172148 # number of ReadSharedReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::total 1172148 # number of ReadSharedReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 958 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 1952658 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 1953616 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 958 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 1952658 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 1953616 # number of overall MSHR misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 60929728000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 60929728000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 64361000 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 64361000 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 90704747000 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 90704747000 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 64361000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 151634475000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 151698836000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 64361000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 151634475000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 151698836000 # number of overall MSHR miss cycles
system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.413550 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.413550 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 1 # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.161927 # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.161927 # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.213965 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.214047 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.213965 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.214047 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 78063.994055 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 78063.994055 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 67182.672234 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 67182.672234 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 77383.356880 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 77383.356880 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67182.672234 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 77655.418921 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 77650.283372 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67182.672234 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 77655.418921 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 77650.283372 # average overall mshr miss latency
system.cpu.toL2Bus.snoop_filter.tot_requests 18249005 # Total number of requests made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_requests 9121977 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.snoop_filter.tot_snoops 1268 # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1268 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.trans_dist::ReadResp 7239688 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackDirty 4708742 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackClean 3 # Transaction distribution
system.cpu.toL2Bus.trans_dist::CleanEvict 6334123 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 1887340 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 1887340 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadCleanReq 958 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadSharedReq 7238730 # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1919 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 27374114 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 27376033 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 61504 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 820011072 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total 820072576 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops 1920891 # Total snoops (count)