system.cpu.misc_regfile_writes 31840 # number of misc regfile writes
system.cpu.dcache.tags.replacements 486293 # number of replacements
system.cpu.dcache.tags.tagsinuse 510.756058 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 40330532 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 486805 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 82.847407 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 150823500 # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data 510.756058 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.997570 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.997570 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0 56 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1 456 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 84456645 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 84456645 # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data 21406566 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 21406566 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 18832689 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 18832689 # number of WriteReq hits
system.cpu.dcache.SoftPFReq_hits::cpu.data 59994 # number of SoftPFReq hits
system.cpu.dcache.SoftPFReq_hits::total 59994 # number of SoftPFReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data 15306 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total 15306 # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data 15919 # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total 15919 # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data 40239255 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 40239255 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 40299249 # number of overall hits
system.cpu.dcache.overall_hits::total 40299249 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 567937 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 567937 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 1017212 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 1017212 # number of WriteReq misses
system.cpu.dcache.SoftPFReq_misses::cpu.data 68679 # number of SoftPFReq misses
system.cpu.dcache.SoftPFReq_misses::total 68679 # number of SoftPFReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.data 618 # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total 618 # number of LoadLockedReq misses
system.cpu.dcache.demand_misses::cpu.data 1585149 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 1585149 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 1653828 # number of overall misses
system.cpu.dcache.overall_misses::total 1653828 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 9485185000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 9485185000 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 14264451930 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 14264451930 # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 5633500 # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total 5633500 # number of LoadLockedReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 23749636930 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 23749636930 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 23749636930 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 23749636930 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 21974503 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 21974503 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 19849901 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 19849901 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::cpu.data 128673 # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::total 128673 # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 15924 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total 15924 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data 15919 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total 15919 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 41824404 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 41824404 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 41953077 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 41953077 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.025845 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.025845 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.051245 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.051245 # miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.533748 # miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::total 0.533748 # miss rate for SoftPFReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.038809 # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.038809 # miss rate for LoadLockedReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.037900 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.037900 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.039421 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.039421 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16701.121779 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 16701.121779 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 14023.086564 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 14023.086564 # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 9115.695793 # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 9115.695793 # average LoadLockedReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 14982.589605 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 14982.589605 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 14360.403216 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 14360.403216 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 48 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 2907482 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 6 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 131418 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs 8 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets 22.123925 # average number of cycles each access was blocked
system.cpu.dcache.writebacks::writebacks 486293 # number of writebacks
system.cpu.dcache.writebacks::total 486293 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 267392 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 267392 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 868636 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 868636 # number of WriteReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 618 # number of LoadLockedReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::total 618 # number of LoadLockedReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data 1136028 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 1136028 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 1136028 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 1136028 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 300545 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 300545 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 148576 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 148576 # number of WriteReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 37700 # number of SoftPFReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::total 37700 # number of SoftPFReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 449121 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 449121 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 486821 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 486821 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3693304500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 3693304500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2308719470 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 2308719470 # number of WriteReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1888982500 # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1888982500 # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6002023970 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 6002023970 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7891006470 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 7891006470 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.013677 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.013677 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.007485 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.007485 # mshr miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.292991 # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.292991 # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.010738 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.010738 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.011604 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.011604 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12288.690546 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12288.690546 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 15538.979849 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 15538.979849 # average WriteReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 50105.636605 # average SoftPFReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 50105.636605 # average SoftPFReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13363.935265 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 13363.935265 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16209.256523 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 16209.256523 # average overall mshr miss latency
system.cpu.icache.tags.replacements 325000 # number of replacements
system.cpu.icache.tags.tagsinuse 510.229072 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 22083387 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 325512 # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs 67.842006 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 1115028500 # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst 510.229072 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.996541 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.996541 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0 85 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1 63 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::2 37 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::3 320 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::4 7 # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses 45161716 # Number of tag accesses
system.cpu.icache.tags.data_accesses 45161716 # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst 22083387 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 22083387 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 22083387 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 22083387 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 22083387 # number of overall hits
system.cpu.icache.overall_hits::total 22083387 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 334707 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 334707 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 334707 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 334707 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 334707 # number of overall misses
system.cpu.icache.overall_misses::total 334707 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 3526570179 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 3526570179 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 3526570179 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 3526570179 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 3526570179 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 3526570179 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 22418094 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 22418094 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 22418094 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 22418094 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 22418094 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 22418094 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.014930 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.014930 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.014930 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.014930 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.014930 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.014930 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 10536.290484 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 10536.290484 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 10536.290484 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 10536.290484 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 10536.290484 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 10536.290484 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 264177 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 49 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 16495 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 2 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs 16.015580 # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets 24.500000 # average number of cycles each access was blocked
system.cpu.icache.writebacks::writebacks 325000 # number of writebacks
system.cpu.icache.writebacks::total 325000 # number of writebacks
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 9178 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total 9178 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst 9178 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total 9178 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst 9178 # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total 9178 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 325529 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 325529 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 325529 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 325529 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 325529 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 325529 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 3259633220 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 3259633220 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 3259633220 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 3259633220 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 3259633220 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 3259633220 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.014521 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.014521 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.014521 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.014521 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.014521 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.014521 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 10013.342037 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 10013.342037 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 10013.342037 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 10013.342037 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 10013.342037 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 10013.342037 # average overall mshr miss latency
system.cpu.l2cache.prefetcher.num_hwpf_issued 822902 # number of hwpf issued
system.cpu.l2cache.prefetcher.pfIdentified 826054 # number of prefetch candidates identified
system.cpu.l2cache.prefetcher.pfBufferHit 2760 # number of redundant prefetches already in prefetch queue
system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
system.cpu.l2cache.prefetcher.pfSpanPage 78906 # number of prefetches not generated due to page crossing
system.cpu.l2cache.tags.replacements 128177 # number of replacements
system.cpu.l2cache.tags.tagsinuse 15989.063291 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 1184574 # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs 144531 # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs 8.195986 # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks 15883.544788 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 105.518503 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks 0.969455 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.006440 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total 0.975895 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1022 30 # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_blocks::1024 16324 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1022::1 7 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1022::2 3 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1022::3 14 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1022::4 6 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 124 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 2742 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 12115 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 553 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 790 # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1022 0.001831 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.996338 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 25089114 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 25089114 # Number of data accesses
system.cpu.l2cache.WritebackDirty_hits::writebacks 260314 # number of WritebackDirty hits
system.cpu.l2cache.WritebackDirty_hits::total 260314 # number of WritebackDirty hits
system.cpu.l2cache.WritebackClean_hits::writebacks 470737 # number of WritebackClean hits
system.cpu.l2cache.WritebackClean_hits::total 470737 # number of WritebackClean hits
system.cpu.l2cache.ReadExReq_hits::cpu.data 137093 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total 137093 # number of ReadExReq hits
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 314576 # number of ReadCleanReq hits
system.cpu.l2cache.ReadCleanReq_hits::total 314576 # number of ReadCleanReq hits
system.cpu.l2cache.ReadSharedReq_hits::cpu.data 300687 # number of ReadSharedReq hits
system.cpu.l2cache.ReadSharedReq_hits::total 300687 # number of ReadSharedReq hits
system.cpu.l2cache.demand_hits::cpu.inst 314576 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data 437780 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 752356 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst 314576 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data 437780 # number of overall hits
system.cpu.l2cache.overall_hits::total 752356 # number of overall hits
system.cpu.l2cache.UpgradeReq_misses::cpu.data 16 # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_misses::total 16 # number of UpgradeReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data 11519 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 11519 # number of ReadExReq misses
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 10935 # number of ReadCleanReq misses
system.cpu.l2cache.ReadCleanReq_misses::total 10935 # number of ReadCleanReq misses
system.cpu.l2cache.ReadSharedReq_misses::cpu.data 37506 # number of ReadSharedReq misses
system.cpu.l2cache.ReadSharedReq_misses::total 37506 # number of ReadSharedReq misses
system.cpu.l2cache.demand_misses::cpu.inst 10935 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 49025 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 59960 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst 10935 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 49025 # number of overall misses
system.cpu.l2cache.overall_misses::total 59960 # number of overall misses
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1190791000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 1190791000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 838826500 # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::total 838826500 # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 3069049000 # number of ReadSharedReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::total 3069049000 # number of ReadSharedReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 838826500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 4259840000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 5098666500 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 838826500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 4259840000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 5098666500 # number of overall miss cycles
system.cpu.l2cache.WritebackDirty_accesses::writebacks 260314 # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackDirty_accesses::total 260314 # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::writebacks 470737 # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::total 470737 # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::cpu.data 16 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::total 16 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data 148612 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 148612 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 325511 # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::total 325511 # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 338193 # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::total 338193 # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst 325511 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 486805 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 812316 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 325511 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 486805 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 812316 # number of overall (read+write) accesses
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 1 # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.077511 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 0.077511 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.033593 # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.033593 # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.110901 # miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.110901 # miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.033593 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.100708 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.073814 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.033593 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.100708 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.073814 # miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 103376.247938 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 103376.247938 # average ReadExReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 76710.242341 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 76710.242341 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 81828.214152 # average ReadSharedReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 81828.214152 # average ReadSharedReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76710.242341 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 86891.177970 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 85034.464643 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76710.242341 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 86891.177970 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 85034.464643 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.unused_prefetches 424 # number of HardPF blocks evicted w/o reference
system.cpu.l2cache.writebacks::writebacks 97140 # number of writebacks
system.cpu.l2cache.writebacks::total 97140 # number of writebacks
system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 3182 # number of ReadExReq MSHR hits
system.cpu.l2cache.ReadExReq_mshr_hits::total 3182 # number of ReadExReq MSHR hits
system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 28 # number of ReadCleanReq MSHR hits
system.cpu.l2cache.ReadCleanReq_mshr_hits::total 28 # number of ReadCleanReq MSHR hits
system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 100 # number of ReadSharedReq MSHR hits
system.cpu.l2cache.ReadSharedReq_mshr_hits::total 100 # number of ReadSharedReq MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.inst 28 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.data 3282 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::total 3310 # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.inst 28 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.data 3282 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::total 3310 # number of overall MSHR hits
system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 112662 # number of HardPFReq MSHR misses
system.cpu.l2cache.HardPFReq_mshr_misses::total 112662 # number of HardPFReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 16 # number of UpgradeReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::total 16 # number of UpgradeReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 8337 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 8337 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 10907 # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::total 10907 # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 37406 # number of ReadSharedReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::total 37406 # number of ReadSharedReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 10907 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 45743 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 56650 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 10907 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 45743 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 112662 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 169312 # number of overall MSHR misses
system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 10325101509 # number of HardPFReq MSHR miss cycles
system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 10325101509 # number of HardPFReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 232500 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 232500 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 662233000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 662233000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 771578500 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 771578500 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 2838075000 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 2838075000 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 771578500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 3500308000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 4271886500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 771578500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 3500308000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 10325101509 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 14596988009 # number of overall MSHR miss cycles
system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses
system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.056099 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.056099 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.033507 # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.033507 # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.110605 # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.110605 # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.033507 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.093966 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.069739 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.033507 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.093966 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.208431 # mshr miss rate for overall accesses
system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 91646.708819 # average HardPFReq mshr miss latency
system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 91646.708819 # average HardPFReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 14531.250000 # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 14531.250000 # average UpgradeReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 79433.009476 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 79433.009476 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 70741.587971 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 70741.587971 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 75872.186280 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 75872.186280 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 70741.587971 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 76521.172638 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 75408.411297 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 70741.587971 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 76521.172638 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 91646.708819 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 86213.546642 # average overall mshr miss latency
system.cpu.toL2Bus.snoop_filter.tot_requests 1623643 # Total number of requests made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_requests 811337 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 80260 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.snoop_filter.tot_snoops 67456 # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 56671 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 10785 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.trans_dist::ReadResp 663721 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackDirty 357454 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackClean 550979 # Transaction distribution
system.cpu.toL2Bus.trans_dist::CleanEvict 79349 # Transaction distribution
system.cpu.toL2Bus.trans_dist::HardPFReq 142185 # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeReq 16 # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeResp 16 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 148612 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 148612 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadCleanReq 325529 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadSharedReq 338193 # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 976039 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1459935 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 2435974 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 41632640 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 62278272 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total 103910912 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops 318692 # Total snoops (count)