system.cpu.workload.num_syscalls 1946 # Number of system calls
system.cpu.numCycles 113605949 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 70915150 # Number of instructions committed
system.cpu.committedOps 90690106 # Number of ops (including micro ops) committed
system.cpu.discardedOps 1137741 # Number of ops (including micro ops) which were discarded before commit
system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching
system.cpu.cpi 1.601998 # CPI: cycles per instruction
system.cpu.ipc 0.624220 # IPC: instructions per cycle
system.cpu.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
system.cpu.op_class_0::IntAlu 47187979 52.03% 52.03% # Class of committed instruction
system.cpu.op_class_0::IntMult 80119 0.09% 52.12% # Class of committed instruction
system.cpu.op_class_0::IntDiv 0 0.00% 52.12% # Class of committed instruction
system.cpu.op_class_0::FloatAdd 0 0.00% 52.12% # Class of committed instruction
system.cpu.op_class_0::FloatCmp 0 0.00% 52.12% # Class of committed instruction
system.cpu.op_class_0::FloatCvt 0 0.00% 52.12% # Class of committed instruction
system.cpu.op_class_0::FloatMult 0 0.00% 52.12% # Class of committed instruction
system.cpu.op_class_0::FloatDiv 0 0.00% 52.12% # Class of committed instruction
system.cpu.op_class_0::FloatSqrt 0 0.00% 52.12% # Class of committed instruction
system.cpu.op_class_0::SimdAdd 0 0.00% 52.12% # Class of committed instruction
system.cpu.op_class_0::SimdAddAcc 0 0.00% 52.12% # Class of committed instruction
system.cpu.op_class_0::SimdAlu 0 0.00% 52.12% # Class of committed instruction
system.cpu.op_class_0::SimdCmp 0 0.00% 52.12% # Class of committed instruction
system.cpu.op_class_0::SimdCvt 0 0.00% 52.12% # Class of committed instruction
system.cpu.op_class_0::SimdMisc 0 0.00% 52.12% # Class of committed instruction
system.cpu.op_class_0::SimdMult 0 0.00% 52.12% # Class of committed instruction
system.cpu.op_class_0::SimdMultAcc 0 0.00% 52.12% # Class of committed instruction
system.cpu.op_class_0::SimdShift 0 0.00% 52.12% # Class of committed instruction
system.cpu.op_class_0::SimdShiftAcc 0 0.00% 52.12% # Class of committed instruction
system.cpu.op_class_0::SimdSqrt 0 0.00% 52.12% # Class of committed instruction
system.cpu.op_class_0::SimdFloatAdd 0 0.00% 52.12% # Class of committed instruction
system.cpu.op_class_0::SimdFloatAlu 0 0.00% 52.12% # Class of committed instruction
system.cpu.op_class_0::SimdFloatCmp 0 0.00% 52.12% # Class of committed instruction
system.cpu.op_class_0::SimdFloatCvt 0 0.00% 52.12% # Class of committed instruction
system.cpu.op_class_0::SimdFloatDiv 0 0.00% 52.12% # Class of committed instruction
system.cpu.op_class_0::SimdFloatMisc 7 0.00% 52.12% # Class of committed instruction
system.cpu.op_class_0::SimdFloatMult 0 0.00% 52.12% # Class of committed instruction
system.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 52.12% # Class of committed instruction
system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 52.12% # Class of committed instruction
system.cpu.op_class_0::MemRead 22866262 25.21% 77.33% # Class of committed instruction
system.cpu.op_class_0::MemWrite 20555739 22.67% 100.00% # Class of committed instruction
system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
system.cpu.op_class_0::total 90690106 # Class of committed instruction
system.cpu.tickCycles 95311103 # Number of cycles that the object actually ticked
system.cpu.idleCycles 18294846 # Total number of cycles that the object has spent stopped
system.cpu.dcache.tags.replacements 156448 # number of replacements
system.cpu.dcache.tags.tagsinuse 4067.225830 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 42620314 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 160544 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 265.474350 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 820768500 # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data 4067.225830 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.992975 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.992975 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0 44 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1 1099 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2 2953 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 86009120 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 86009120 # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data 22862903 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 22862903 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 19642172 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 19642172 # number of WriteReq hits
system.cpu.dcache.SoftPFReq_hits::cpu.data 83401 # number of SoftPFReq hits
system.cpu.dcache.SoftPFReq_hits::total 83401 # number of SoftPFReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data 15919 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total 15919 # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data 15919 # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total 15919 # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data 42505075 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 42505075 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 42588476 # number of overall hits
system.cpu.dcache.overall_hits::total 42588476 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 51661 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 51661 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 207729 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 207729 # number of WriteReq misses
system.cpu.dcache.SoftPFReq_misses::cpu.data 44584 # number of SoftPFReq misses
system.cpu.dcache.SoftPFReq_misses::total 44584 # number of SoftPFReq misses
system.cpu.dcache.demand_misses::cpu.data 259390 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 259390 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 303974 # number of overall misses
system.cpu.dcache.overall_misses::total 303974 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 1490194000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 1490194000 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 16811157000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 16811157000 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 18301351000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 18301351000 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 18301351000 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 18301351000 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 22914564 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 22914564 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 19849901 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 19849901 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::cpu.data 127985 # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::total 127985 # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 15919 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total 15919 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data 15919 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total 15919 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 42764465 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 42764465 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 42892450 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 42892450 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002255 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.002255 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.010465 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.010465 # miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.348353 # miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::total 0.348353 # miss rate for SoftPFReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.006066 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.006066 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.007087 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.007087 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 28845.628230 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 28845.628230 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 80928.310443 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 80928.310443 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 70555.345233 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 70555.345233 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 60206.961780 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 60206.961780 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.writebacks::writebacks 128389 # number of writebacks
system.cpu.dcache.writebacks::total 128389 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 22138 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 22138 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 100695 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 100695 # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data 122833 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 122833 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 122833 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 122833 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 29523 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 29523 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 107034 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 107034 # number of WriteReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 23987 # number of SoftPFReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::total 23987 # number of SoftPFReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 136557 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 136557 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 160544 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 160544 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 578329500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 578329500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8490118500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 8490118500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1713467500 # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1713467500 # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9068448000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 9068448000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10781915500 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 10781915500 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001288 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001288 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005392 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005392 # mshr miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.187420 # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.187420 # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003193 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.003193 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003743 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.003743 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19589.116960 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19589.116960 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 79321.696844 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 79321.696844 # average WriteReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 71433.172135 # average SoftPFReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 71433.172135 # average SoftPFReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 66407.785760 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 66407.785760 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 67158.632524 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 67158.632524 # average overall mshr miss latency
system.cpu.icache.tags.replacements 43497 # number of replacements
system.cpu.icache.tags.tagsinuse 1852.676989 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 24844377 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 45539 # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs 545.562639 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst 1852.676989 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.904627 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.904627 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024 2042 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0 76 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1 46 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::3 915 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::4 1005 # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024 0.997070 # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses 49825373 # Number of tag accesses
system.cpu.icache.tags.data_accesses 49825373 # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst 24844377 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 24844377 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 24844377 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 24844377 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 24844377 # number of overall hits
system.cpu.icache.overall_hits::total 24844377 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 45540 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 45540 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 45540 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 45540 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 45540 # number of overall misses
system.cpu.icache.overall_misses::total 45540 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 905103000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 905103000 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 905103000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 905103000 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 905103000 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 905103000 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 24889917 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 24889917 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 24889917 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 24889917 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 24889917 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 24889917 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001830 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.001830 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.001830 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.001830 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.001830 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.001830 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 19874.901186 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 19874.901186 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 19874.901186 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 19874.901186 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 19874.901186 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 19874.901186 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.writebacks::writebacks 43497 # number of writebacks
system.cpu.icache.writebacks::total 43497 # number of writebacks
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 45540 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 45540 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 45540 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 45540 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 45540 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 45540 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 859564000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 859564000 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 859564000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 859564000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 859564000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 859564000 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.001830 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.001830 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.001830 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.001830 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.001830 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.001830 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18874.923144 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18874.923144 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18874.923144 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 18874.923144 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18874.923144 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 18874.923144 # average overall mshr miss latency
system.cpu.l2cache.tags.replacements 96391 # number of replacements
system.cpu.l2cache.tags.tagsinuse 29870.997301 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 163417 # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs 127542 # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs 1.281280 # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks 26781.820547 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst 1433.103835 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 1656.072920 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks 0.817316 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.043735 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data 0.050539 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total 0.911590 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1024 31151 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 191 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 1859 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 12725 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 15781 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 595 # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.950653 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 3420152 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 3420152 # Number of data accesses
system.cpu.l2cache.WritebackDirty_hits::writebacks 128389 # number of WritebackDirty hits
system.cpu.l2cache.WritebackDirty_hits::total 128389 # number of WritebackDirty hits
system.cpu.l2cache.WritebackClean_hits::writebacks 39908 # number of WritebackClean hits
system.cpu.l2cache.WritebackClean_hits::total 39908 # number of WritebackClean hits
system.cpu.l2cache.ReadExReq_hits::cpu.data 4752 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total 4752 # number of ReadExReq hits
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 41065 # number of ReadCleanReq hits
system.cpu.l2cache.ReadCleanReq_hits::total 41065 # number of ReadCleanReq hits
system.cpu.l2cache.ReadSharedReq_hits::cpu.data 31907 # number of ReadSharedReq hits
system.cpu.l2cache.ReadSharedReq_hits::total 31907 # number of ReadSharedReq hits
system.cpu.l2cache.demand_hits::cpu.inst 41065 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data 36659 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 77724 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst 41065 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data 36659 # number of overall hits
system.cpu.l2cache.overall_hits::total 77724 # number of overall hits
system.cpu.l2cache.ReadExReq_misses::cpu.data 102282 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 102282 # number of ReadExReq misses
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 4475 # number of ReadCleanReq misses
system.cpu.l2cache.ReadCleanReq_misses::total 4475 # number of ReadCleanReq misses
system.cpu.l2cache.ReadSharedReq_misses::cpu.data 21603 # number of ReadSharedReq misses
system.cpu.l2cache.ReadSharedReq_misses::total 21603 # number of ReadSharedReq misses
system.cpu.l2cache.demand_misses::cpu.inst 4475 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 123885 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 128360 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst 4475 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 123885 # number of overall misses
system.cpu.l2cache.overall_misses::total 128360 # number of overall misses
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 8279623500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 8279623500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 356201500 # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::total 356201500 # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 1872087500 # number of ReadSharedReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::total 1872087500 # number of ReadSharedReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 356201500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 10151711000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 10507912500 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 356201500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 10151711000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 10507912500 # number of overall miss cycles
system.cpu.l2cache.WritebackDirty_accesses::writebacks 128389 # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackDirty_accesses::total 128389 # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::writebacks 39908 # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::total 39908 # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data 107034 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 107034 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 45540 # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::total 45540 # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 53510 # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::total 53510 # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst 45540 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 160544 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 206084 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 45540 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 160544 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 206084 # number of overall (read+write) accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.955603 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 0.955603 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.098265 # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.098265 # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.403719 # miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.403719 # miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.098265 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.771658 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.622853 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.098265 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.771658 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.622853 # miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 80948.979293 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 80948.979293 # average ReadExReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 79598.100559 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 79598.100559 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 86658.681665 # average ReadSharedReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 86658.681665 # average ReadSharedReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 79598.100559 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 81944.634136 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 81862.827205 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 79598.100559 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 81944.634136 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 81862.827205 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.writebacks::writebacks 86215 # number of writebacks
system.cpu.l2cache.writebacks::total 86215 # number of writebacks
system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 13 # number of ReadCleanReq MSHR hits
system.cpu.l2cache.ReadCleanReq_mshr_hits::total 13 # number of ReadCleanReq MSHR hits
system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 62 # number of ReadSharedReq MSHR hits
system.cpu.l2cache.ReadSharedReq_mshr_hits::total 62 # number of ReadSharedReq MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.inst 13 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.data 62 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::total 75 # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.inst 13 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.data 62 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::total 75 # number of overall MSHR hits
system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 96 # number of CleanEvict MSHR misses
system.cpu.l2cache.CleanEvict_mshr_misses::total 96 # number of CleanEvict MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 102282 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 102282 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 4462 # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::total 4462 # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 21541 # number of ReadSharedReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::total 21541 # number of ReadSharedReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 4462 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 123823 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 128285 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 4462 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 123823 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 128285 # number of overall MSHR misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7256803500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7256803500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 310457000 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 310457000 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 1652012000 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 1652012000 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 310457000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8908815500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 9219272500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 310457000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8908815500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 9219272500 # number of overall MSHR miss cycles
system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.955603 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.955603 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.097980 # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.097980 # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.402560 # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.402560 # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.097980 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.771271 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.622489 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.097980 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.771271 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.622489 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 70948.979293 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 70948.979293 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 69577.991932 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 69577.991932 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 76691.518500 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 76691.518500 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69577.991932 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71947.986238 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 71865.553260 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69577.991932 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71947.986238 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 71865.553260 # average overall mshr miss latency
system.cpu.toL2Bus.snoop_filter.tot_requests 406029 # Total number of requests made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_requests 199980 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 7832 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.snoop_filter.tot_snoops 3359 # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 3330 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 29 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.trans_dist::ReadResp 99049 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackDirty 214604 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackClean 43497 # Transaction distribution
system.cpu.toL2Bus.trans_dist::CleanEvict 38235 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 107034 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 107034 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadCleanReq 45540 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadSharedReq 53510 # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 134576 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 477536 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 612112 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5698304 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 18491712 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total 24190016 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops 96391 # Total snoops (count)