system.cpu.workload.num_syscalls 191 # Number of system calls
system.cpu.numCycles 423429906 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 273037857 # Number of instructions committed
system.cpu.committedOps 327812214 # Number of ops (including micro ops) committed
system.cpu.discardedOps 2127081 # Number of ops (including micro ops) which were discarded before commit
system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching
system.cpu.cpi 1.550810 # CPI: cycles per instruction
system.cpu.ipc 0.644824 # IPC: instructions per cycle
system.cpu.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
system.cpu.op_class_0::IntAlu 104312544 31.82% 31.82% # Class of committed instruction
system.cpu.op_class_0::IntMult 2145905 0.65% 32.48% # Class of committed instruction
system.cpu.op_class_0::IntDiv 0 0.00% 32.48% # Class of committed instruction
system.cpu.op_class_0::FloatAdd 0 0.00% 32.48% # Class of committed instruction
system.cpu.op_class_0::FloatCmp 0 0.00% 32.48% # Class of committed instruction
system.cpu.op_class_0::FloatCvt 0 0.00% 32.48% # Class of committed instruction
system.cpu.op_class_0::FloatMult 0 0.00% 32.48% # Class of committed instruction
system.cpu.op_class_0::FloatDiv 0 0.00% 32.48% # Class of committed instruction
system.cpu.op_class_0::FloatSqrt 0 0.00% 32.48% # Class of committed instruction
system.cpu.op_class_0::SimdAdd 0 0.00% 32.48% # Class of committed instruction
system.cpu.op_class_0::SimdAddAcc 0 0.00% 32.48% # Class of committed instruction
system.cpu.op_class_0::SimdAlu 0 0.00% 32.48% # Class of committed instruction
system.cpu.op_class_0::SimdCmp 0 0.00% 32.48% # Class of committed instruction
system.cpu.op_class_0::SimdCvt 0 0.00% 32.48% # Class of committed instruction
system.cpu.op_class_0::SimdMisc 0 0.00% 32.48% # Class of committed instruction
system.cpu.op_class_0::SimdMult 0 0.00% 32.48% # Class of committed instruction
system.cpu.op_class_0::SimdMultAcc 0 0.00% 32.48% # Class of committed instruction
system.cpu.op_class_0::SimdShift 0 0.00% 32.48% # Class of committed instruction
system.cpu.op_class_0::SimdShiftAcc 0 0.00% 32.48% # Class of committed instruction
system.cpu.op_class_0::SimdSqrt 0 0.00% 32.48% # Class of committed instruction
system.cpu.op_class_0::SimdFloatAdd 6594343 2.01% 34.49% # Class of committed instruction
system.cpu.op_class_0::SimdFloatAlu 0 0.00% 34.49% # Class of committed instruction
system.cpu.op_class_0::SimdFloatCmp 7943502 2.42% 36.91% # Class of committed instruction
system.cpu.op_class_0::SimdFloatCvt 3118180 0.95% 37.86% # Class of committed instruction
system.cpu.op_class_0::SimdFloatDiv 1563217 0.48% 38.34% # Class of committed instruction
system.cpu.op_class_0::SimdFloatMisc 19652356 6.00% 44.33% # Class of committed instruction
system.cpu.op_class_0::SimdFloatMult 7136937 2.18% 46.51% # Class of committed instruction
system.cpu.op_class_0::SimdFloatMultAcc 7062098 2.15% 48.66% # Class of committed instruction
system.cpu.op_class_0::SimdFloatSqrt 175285 0.05% 48.72% # Class of committed instruction
system.cpu.op_class_0::MemRead 85732248 26.15% 74.87% # Class of committed instruction
system.cpu.op_class_0::MemWrite 82375599 25.13% 100.00% # Class of committed instruction
system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
system.cpu.op_class_0::total 327812214 # Class of committed instruction
system.cpu.tickCycles 420106568 # Number of cycles that the object actually ticked
system.cpu.idleCycles 3323338 # Total number of cycles that the object has spent stopped
system.cpu.dcache.tags.replacements 1355 # number of replacements
system.cpu.dcache.tags.tagsinuse 3085.570959 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 168654881 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 4512 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 37379.184619 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data 3085.570959 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.753313 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.753313 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 3157 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0 21 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1 21 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2 12 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::3 672 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::4 2431 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 0.770752 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 337328856 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 337328856 # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data 86522107 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 86522107 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 82047451 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 82047451 # number of WriteReq hits
system.cpu.dcache.SoftPFReq_hits::cpu.data 63533 # number of SoftPFReq hits
system.cpu.dcache.SoftPFReq_hits::total 63533 # number of SoftPFReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data 10895 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total 10895 # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data 10895 # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total 10895 # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data 168569558 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 168569558 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 168633091 # number of overall hits
system.cpu.dcache.overall_hits::total 168633091 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 2060 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 2060 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 5226 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 5226 # number of WriteReq misses
system.cpu.dcache.SoftPFReq_misses::cpu.data 5 # number of SoftPFReq misses
system.cpu.dcache.SoftPFReq_misses::total 5 # number of SoftPFReq misses
system.cpu.dcache.demand_misses::cpu.data 7286 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 7286 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 7291 # number of overall misses
system.cpu.dcache.overall_misses::total 7291 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 136635000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 136635000 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 394688000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 394688000 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 531323000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 531323000 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 531323000 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 531323000 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 86524167 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 86524167 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 82052677 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 82052677 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::cpu.data 63538 # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::total 63538 # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 10895 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total 10895 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data 10895 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total 10895 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 168576844 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 168576844 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 168640382 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 168640382 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000024 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.000024 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000064 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.000064 # miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.000079 # miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::total 0.000079 # miss rate for SoftPFReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.000043 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.000043 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.000043 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.000043 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 66327.669903 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 66327.669903 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 75523.918867 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 75523.918867 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 72923.826517 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 72923.826517 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 72873.817035 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 72873.817035 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.writebacks::writebacks 1010 # number of writebacks
system.cpu.dcache.writebacks::total 1010 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 421 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 421 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2356 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 2356 # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data 2777 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 2777 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 2777 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 2777 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1639 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 1639 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2870 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 2870 # number of WriteReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 3 # number of SoftPFReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::total 3 # number of SoftPFReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 4509 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 4509 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 4512 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 4512 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 109916500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 109916500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 219842000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 219842000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 481000 # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 481000 # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 329758500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 329758500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 330239500 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 330239500 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000019 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000019 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000035 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000035 # mshr miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.000047 # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.000047 # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.000027 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.000027 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 67063.148261 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 67063.148261 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 76600 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 76600 # average WriteReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 160333.333333 # average SoftPFReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 160333.333333 # average SoftPFReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 73133.399867 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 73133.399867 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 73191.378546 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 73191.378546 # average overall mshr miss latency
system.cpu.icache.tags.replacements 38168 # number of replacements
system.cpu.icache.tags.tagsinuse 1923.744161 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 69641436 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 40104 # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs 1736.520946 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst 1923.744161 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.939328 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.939328 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024 1936 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0 60 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1 84 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::2 33 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::3 276 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::4 1483 # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024 0.945312 # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses 139403186 # Number of tag accesses
system.cpu.icache.tags.data_accesses 139403186 # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst 69641436 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 69641436 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 69641436 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 69641436 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 69641436 # number of overall hits
system.cpu.icache.overall_hits::total 69641436 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 40105 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 40105 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 40105 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 40105 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 40105 # number of overall misses
system.cpu.icache.overall_misses::total 40105 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 757528000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 757528000 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 757528000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 757528000 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 757528000 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 757528000 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 69681541 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 69681541 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 69681541 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 69681541 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 69681541 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 69681541 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000576 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.000576 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.000576 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.000576 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.000576 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.000576 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 18888.617379 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 18888.617379 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 18888.617379 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 18888.617379 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 18888.617379 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 18888.617379 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.writebacks::writebacks 38168 # number of writebacks
system.cpu.icache.writebacks::total 38168 # number of writebacks
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 40105 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 40105 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 40105 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 40105 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 40105 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 40105 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 717424000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 717424000 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 717424000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 717424000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 717424000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 717424000 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000576 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000576 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000576 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.000576 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000576 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.000576 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 17888.642314 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 17888.642314 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 17888.642314 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 17888.642314 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 17888.642314 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 17888.642314 # average overall mshr miss latency
system.cpu.l2cache.tags.replacements 0 # number of replacements
system.cpu.l2cache.tags.tagsinuse 4199.701287 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 60529 # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs 5648 # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs 10.716891 # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks 353.800339 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst 3167.579629 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 678.321319 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks 0.010797 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.096667 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data 0.020701 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total 0.128165 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1024 5648 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 56 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 37 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 42 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1251 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 4262 # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.172363 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 561366 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 561366 # Number of data accesses
system.cpu.l2cache.WritebackDirty_hits::writebacks 1010 # number of WritebackDirty hits
system.cpu.l2cache.WritebackDirty_hits::total 1010 # number of WritebackDirty hits
system.cpu.l2cache.WritebackClean_hits::writebacks 23251 # number of WritebackClean hits
system.cpu.l2cache.WritebackClean_hits::total 23251 # number of WritebackClean hits
system.cpu.l2cache.ReadExReq_hits::cpu.data 16 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total 16 # number of ReadExReq hits
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 36680 # number of ReadCleanReq hits
system.cpu.l2cache.ReadCleanReq_hits::total 36680 # number of ReadCleanReq hits
system.cpu.l2cache.ReadSharedReq_hits::cpu.data 291 # number of ReadSharedReq hits
system.cpu.l2cache.ReadSharedReq_hits::total 291 # number of ReadSharedReq hits
system.cpu.l2cache.demand_hits::cpu.inst 36680 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data 307 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 36987 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst 36680 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data 307 # number of overall hits
system.cpu.l2cache.overall_hits::total 36987 # number of overall hits
system.cpu.l2cache.ReadExReq_misses::cpu.data 2854 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 2854 # number of ReadExReq misses
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 3425 # number of ReadCleanReq misses
system.cpu.l2cache.ReadCleanReq_misses::total 3425 # number of ReadCleanReq misses
system.cpu.l2cache.ReadSharedReq_misses::cpu.data 1351 # number of ReadSharedReq misses
system.cpu.l2cache.ReadSharedReq_misses::total 1351 # number of ReadSharedReq misses
system.cpu.l2cache.demand_misses::cpu.inst 3425 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 4205 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 7630 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst 3425 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 4205 # number of overall misses
system.cpu.l2cache.overall_misses::total 7630 # number of overall misses
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 215334500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 215334500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 257203500 # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::total 257203500 # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 104684500 # number of ReadSharedReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::total 104684500 # number of ReadSharedReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 257203500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 320019000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 577222500 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 257203500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 320019000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 577222500 # number of overall miss cycles
system.cpu.l2cache.WritebackDirty_accesses::writebacks 1010 # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackDirty_accesses::total 1010 # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::writebacks 23251 # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::total 23251 # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data 2870 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 2870 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 40105 # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::total 40105 # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1642 # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::total 1642 # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst 40105 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 4512 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 44617 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 40105 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 4512 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 44617 # number of overall (read+write) accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.994425 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 0.994425 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.085401 # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.085401 # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.822777 # miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.822777 # miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.085401 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.931959 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.171011 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.085401 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.931959 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.171011 # miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 75450.070077 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 75450.070077 # average ReadExReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75095.912409 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75095.912409 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 77486.676536 # average ReadSharedReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 77486.676536 # average ReadSharedReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75095.912409 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76104.399524 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 75651.703801 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75095.912409 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76104.399524 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 75651.703801 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 2 # number of ReadCleanReq MSHR hits
system.cpu.l2cache.ReadCleanReq_mshr_hits::total 2 # number of ReadCleanReq MSHR hits
system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 42 # number of ReadSharedReq MSHR hits
system.cpu.l2cache.ReadSharedReq_mshr_hits::total 42 # number of ReadSharedReq MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.inst 2 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.data 42 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::total 44 # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.inst 2 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.data 42 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::total 44 # number of overall MSHR hits
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 2854 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 2854 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 3423 # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::total 3423 # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 1309 # number of ReadSharedReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::total 1309 # number of ReadSharedReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 3423 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 4163 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 7586 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 3423 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 4163 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 7586 # number of overall MSHR misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 186794500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 186794500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 222839000 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 222839000 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 88850500 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 88850500 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 222839000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 275645000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 498484000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 222839000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 275645000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 498484000 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.994425 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.994425 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.085351 # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.085351 # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.797199 # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.797199 # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.085351 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.922651 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.170025 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.085351 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.922651 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.170025 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 65450.070077 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 65450.070077 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65100.496640 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65100.496640 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 67876.623377 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 67876.623377 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65100.496640 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 66213.067499 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65711.046665 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65100.496640 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 66213.067499 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65711.046665 # average overall mshr miss latency
system.cpu.toL2Bus.snoop_filter.tot_requests 84140 # Total number of requests made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_requests 39625 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 15034 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.trans_dist::ReadResp 41746 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackDirty 1010 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackClean 38168 # Transaction distribution
system.cpu.toL2Bus.trans_dist::CleanEvict 345 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 2870 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 2870 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadCleanReq 40105 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadSharedReq 1642 # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 118377 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 10379 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 128756 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5009408 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 353408 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total 5362816 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops 0 # Total snoops (count)