2006-10-12 21:04:14 +02:00
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|
---------- Begin Simulation Statistics ----------
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|
global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
2006-12-05 01:07:00 +01:00
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|
|
global.BPredUnit.BTBHits 1060300638 # Number of BTB hits
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|
|
|
|
global.BPredUnit.BTBLookups 1075264664 # Number of BTB lookups
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|
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|
|
global.BPredUnit.RASInCorrect 132 # Number of incorrect RAS predictions.
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|
|
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|
global.BPredUnit.condIncorrect 20658855 # Number of conditional branches incorrect
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|
|
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|
global.BPredUnit.condPredicted 1028649695 # Number of conditional branches predicted
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|
|
|
|
global.BPredUnit.lookups 1098978166 # Number of BP lookups
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|
|
|
|
global.BPredUnit.usedRAS 20738311 # Number of times the RAS was used to get a target.
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|
|
|
|
host_inst_rate 27542 # Simulator instruction rate (inst/s)
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|
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|
host_mem_usage 1254844 # Number of bytes of host memory used
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|
host_seconds 63032.08 # Real time elapsed on the host
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host_tick_rate 395232 # Simulator tick rate (ticks/s)
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|
memdepunit.memDep.conflictingLoads 114920109 # Number of conflicting loads.
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|
memdepunit.memDep.conflictingStores 60881817 # Number of conflicting stores.
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|
memdepunit.memDep.insertedLoads 938731548 # Number of loads inserted to the mem dependence unit.
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|
memdepunit.memDep.insertedStores 389309694 # Number of stores inserted to the mem dependence unit.
|
2006-10-12 21:04:14 +02:00
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|
sim_freq 1000000000000 # Frequency of simulated ticks
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2006-12-05 01:07:00 +01:00
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|
|
sim_insts 1736043781 # Number of instructions simulated
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|
|
|
sim_seconds 0.024912 # Number of seconds simulated
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|
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|
|
sim_ticks 24912272090 # Number of ticks simulated
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|
|
|
system.cpu.commit.COM:branches 214632552 # Number of branches committed
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|
system.cpu.commit.COM:bw_lim_events 72343657 # number cycles where commit BW limit reached
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2006-10-12 21:04:14 +02:00
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system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
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system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle
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2006-12-05 01:07:00 +01:00
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system.cpu.commit.COM:committed_per_cycle.samples 5678957793
|
2006-10-12 21:04:14 +02:00
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system.cpu.commit.COM:committed_per_cycle.min_value 0
|
2006-12-05 01:07:00 +01:00
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0 5103057521 8985.90%
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|
1 193842571 341.33%
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2 126727829 223.15%
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3 63255233 111.39%
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4 47590442 83.80%
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5 34302037 60.40%
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6 22774532 40.10%
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7 15063971 26.53%
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8 72343657 127.39%
|
2006-10-12 21:04:14 +02:00
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system.cpu.commit.COM:committed_per_cycle.max_value 8
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system.cpu.commit.COM:committed_per_cycle.end_dist
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2006-12-05 01:07:00 +01:00
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system.cpu.commit.COM:count 1819780126 # Number of instructions committed
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system.cpu.commit.COM:loads 445666361 # Number of loads committed
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2006-10-12 21:04:14 +02:00
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|
system.cpu.commit.COM:membars 0 # Number of memory barriers committed
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2006-12-05 01:07:00 +01:00
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|
system.cpu.commit.COM:refs 606571343 # Number of memory references committed
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2006-10-12 21:04:14 +02:00
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|
system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
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2006-12-05 01:07:00 +01:00
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system.cpu.commit.branchMispredicts 20658355 # The number of times a branch was mispredicted
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system.cpu.commit.commitCommittedInsts 1819780126 # The number of committed instructions
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system.cpu.commit.commitNonSpecStalls 29 # The number of times commit has been forced to stall to communicate backwards
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system.cpu.commit.commitSquashedInsts 3012390712 # The number of squashed insts skipped by commit
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system.cpu.committedInsts 1736043781 # Number of Instructions Simulated
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system.cpu.committedInsts_total 1736043781 # Number of Instructions Simulated
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system.cpu.cpi 14.350025 # CPI: Cycles Per Instruction
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system.cpu.cpi_total 14.350025 # CPI: Total CPI of All Threads
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system.cpu.dcache.ReadReq_accesses 466176479 # number of ReadReq accesses(hits+misses)
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system.cpu.dcache.ReadReq_avg_miss_latency 5764.172372 # average ReadReq miss latency
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system.cpu.dcache.ReadReq_avg_mshr_miss_latency 5678.042412 # average ReadReq mshr miss latency
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system.cpu.dcache.ReadReq_hits 454097633 # number of ReadReq hits
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|
|
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|
system.cpu.dcache.ReadReq_miss_latency 69624550394 # number of ReadReq miss cycles
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|
system.cpu.dcache.ReadReq_miss_rate 0.025910 # miss rate for ReadReq accesses
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system.cpu.dcache.ReadReq_misses 12078846 # number of ReadReq misses
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system.cpu.dcache.ReadReq_mshr_hits 4784670 # number of ReadReq MSHR hits
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|
system.cpu.dcache.ReadReq_mshr_miss_latency 41416640690 # number of ReadReq MSHR miss cycles
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|
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system.cpu.dcache.ReadReq_mshr_miss_rate 0.015647 # mshr miss rate for ReadReq accesses
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|
system.cpu.dcache.ReadReq_mshr_misses 7294176 # number of ReadReq MSHR misses
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system.cpu.dcache.WriteReq_accesses 160728502 # number of WriteReq accesses(hits+misses)
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system.cpu.dcache.WriteReq_avg_miss_latency 11148.179412 # average WriteReq miss latency
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system.cpu.dcache.WriteReq_avg_mshr_miss_latency 14223.476157 # average WriteReq mshr miss latency
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system.cpu.dcache.WriteReq_hits 157574910 # number of WriteReq hits
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|
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|
system.cpu.dcache.WriteReq_miss_latency 35156809407 # number of WriteReq miss cycles
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system.cpu.dcache.WriteReq_miss_rate 0.019621 # miss rate for WriteReq accesses
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system.cpu.dcache.WriteReq_misses 3153592 # number of WriteReq misses
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system.cpu.dcache.WriteReq_mshr_hits 1270515 # number of WriteReq MSHR hits
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system.cpu.dcache.WriteReq_mshr_miss_latency 26783900812 # number of WriteReq MSHR miss cycles
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system.cpu.dcache.WriteReq_mshr_miss_rate 0.011716 # mshr miss rate for WriteReq accesses
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|
system.cpu.dcache.WriteReq_mshr_misses 1883077 # number of WriteReq MSHR misses
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|
|
|
|
system.cpu.dcache.avg_blocked_cycles_no_mshrs 972.020892 # average number of cycles each access was blocked
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system.cpu.dcache.avg_blocked_cycles_no_targets 2881.979981 # average number of cycles each access was blocked
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system.cpu.dcache.avg_refs 66.650940 # Average number of references to valid blocks.
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system.cpu.dcache.blocked_no_mshrs 659829 # number of cycles access was blocked
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system.cpu.dcache.blocked_no_targets 896062 # number of cycles access was blocked
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system.cpu.dcache.blocked_cycles_no_mshrs 641367573 # number of cycles access was blocked
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|
|
|
|
system.cpu.dcache.blocked_cycles_no_targets 2582432746 # number of cycles access was blocked
|
2006-10-12 21:04:14 +02:00
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|
|
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
2006-12-05 01:07:00 +01:00
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|
|
system.cpu.dcache.demand_accesses 626904981 # number of demand (read+write) accesses
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system.cpu.dcache.demand_avg_miss_latency 6878.830546 # average overall miss latency
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system.cpu.dcache.demand_avg_mshr_miss_latency 7431.476663 # average overall mshr miss latency
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|
|
|
|
system.cpu.dcache.demand_hits 611672543 # number of demand (read+write) hits
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|
|
|
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system.cpu.dcache.demand_miss_latency 104781359801 # number of demand (read+write) miss cycles
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system.cpu.dcache.demand_miss_rate 0.024298 # miss rate for demand accesses
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system.cpu.dcache.demand_misses 15232438 # number of demand (read+write) misses
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system.cpu.dcache.demand_mshr_hits 6055185 # number of demand (read+write) MSHR hits
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system.cpu.dcache.demand_mshr_miss_latency 68200541502 # number of demand (read+write) MSHR miss cycles
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|
system.cpu.dcache.demand_mshr_miss_rate 0.014639 # mshr miss rate for demand accesses
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system.cpu.dcache.demand_mshr_misses 9177253 # number of demand (read+write) MSHR misses
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2006-10-12 21:04:14 +02:00
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|
system.cpu.dcache.fast_writes 0 # number of fast writes performed
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|
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|
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
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system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
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2006-12-05 01:07:00 +01:00
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system.cpu.dcache.overall_accesses 626904981 # number of overall (read+write) accesses
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system.cpu.dcache.overall_avg_miss_latency 6878.830546 # average overall miss latency
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system.cpu.dcache.overall_avg_mshr_miss_latency 7431.476663 # average overall mshr miss latency
|
2006-10-12 21:04:14 +02:00
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|
system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
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2006-12-05 01:07:00 +01:00
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system.cpu.dcache.overall_hits 611672543 # number of overall hits
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|
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system.cpu.dcache.overall_miss_latency 104781359801 # number of overall miss cycles
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system.cpu.dcache.overall_miss_rate 0.024298 # miss rate for overall accesses
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system.cpu.dcache.overall_misses 15232438 # number of overall misses
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system.cpu.dcache.overall_mshr_hits 6055185 # number of overall MSHR hits
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system.cpu.dcache.overall_mshr_miss_latency 68200541502 # number of overall MSHR miss cycles
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|
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system.cpu.dcache.overall_mshr_miss_rate 0.014639 # mshr miss rate for overall accesses
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|
system.cpu.dcache.overall_mshr_misses 9177253 # number of overall MSHR misses
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2006-10-12 21:04:14 +02:00
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|
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system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
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|
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|
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
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|
|
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|
system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
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|
system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
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|
system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
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|
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|
|
system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
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|
system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
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system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
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|
system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
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|
|
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|
system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
|
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|
|
|
system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
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2006-12-05 01:07:00 +01:00
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|
|
system.cpu.dcache.replacements 9173157 # number of replacements
|
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|
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|
system.cpu.dcache.sampled_refs 9177253 # Sample count of references to valid blocks.
|
2006-10-12 21:04:14 +02:00
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|
|
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
2006-12-05 01:07:00 +01:00
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|
|
system.cpu.dcache.tagsinuse 4093.061614 # Cycle average of tags in use
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|
system.cpu.dcache.total_refs 611672543 # Total number of references to valid blocks.
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|
|
|
|
system.cpu.dcache.warmup_cycle 39716000 # Cycle when the warmup percentage was hit.
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system.cpu.dcache.writebacks 2244715 # number of writebacks
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|
|
|
|
system.cpu.decode.DECODE:BlockedCycles 3168036062 # Number of cycles decode is blocked
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system.cpu.decode.DECODE:BranchMispred 511 # Number of times decode detected a branch misprediction
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system.cpu.decode.DECODE:BranchResolved 48557069 # Number of times decode resolved a branch
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|
|
|
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system.cpu.decode.DECODE:DecodedInsts 6641345328 # Number of instructions handled by decode
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|
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|
system.cpu.decode.DECODE:IdleCycles 1298412925 # Number of cycles decode is idle
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|
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system.cpu.decode.DECODE:RunCycles 1202046298 # Number of cycles decode is running
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|
|
|
|
system.cpu.decode.DECODE:SquashCycles 501929792 # Number of cycles decode is squashing
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|
|
|
|
system.cpu.decode.DECODE:SquashedInsts 1629 # Number of squashed instructions handled by decode
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|
|
|
|
system.cpu.decode.DECODE:UnblockCycles 10462509 # Number of cycles decode is unblocking
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|
|
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system.cpu.fetch.Branches 1098978166 # Number of branches that fetch encountered
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|
|
|
|
system.cpu.fetch.CacheLines 541280485 # Number of cache lines fetched
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|
|
|
|
system.cpu.fetch.Cycles 1955627258 # Number of cycles fetch has run and was not squashing or blocked
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|
|
|
|
system.cpu.fetch.IcacheSquashes 11328270 # Number of outstanding Icache misses that were squashed
|
|
|
|
|
system.cpu.fetch.Insts 7938391391 # Number of instructions fetch has processed
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|
|
|
|
system.cpu.fetch.SquashCycles 242391708 # Number of cycles fetch has spent squashing
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|
|
|
|
system.cpu.fetch.branchRate 0.177803 # Number of branch fetches per cycle
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|
|
|
|
system.cpu.fetch.icacheStallCycles 541280485 # Number of cycles fetch is stalled on an Icache miss
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|
|
|
|
system.cpu.fetch.predictedBranches 1081038949 # Number of branches that fetch has predicted taken
|
|
|
|
|
system.cpu.fetch.rate 1.284345 # Number of inst fetches per cycle
|
2006-10-12 21:04:14 +02:00
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|
|
system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total)
|
2006-12-05 01:07:00 +01:00
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|
|
system.cpu.fetch.rateDist.samples 6180887586
|
2006-10-12 21:04:14 +02:00
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|
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system.cpu.fetch.rateDist.min_value 0
|
2006-12-05 01:07:00 +01:00
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|
|
0 4766540797 7711.74%
|
|
|
|
|
1 80764415 130.67%
|
|
|
|
|
2 63598055 102.89%
|
|
|
|
|
3 58203597 94.17%
|
|
|
|
|
4 424384465 686.61%
|
|
|
|
|
5 69131012 111.85%
|
|
|
|
|
6 94422767 152.77%
|
|
|
|
|
7 44649271 72.24%
|
|
|
|
|
8 579193207 937.07%
|
2006-10-12 21:04:14 +02:00
|
|
|
system.cpu.fetch.rateDist.max_value 8
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|
|
|
|
system.cpu.fetch.rateDist.end_dist
|
|
|
|
|
|
2006-12-05 01:07:00 +01:00
|
|
|
system.cpu.icache.ReadReq_accesses 541280484 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.icache.ReadReq_avg_miss_latency 5378.819380 # average ReadReq miss latency
|
|
|
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency 4616.750831 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.icache.ReadReq_hits 541279194 # number of ReadReq hits
|
|
|
|
|
system.cpu.icache.ReadReq_miss_latency 6938677 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.icache.ReadReq_miss_rate 0.000002 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.icache.ReadReq_misses 1290 # number of ReadReq misses
|
|
|
|
|
system.cpu.icache.ReadReq_mshr_hits 387 # number of ReadReq MSHR hits
|
|
|
|
|
system.cpu.icache.ReadReq_mshr_miss_latency 4168926 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.icache.ReadReq_mshr_miss_rate 0.000002 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.icache.ReadReq_mshr_misses 903 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.icache.avg_blocked_cycles_no_targets 4207.523810 # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.icache.avg_refs 599423.249169 # Average number of references to valid blocks.
|
2006-10-12 21:04:14 +02:00
|
|
|
system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
|
2006-12-05 01:07:00 +01:00
|
|
|
system.cpu.icache.blocked_no_targets 21 # number of cycles access was blocked
|
2006-10-12 21:04:14 +02:00
|
|
|
system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
|
2006-12-05 01:07:00 +01:00
|
|
|
system.cpu.icache.blocked_cycles_no_targets 88358 # number of cycles access was blocked
|
2006-10-12 21:04:14 +02:00
|
|
|
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
2006-12-05 01:07:00 +01:00
|
|
|
system.cpu.icache.demand_accesses 541280484 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.icache.demand_avg_miss_latency 5378.819380 # average overall miss latency
|
|
|
|
|
system.cpu.icache.demand_avg_mshr_miss_latency 4616.750831 # average overall mshr miss latency
|
|
|
|
|
system.cpu.icache.demand_hits 541279194 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.icache.demand_miss_latency 6938677 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.icache.demand_miss_rate 0.000002 # miss rate for demand accesses
|
|
|
|
|
system.cpu.icache.demand_misses 1290 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.icache.demand_mshr_hits 387 # number of demand (read+write) MSHR hits
|
|
|
|
|
system.cpu.icache.demand_mshr_miss_latency 4168926 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.icache.demand_mshr_miss_rate 0.000002 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.icache.demand_mshr_misses 903 # number of demand (read+write) MSHR misses
|
2006-10-12 21:04:14 +02:00
|
|
|
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
|
|
|
|
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
|
|
|
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
2006-12-05 01:07:00 +01:00
|
|
|
system.cpu.icache.overall_accesses 541280484 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.icache.overall_avg_miss_latency 5378.819380 # average overall miss latency
|
|
|
|
|
system.cpu.icache.overall_avg_mshr_miss_latency 4616.750831 # average overall mshr miss latency
|
2006-10-12 21:04:14 +02:00
|
|
|
system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
2006-12-05 01:07:00 +01:00
|
|
|
system.cpu.icache.overall_hits 541279194 # number of overall hits
|
|
|
|
|
system.cpu.icache.overall_miss_latency 6938677 # number of overall miss cycles
|
|
|
|
|
system.cpu.icache.overall_miss_rate 0.000002 # miss rate for overall accesses
|
|
|
|
|
system.cpu.icache.overall_misses 1290 # number of overall misses
|
|
|
|
|
system.cpu.icache.overall_mshr_hits 387 # number of overall MSHR hits
|
|
|
|
|
system.cpu.icache.overall_mshr_miss_latency 4168926 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu.icache.overall_mshr_miss_rate 0.000002 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.icache.overall_mshr_misses 903 # number of overall MSHR misses
|
2006-10-12 21:04:14 +02:00
|
|
|
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
|
|
|
|
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
|
|
|
|
system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
|
|
|
|
|
system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
|
|
|
|
|
system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
|
|
|
|
|
system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
|
|
|
|
|
system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
|
|
|
|
|
system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
|
|
|
|
|
system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
|
|
|
|
|
system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
|
|
|
|
|
system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
|
2006-12-05 01:07:00 +01:00
|
|
|
system.cpu.icache.replacements 1 # number of replacements
|
|
|
|
|
system.cpu.icache.sampled_refs 903 # Sample count of references to valid blocks.
|
2006-10-12 21:04:14 +02:00
|
|
|
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
2006-12-05 01:07:00 +01:00
|
|
|
system.cpu.icache.tagsinuse 716.132429 # Cycle average of tags in use
|
|
|
|
|
system.cpu.icache.total_refs 541279194 # Total number of references to valid blocks.
|
2006-10-12 21:04:14 +02:00
|
|
|
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
|
|
|
system.cpu.icache.writebacks 0 # number of writebacks
|
2006-12-05 01:07:00 +01:00
|
|
|
system.cpu.idleCycles 18731384505 # Total number of cycles that the CPU has spent unscheduled due to idling
|
|
|
|
|
system.cpu.iew.EXEC:branches 250098653 # Number of branches executed
|
|
|
|
|
system.cpu.iew.EXEC:nop 147895912 # number of nop insts executed
|
|
|
|
|
system.cpu.iew.EXEC:rate 0.440971 # Inst execution rate
|
|
|
|
|
system.cpu.iew.EXEC:refs 918923683 # number of memory reference insts executed
|
|
|
|
|
system.cpu.iew.EXEC:stores 177016651 # Number of stores executed
|
2006-10-12 21:04:14 +02:00
|
|
|
system.cpu.iew.EXEC:swp 0 # number of swp insts executed
|
2006-12-05 01:07:00 +01:00
|
|
|
system.cpu.iew.WB:consumers 1839076786 # num instructions consuming a value
|
|
|
|
|
system.cpu.iew.WB:count 2471794731 # cumulative count of insts written-back
|
|
|
|
|
system.cpu.iew.WB:fanout 0.797100 # average fanout of values written-back
|
2006-10-12 21:04:14 +02:00
|
|
|
system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
|
|
|
|
|
system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
2006-12-05 01:07:00 +01:00
|
|
|
system.cpu.iew.WB:producers 1465928228 # num instructions producing a value
|
|
|
|
|
system.cpu.iew.WB:rate 0.399909 # insts written-back per cycle
|
|
|
|
|
system.cpu.iew.WB:sent 2475054397 # cumulative count of insts sent to commit
|
|
|
|
|
system.cpu.iew.branchMispredicts 21956654 # Number of branch mispredicts detected at execute
|
|
|
|
|
system.cpu.iew.iewBlockCycles 2471410228 # Number of cycles IEW is blocking
|
|
|
|
|
system.cpu.iew.iewDispLoadInsts 938731548 # Number of dispatched load instructions
|
|
|
|
|
system.cpu.iew.iewDispNonSpecInsts 45 # Number of dispatched non-speculative instructions
|
|
|
|
|
system.cpu.iew.iewDispSquashedInsts 111073783 # Number of squashed instructions skipped by dispatch
|
|
|
|
|
system.cpu.iew.iewDispStoreInsts 389309694 # Number of dispatched store instructions
|
|
|
|
|
system.cpu.iew.iewDispatchedInsts 4831881465 # Number of instructions dispatched to IQ
|
|
|
|
|
system.cpu.iew.iewExecLoadInsts 741907032 # Number of load instructions executed
|
|
|
|
|
system.cpu.iew.iewExecSquashedInsts 286170200 # Number of squashed instructions skipped in execute
|
|
|
|
|
system.cpu.iew.iewExecutedInsts 2725595031 # Number of executed instructions
|
|
|
|
|
system.cpu.iew.iewIQFullEvents 1536928 # Number of times the IQ has become full, causing a stall
|
2006-10-12 21:04:14 +02:00
|
|
|
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
2006-12-05 01:07:00 +01:00
|
|
|
system.cpu.iew.iewLSQFullEvents 161620 # Number of times the LSQ has become full, causing a stall
|
|
|
|
|
system.cpu.iew.iewSquashCycles 501929792 # Number of cycles IEW is squashing
|
|
|
|
|
system.cpu.iew.iewUnblockCycles 6153373 # Number of cycles IEW is unblocking
|
|
|
|
|
system.cpu.iew.lsq.thread.0.blockedLoads 8 # Number of blocked loads due to partial load-store forwarding
|
|
|
|
|
system.cpu.iew.lsq.thread.0.cacheBlocked 233590575 # Number of times an access to memory failed due to the cache being blocked
|
|
|
|
|
system.cpu.iew.lsq.thread.0.forwLoads 41593346 # Number of loads that had data forwarded from stores
|
|
|
|
|
system.cpu.iew.lsq.thread.0.ignoredResponses 516978 # Number of memory responses ignored because the instruction is squashed
|
2006-10-12 21:04:14 +02:00
|
|
|
system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
|
|
|
|
system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
2006-12-05 01:07:00 +01:00
|
|
|
system.cpu.iew.lsq.thread.0.memOrderViolation 47985 # Number of memory ordering violations
|
|
|
|
|
system.cpu.iew.lsq.thread.0.rescheduledLoads 8 # Number of loads that were rescheduled
|
|
|
|
|
system.cpu.iew.lsq.thread.0.squashedLoads 493065187 # Number of loads squashed
|
|
|
|
|
system.cpu.iew.lsq.thread.0.squashedStores 228404712 # Number of stores squashed
|
|
|
|
|
system.cpu.iew.memOrderViolationEvents 47985 # Number of memory order violations
|
|
|
|
|
system.cpu.iew.predictedNotTakenIncorrect 11190791 # Number of branches that were predicted not taken incorrectly
|
|
|
|
|
system.cpu.iew.predictedTakenIncorrect 10765863 # Number of branches that were predicted taken incorrectly
|
|
|
|
|
system.cpu.ipc 0.069686 # IPC: Instructions Per Cycle
|
|
|
|
|
system.cpu.ipc_total 0.069686 # IPC: Total IPC of All Threads
|
|
|
|
|
system.cpu.iq.ISSUE:FU_type_0 3011765231 # Type of FU issued
|
2006-10-12 21:04:14 +02:00
|
|
|
system.cpu.iq.ISSUE:FU_type_0.start_dist
|
2006-12-05 01:07:00 +01:00
|
|
|
(null) 0 0.00% # Type of FU issued
|
|
|
|
|
IntAlu 1970711875 65.43% # Type of FU issued
|
|
|
|
|
IntMult 679 0.00% # Type of FU issued
|
2006-10-12 21:04:14 +02:00
|
|
|
IntDiv 0 0.00% # Type of FU issued
|
2006-12-05 01:07:00 +01:00
|
|
|
FloatAdd 206 0.00% # Type of FU issued
|
|
|
|
|
FloatCmp 15 0.00% # Type of FU issued
|
|
|
|
|
FloatCvt 146 0.00% # Type of FU issued
|
|
|
|
|
FloatMult 12 0.00% # Type of FU issued
|
|
|
|
|
FloatDiv 24 0.00% # Type of FU issued
|
2006-10-12 21:04:14 +02:00
|
|
|
FloatSqrt 0 0.00% # Type of FU issued
|
2006-12-05 01:07:00 +01:00
|
|
|
MemRead 862446019 28.64% # Type of FU issued
|
|
|
|
|
MemWrite 178606255 5.93% # Type of FU issued
|
2006-10-12 21:04:14 +02:00
|
|
|
IprAccess 0 0.00% # Type of FU issued
|
|
|
|
|
InstPrefetch 0 0.00% # Type of FU issued
|
|
|
|
|
system.cpu.iq.ISSUE:FU_type_0.end_dist
|
2006-12-05 01:07:00 +01:00
|
|
|
system.cpu.iq.ISSUE:fu_busy_cnt 11307551 # FU busy when requested
|
|
|
|
|
system.cpu.iq.ISSUE:fu_busy_rate 0.003754 # FU busy rate (busy events/executed inst)
|
2006-10-12 21:04:14 +02:00
|
|
|
system.cpu.iq.ISSUE:fu_full.start_dist
|
|
|
|
|
(null) 0 0.00% # attempts to use FU when none available
|
2006-12-05 01:07:00 +01:00
|
|
|
IntAlu 509990 4.51% # attempts to use FU when none available
|
2006-10-12 21:04:14 +02:00
|
|
|
IntMult 0 0.00% # attempts to use FU when none available
|
|
|
|
|
IntDiv 0 0.00% # attempts to use FU when none available
|
|
|
|
|
FloatAdd 0 0.00% # attempts to use FU when none available
|
|
|
|
|
FloatCmp 0 0.00% # attempts to use FU when none available
|
|
|
|
|
FloatCvt 0 0.00% # attempts to use FU when none available
|
|
|
|
|
FloatMult 0 0.00% # attempts to use FU when none available
|
|
|
|
|
FloatDiv 0 0.00% # attempts to use FU when none available
|
|
|
|
|
FloatSqrt 0 0.00% # attempts to use FU when none available
|
2006-12-05 01:07:00 +01:00
|
|
|
MemRead 9173598 81.13% # attempts to use FU when none available
|
|
|
|
|
MemWrite 1623963 14.36% # attempts to use FU when none available
|
2006-10-12 21:04:14 +02:00
|
|
|
IprAccess 0 0.00% # attempts to use FU when none available
|
|
|
|
|
InstPrefetch 0 0.00% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.ISSUE:fu_full.end_dist
|
|
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle
|
2006-12-05 01:07:00 +01:00
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle.samples 6180887586
|
2006-10-12 21:04:14 +02:00
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle.min_value 0
|
2006-12-05 01:07:00 +01:00
|
|
|
0 4878979324 7893.65%
|
|
|
|
|
1 360055339 582.53%
|
|
|
|
|
2 481197713 778.53%
|
|
|
|
|
3 280796976 454.30%
|
|
|
|
|
4 94854448 153.46%
|
|
|
|
|
5 50760526 82.12%
|
|
|
|
|
6 26723872 43.24%
|
|
|
|
|
7 6795220 10.99%
|
|
|
|
|
8 724168 1.17%
|
2006-10-12 21:04:14 +02:00
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle.max_value 8
|
|
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle.end_dist
|
|
|
|
|
|
2006-12-05 01:07:00 +01:00
|
|
|
system.cpu.iq.ISSUE:rate 0.487271 # Inst issue rate
|
|
|
|
|
system.cpu.iq.iqInstsAdded 4683985508 # Number of instructions added to the IQ (excludes non-spec)
|
|
|
|
|
system.cpu.iq.iqInstsIssued 3011765231 # Number of instructions issued
|
|
|
|
|
system.cpu.iq.iqNonSpecInstsAdded 45 # Number of non-speculative instructions added to the IQ
|
|
|
|
|
system.cpu.iq.iqSquashedInstsExamined 2916477755 # Number of squashed instructions iterated over during squash; mainly for profiling
|
|
|
|
|
system.cpu.iq.iqSquashedInstsIssued 6096386 # Number of squashed instructions issued
|
|
|
|
|
system.cpu.iq.iqSquashedNonSpecRemoved 16 # Number of squashed non-spec instructions that were removed
|
|
|
|
|
system.cpu.iq.iqSquashedOperandsExamined 3050829124 # Number of squashed operands that are examined and possibly removed from graph
|
|
|
|
|
system.cpu.l2cache.ReadReq_accesses 9178154 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency 7336.712513 # average ReadReq miss latency
|
|
|
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2076.036854 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.l2cache.ReadReq_hits 7008989 # number of ReadReq hits
|
|
|
|
|
system.cpu.l2cache.ReadReq_miss_latency 15914539999 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadReq_miss_rate 0.236340 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_misses 2169165 # number of ReadReq misses
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency 4503266483 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.236340 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_misses 2169165 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.l2cache.WriteReqNoAck|Writeback_accesses 2244715 # number of WriteReqNoAck|Writeback accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.WriteReqNoAck|Writeback_hits 2215400 # number of WriteReqNoAck|Writeback hits
|
|
|
|
|
system.cpu.l2cache.WriteReqNoAck|Writeback_miss_rate 0.013060 # miss rate for WriteReqNoAck|Writeback accesses
|
|
|
|
|
system.cpu.l2cache.WriteReqNoAck|Writeback_misses 29315 # number of WriteReqNoAck|Writeback misses
|
|
|
|
|
system.cpu.l2cache.WriteReqNoAck|Writeback_mshr_miss_rate 0.013060 # mshr miss rate for WriteReqNoAck|Writeback accesses
|
|
|
|
|
system.cpu.l2cache.WriteReqNoAck|Writeback_mshr_misses 29315 # number of WriteReqNoAck|Writeback MSHR misses
|
2006-10-12 21:04:14 +02:00
|
|
|
system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
|
2006-12-05 01:07:00 +01:00
|
|
|
system.cpu.l2cache.avg_refs 4.252507 # Average number of references to valid blocks.
|
2006-10-12 21:04:14 +02:00
|
|
|
system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
2006-12-05 01:07:00 +01:00
|
|
|
system.cpu.l2cache.demand_accesses 9178154 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.demand_avg_miss_latency 7336.712513 # average overall miss latency
|
|
|
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency 2076.036854 # average overall mshr miss latency
|
|
|
|
|
system.cpu.l2cache.demand_hits 7008989 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.l2cache.demand_miss_latency 15914539999 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_miss_rate 0.236340 # miss rate for demand accesses
|
|
|
|
|
system.cpu.l2cache.demand_misses 2169165 # number of demand (read+write) misses
|
2006-10-12 21:04:14 +02:00
|
|
|
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
2006-12-05 01:07:00 +01:00
|
|
|
system.cpu.l2cache.demand_mshr_miss_latency 4503266483 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_mshr_miss_rate 0.236340 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.l2cache.demand_mshr_misses 2169165 # number of demand (read+write) MSHR misses
|
2006-10-12 21:04:14 +02:00
|
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
|
|
|
|
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
|
|
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
2006-12-05 01:07:00 +01:00
|
|
|
system.cpu.l2cache.overall_accesses 11422869 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.overall_avg_miss_latency 7238.883228 # average overall miss latency
|
|
|
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency 2076.036854 # average overall mshr miss latency
|
2006-10-12 21:04:14 +02:00
|
|
|
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
2006-12-05 01:07:00 +01:00
|
|
|
system.cpu.l2cache.overall_hits 9224389 # number of overall hits
|
|
|
|
|
system.cpu.l2cache.overall_miss_latency 15914539999 # number of overall miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_miss_rate 0.192463 # miss rate for overall accesses
|
|
|
|
|
system.cpu.l2cache.overall_misses 2198480 # number of overall misses
|
2006-10-12 21:04:14 +02:00
|
|
|
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
2006-12-05 01:07:00 +01:00
|
|
|
system.cpu.l2cache.overall_mshr_miss_latency 4503266483 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_mshr_miss_rate 0.189897 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.l2cache.overall_mshr_misses 2169165 # number of overall MSHR misses
|
2006-10-12 21:04:14 +02:00
|
|
|
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
|
|
|
|
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
|
|
|
|
system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
|
|
|
|
|
system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
|
|
|
|
|
system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
|
|
|
|
|
system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
|
|
|
|
|
system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
|
|
|
|
|
system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
|
|
|
|
|
system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
|
|
|
|
|
system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
|
|
|
|
|
system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
|
2006-12-05 01:07:00 +01:00
|
|
|
system.cpu.l2cache.replacements 2136397 # number of replacements
|
|
|
|
|
system.cpu.l2cache.sampled_refs 2169165 # Sample count of references to valid blocks.
|
2006-10-12 21:04:14 +02:00
|
|
|
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
2006-12-05 01:07:00 +01:00
|
|
|
system.cpu.l2cache.tagsinuse 32623.472165 # Cycle average of tags in use
|
|
|
|
|
system.cpu.l2cache.total_refs 9224389 # Total number of references to valid blocks.
|
|
|
|
|
system.cpu.l2cache.warmup_cycle 520424000 # Cycle when the warmup percentage was hit.
|
|
|
|
|
system.cpu.l2cache.writebacks 1039341 # number of writebacks
|
|
|
|
|
system.cpu.numCycles 6180887586 # number of cpu cycles simulated
|
|
|
|
|
system.cpu.rename.RENAME:BlockCycles 2894504060 # Number of cycles rename is blocking
|
|
|
|
|
system.cpu.rename.RENAME:CommittedMaps 1376202963 # Number of HB maps that are committed
|
|
|
|
|
system.cpu.rename.RENAME:IQFullEvents 6511750 # Number of times rename has blocked due to IQ full
|
|
|
|
|
system.cpu.rename.RENAME:IdleCycles 1451413065 # Number of cycles rename is idle
|
|
|
|
|
system.cpu.rename.RENAME:LSQFullEvents 266047107 # Number of times rename has blocked due to LSQ full
|
|
|
|
|
system.cpu.rename.RENAME:ROBFullEvents 3125053 # Number of times rename has blocked due to ROB full
|
|
|
|
|
system.cpu.rename.RENAME:RenameLookups 8501370508 # Number of register rename lookups that rename has made
|
|
|
|
|
system.cpu.rename.RENAME:RenamedInsts 6112671585 # Number of instructions processed by rename
|
|
|
|
|
system.cpu.rename.RENAME:RenamedOperands 4584914520 # Number of destination operands rename has renamed
|
|
|
|
|
system.cpu.rename.RENAME:RunCycles 1056218413 # Number of cycles rename is running
|
|
|
|
|
system.cpu.rename.RENAME:SquashCycles 501929792 # Number of cycles rename is squashing
|
|
|
|
|
system.cpu.rename.RENAME:UnblockCycles 276756270 # Number of cycles rename is unblocking
|
|
|
|
|
system.cpu.rename.RENAME:UndoneMaps 3208711557 # Number of HB maps that are undone due to squashing
|
|
|
|
|
system.cpu.rename.RENAME:serializeStallCycles 65986 # count of cycles rename stalled for serializing inst
|
|
|
|
|
system.cpu.rename.RENAME:serializingInsts 49 # count of serializing insts renamed
|
|
|
|
|
system.cpu.rename.RENAME:skidInsts 1117979447 # count of insts added to the skid buffer
|
|
|
|
|
system.cpu.rename.RENAME:tempSerializingInsts 47 # count of temporary serializing insts renamed
|
|
|
|
|
system.cpu.timesIdled 7293390 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
|
|
|
|
system.cpu.workload.PROG:num_syscalls 29 # Number of system calls
|
2006-10-12 21:04:14 +02:00
|
|
|
|
|
|
|
|
---------- End Simulation Statistics ----------
|
