system.cpu.workload.num_syscalls 37 # Number of system calls
system.cpu.numCycles 1008516526 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 928789150 # Number of instructions committed
system.cpu.committedOps 928789150 # Number of ops (including micro ops) committed
system.cpu.discardedOps 316849 # Number of ops (including micro ops) which were discarded before commit
system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching
system.cpu.cpi 1.085840 # CPI: cycles per instruction
system.cpu.ipc 0.920946 # IPC: instructions per cycle
system.cpu.op_class_0::No_OpClass 86206875 9.28% 9.28% # Class of committed instruction
system.cpu.op_class_0::IntAlu 486529511 52.38% 61.66% # Class of committed instruction
system.cpu.op_class_0::IntMult 7040 0.00% 61.67% # Class of committed instruction
system.cpu.op_class_0::IntDiv 0 0.00% 61.67% # Class of committed instruction
system.cpu.op_class_0::FloatAdd 13018262 1.40% 63.07% # Class of committed instruction
system.cpu.op_class_0::FloatCmp 3826477 0.41% 63.48% # Class of committed instruction
system.cpu.op_class_0::FloatCvt 3187663 0.34% 63.82% # Class of committed instruction
system.cpu.op_class_0::FloatMult 4 0.00% 63.82% # Class of committed instruction
system.cpu.op_class_0::FloatDiv 0 0.00% 63.82% # Class of committed instruction
system.cpu.op_class_0::FloatSqrt 0 0.00% 63.82% # Class of committed instruction
system.cpu.op_class_0::SimdAdd 0 0.00% 63.82% # Class of committed instruction
system.cpu.op_class_0::SimdAddAcc 0 0.00% 63.82% # Class of committed instruction
system.cpu.op_class_0::SimdAlu 0 0.00% 63.82% # Class of committed instruction
system.cpu.op_class_0::SimdCmp 0 0.00% 63.82% # Class of committed instruction
system.cpu.op_class_0::SimdCvt 0 0.00% 63.82% # Class of committed instruction
system.cpu.op_class_0::SimdMisc 0 0.00% 63.82% # Class of committed instruction
system.cpu.op_class_0::SimdMult 0 0.00% 63.82% # Class of committed instruction
system.cpu.op_class_0::SimdMultAcc 0 0.00% 63.82% # Class of committed instruction
system.cpu.op_class_0::SimdShift 0 0.00% 63.82% # Class of committed instruction
system.cpu.op_class_0::SimdShiftAcc 0 0.00% 63.82% # Class of committed instruction
system.cpu.op_class_0::SimdSqrt 0 0.00% 63.82% # Class of committed instruction
system.cpu.op_class_0::SimdFloatAdd 0 0.00% 63.82% # Class of committed instruction
system.cpu.op_class_0::SimdFloatAlu 0 0.00% 63.82% # Class of committed instruction
system.cpu.op_class_0::SimdFloatCmp 0 0.00% 63.82% # Class of committed instruction
system.cpu.op_class_0::SimdFloatCvt 0 0.00% 63.82% # Class of committed instruction
system.cpu.op_class_0::SimdFloatDiv 0 0.00% 63.82% # Class of committed instruction
system.cpu.op_class_0::SimdFloatMisc 0 0.00% 63.82% # Class of committed instruction
system.cpu.op_class_0::SimdFloatMult 0 0.00% 63.82% # Class of committed instruction
system.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 63.82% # Class of committed instruction
system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 63.82% # Class of committed instruction
system.cpu.op_class_0::MemRead 237705247 25.59% 89.42% # Class of committed instruction
system.cpu.op_class_0::MemWrite 98308071 10.58% 100.00% # Class of committed instruction
system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
system.cpu.op_class_0::total 928789150 # Class of committed instruction
system.cpu.tickCycles 957154131 # Number of cycles that the object actually ticked
system.cpu.idleCycles 51362395 # Total number of cycles that the object has spent stopped
system.cpu.dcache.tags.replacements 776530 # number of replacements
system.cpu.dcache.tags.tagsinuse 4092.342308 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 321596153 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 780626 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 411.972126 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 901583500 # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data 4092.342308 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.999107 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.999107 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0 56 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1 214 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2 956 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::3 1398 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::4 1472 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 645671096 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 645671096 # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data 223432106 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 223432106 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 98164047 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 98164047 # number of WriteReq hits
system.cpu.dcache.demand_hits::cpu.data 321596153 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 321596153 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 321596153 # number of overall hits
system.cpu.dcache.overall_hits::total 321596153 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 711929 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 711929 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 137153 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 137153 # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data 849082 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 849082 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 849082 # number of overall misses
system.cpu.dcache.overall_misses::total 849082 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 25457059500 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 25457059500 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 10110916000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 10110916000 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 35567975500 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 35567975500 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 35567975500 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 35567975500 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 224144035 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 224144035 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 98301200 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 98301200 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 322445235 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 322445235 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 322445235 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 322445235 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.003176 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.003176 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001395 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.001395 # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.002633 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.002633 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.002633 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.002633 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 35757.862792 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 35757.862792 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 73719.976960 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 73719.976960 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 41889.918170 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 41889.918170 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 41889.918170 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 41889.918170 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.writebacks::writebacks 88489 # number of writebacks
system.cpu.dcache.writebacks::total 88489 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 314 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 314 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 68142 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 68142 # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data 68456 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 68456 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 68456 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 68456 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 711615 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 711615 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 69011 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 69011 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 780626 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 780626 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 780626 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 780626 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 24738054000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 24738054000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5071007000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 5071007000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 29809061000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 29809061000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 29809061000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 29809061000 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.003175 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.003175 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000702 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000702 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002421 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.002421 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002421 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.002421 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 34763.255412 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 34763.255412 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 73481.140688 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 73481.140688 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 38186.098080 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 38186.098080 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 38186.098080 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 38186.098080 # average overall mshr miss latency
system.cpu.icache.tags.replacements 10567 # number of replacements
system.cpu.icache.tags.tagsinuse 1686.158478 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 285751480 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 12309 # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs 23214.841173 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst 1686.158478 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.823320 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.823320 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024 1742 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0 62 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1 103 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::2 2 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::4 1574 # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024 0.850586 # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses 571539889 # Number of tag accesses
system.cpu.icache.tags.data_accesses 571539889 # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst 285751480 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 285751480 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 285751480 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 285751480 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 285751480 # number of overall hits
system.cpu.icache.overall_hits::total 285751480 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 12310 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 12310 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 12310 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 12310 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 12310 # number of overall misses
system.cpu.icache.overall_misses::total 12310 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 352350500 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 352350500 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 352350500 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 352350500 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 352350500 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 352350500 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 285763790 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 285763790 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 285763790 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 285763790 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 285763790 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 285763790 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000043 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.000043 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.000043 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.000043 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.000043 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.000043 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 28623.111292 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 28623.111292 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 28623.111292 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 28623.111292 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 28623.111292 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 28623.111292 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.writebacks::writebacks 10567 # number of writebacks
system.cpu.icache.writebacks::total 10567 # number of writebacks
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 12310 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 12310 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 12310 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 12310 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 12310 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 12310 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 340041500 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 340041500 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 340041500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 340041500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 340041500 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 340041500 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000043 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000043 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000043 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.000043 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000043 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.000043 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 27623.192526 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 27623.192526 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 27623.192526 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 27623.192526 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 27623.192526 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 27623.192526 # average overall mshr miss latency
system.cpu.l2cache.tags.replacements 259940 # number of replacements
system.cpu.l2cache.tags.tagsinuse 32579.649991 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 1218214 # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs 292676 # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs 4.162330 # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks 2630.640415 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst 79.297977 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 29869.711599 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks 0.080281 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.002420 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data 0.911551 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total 0.994252 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1024 32736 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 154 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 280 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 305 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 2976 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 29021 # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.999023 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 13001951 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 13001951 # Number of data accesses
system.cpu.l2cache.WritebackDirty_hits::writebacks 88489 # number of WritebackDirty hits
system.cpu.l2cache.WritebackDirty_hits::total 88489 # number of WritebackDirty hits
system.cpu.l2cache.WritebackClean_hits::writebacks 10567 # number of WritebackClean hits
system.cpu.l2cache.WritebackClean_hits::total 10567 # number of WritebackClean hits
system.cpu.l2cache.ReadExReq_hits::cpu.data 2366 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total 2366 # number of ReadExReq hits
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 9417 # number of ReadCleanReq hits
system.cpu.l2cache.ReadCleanReq_hits::total 9417 # number of ReadCleanReq hits
system.cpu.l2cache.ReadSharedReq_hits::cpu.data 488885 # number of ReadSharedReq hits
system.cpu.l2cache.ReadSharedReq_hits::total 488885 # number of ReadSharedReq hits
system.cpu.l2cache.demand_hits::cpu.inst 9417 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data 491251 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 500668 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst 9417 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data 491251 # number of overall hits
system.cpu.l2cache.overall_hits::total 500668 # number of overall hits
system.cpu.l2cache.ReadExReq_misses::cpu.data 66645 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 66645 # number of ReadExReq misses
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 2893 # number of ReadCleanReq misses
system.cpu.l2cache.ReadCleanReq_misses::total 2893 # number of ReadCleanReq misses
system.cpu.l2cache.ReadSharedReq_misses::cpu.data 222730 # number of ReadSharedReq misses
system.cpu.l2cache.ReadSharedReq_misses::total 222730 # number of ReadSharedReq misses
system.cpu.l2cache.demand_misses::cpu.inst 2893 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 289375 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 292268 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst 2893 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 289375 # number of overall misses
system.cpu.l2cache.overall_misses::total 292268 # number of overall misses
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4942620000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 4942620000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 222699500 # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::total 222699500 # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 18537323500 # number of ReadSharedReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::total 18537323500 # number of ReadSharedReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 222699500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 23479943500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 23702643000 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 222699500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 23479943500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 23702643000 # number of overall miss cycles
system.cpu.l2cache.WritebackDirty_accesses::writebacks 88489 # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackDirty_accesses::total 88489 # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::writebacks 10567 # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::total 10567 # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data 69011 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 69011 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 12310 # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::total 12310 # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 711615 # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::total 711615 # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst 12310 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 780626 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 792936 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 12310 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 780626 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 792936 # number of overall (read+write) accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.965716 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 0.965716 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.235012 # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.235012 # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.312992 # miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.312992 # miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.235012 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.370696 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.368590 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.235012 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.370696 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.368590 # miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74163.403106 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74163.403106 # average ReadExReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 76978.741791 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 76978.741791 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 83227.780272 # average ReadSharedReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 83227.780272 # average ReadSharedReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76978.741791 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 81140.193521 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 81099.001601 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76978.741791 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 81140.193521 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 81099.001601 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.writebacks::writebacks 66683 # number of writebacks
system.cpu.l2cache.writebacks::total 66683 # number of writebacks
system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 1 # number of CleanEvict MSHR misses
system.cpu.l2cache.CleanEvict_mshr_misses::total 1 # number of CleanEvict MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 66645 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 66645 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 2893 # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::total 2893 # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 222730 # number of ReadSharedReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::total 222730 # number of ReadSharedReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 2893 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 289375 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 292268 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 2893 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 289375 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 292268 # number of overall MSHR misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4276170000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4276170000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 193779500 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 193779500 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 16310023500 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 16310023500 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 193779500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 20586193500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 20779973000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 193779500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 20586193500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 20779973000 # number of overall MSHR miss cycles
system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.965716 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.965716 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.235012 # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.235012 # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.312992 # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.312992 # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.235012 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.370696 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.368590 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.235012 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.370696 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.368590 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64163.403106 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64163.403106 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 66982.198410 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 66982.198410 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 73227.780272 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 73227.780272 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66982.198410 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71140.193521 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 71099.035816 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66982.198410 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71140.193521 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 71099.035816 # average overall mshr miss latency
system.cpu.toL2Bus.snoop_filter.tot_requests 1580033 # Total number of requests made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_requests 787097 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.snoop_filter.tot_snoops 2081 # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2081 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.trans_dist::ReadResp 723924 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackDirty 155172 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackClean 10567 # Transaction distribution
system.cpu.toL2Bus.trans_dist::CleanEvict 881298 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 69011 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 69011 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadCleanReq 12310 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadSharedReq 711615 # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 35186 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2337782 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 2372968 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1464064 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 55623360 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total 57087424 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops 259940 # Total snoops (count)