2012-02-13 12:43:09 +01:00
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# Copyright (c) 2012 ARM Limited
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# All rights reserved.
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#
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# The license below extends only to copyright in the software and shall
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# not be construed as granting a license to any other intellectual
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# property including but not limited to intellectual property relating
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# to a hardware implementation of the functionality of the software
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# licensed hereunder. You may use the software subject to the license
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# terms below provided that you ensure that this notice is replicated
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# unmodified and in its entirety in all distributions of the software,
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# modified or unmodified, in source code or in binary form.
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#
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2008-02-06 05:44:13 +01:00
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# Copyright (c) 2005-2008 The Regents of The University of Michigan
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2011-02-07 07:14:17 +01:00
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# Copyright (c) 2011 Regents of the University of California
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2007-05-28 04:21:17 +02:00
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# All rights reserved.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are
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# met: redistributions of source code must retain the above copyright
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# notice, this list of conditions and the following disclaimer;
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# redistributions in binary form must reproduce the above copyright
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# notice, this list of conditions and the following disclaimer in the
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# documentation and/or other materials provided with the distribution;
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# neither the name of the copyright holders nor the names of its
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# contributors may be used to endorse or promote products derived from
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# this software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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#
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# Authors: Nathan Binkert
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2011-02-07 07:14:17 +01:00
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# Rick Strong
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2012-02-13 12:43:09 +01:00
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# Andreas Hansson
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2007-05-28 04:21:17 +02:00
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2009-09-23 00:24:16 +02:00
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import sys
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from m5.defines import buildEnv
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2006-09-05 02:14:07 +02:00
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from m5.params import *
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from m5.proxy import *
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2009-09-23 00:24:16 +02:00
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Bus: Split the bus into a non-coherent and coherent bus
This patch introduces a class hierarchy of buses, a non-coherent one,
and a coherent one, splitting the existing bus functionality. By doing
so it also enables further specialisation of the two types of buses.
A non-coherent bus connects a number of non-snooping masters and
slaves, and routes the request and response packets based on the
address. The request packets issued by the master connected to a
non-coherent bus could still snoop in caches attached to a coherent
bus, as is the case with the I/O bus and memory bus in most system
configurations. No snoops will, however, reach any master on the
non-coherent bus itself. The non-coherent bus can be used as a
template for modelling PCI, PCIe, and non-coherent AMBA and OCP buses,
and is typically used for the I/O buses.
A coherent bus connects a number of (potentially) snooping masters and
slaves, and routes the request and response packets based on the
address, and also forwards all requests to the snoopers and deals with
the snoop responses. The coherent bus can be used as a template for
modelling QPI, HyperTransport, ACE and coherent OCP buses, and is
typically used for the L1-to-L2 buses and as the main system
interconnect.
The configuration scripts are updated to use a NoncoherentBus for all
peripheral and I/O buses.
A bit of minor tidying up has also been done.
--HG--
rename : src/mem/bus.cc => src/mem/coherent_bus.cc
rename : src/mem/bus.hh => src/mem/coherent_bus.hh
rename : src/mem/bus.cc => src/mem/noncoherent_bus.cc
rename : src/mem/bus.hh => src/mem/noncoherent_bus.hh
2012-05-31 19:30:04 +02:00
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from Bus import CoherentBus
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2007-07-29 05:30:43 +02:00
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from InstTracer import InstTracer
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from ExeTracer import ExeTracer
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2009-09-23 00:24:16 +02:00
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from MemObject import MemObject
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2006-06-10 05:01:31 +02:00
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2007-07-29 05:30:43 +02:00
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default_tracer = ExeTracer()
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2009-09-23 00:24:16 +02:00
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if buildEnv['TARGET_ISA'] == 'alpha':
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2009-04-09 07:21:27 +02:00
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from AlphaTLB import AlphaDTB, AlphaITB
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2011-10-09 09:15:50 +02:00
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from AlphaInterrupts import AlphaInterrupts
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2009-09-23 00:24:16 +02:00
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elif buildEnv['TARGET_ISA'] == 'sparc':
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2009-04-09 07:21:27 +02:00
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from SparcTLB import SparcTLB
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2011-10-09 09:15:50 +02:00
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from SparcInterrupts import SparcInterrupts
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2009-09-23 00:24:16 +02:00
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elif buildEnv['TARGET_ISA'] == 'x86':
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2009-04-09 07:21:27 +02:00
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from X86TLB import X86TLB
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2011-10-09 09:15:50 +02:00
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from X86LocalApic import X86LocalApic
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2009-09-23 00:24:16 +02:00
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elif buildEnv['TARGET_ISA'] == 'mips':
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2009-04-09 07:21:27 +02:00
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from MipsTLB import MipsTLB
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2011-10-09 09:15:50 +02:00
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from MipsInterrupts import MipsInterrupts
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2009-09-23 00:24:16 +02:00
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elif buildEnv['TARGET_ISA'] == 'arm':
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2009-04-22 00:40:25 +02:00
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from ArmTLB import ArmTLB
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2011-10-09 09:15:50 +02:00
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from ArmInterrupts import ArmInterrupts
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2009-10-27 17:24:39 +01:00
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elif buildEnv['TARGET_ISA'] == 'power':
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from PowerTLB import PowerTLB
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2011-10-09 09:15:50 +02:00
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from PowerInterrupts import PowerInterrupts
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2007-05-28 04:21:17 +02:00
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2008-08-11 21:22:16 +02:00
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class BaseCPU(MemObject):
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2005-02-03 03:13:01 +01:00
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type = 'BaseCPU'
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2005-01-15 10:12:25 +01:00
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abstract = True
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2012-09-25 18:49:40 +02:00
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@classmethod
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def export_method_cxx_predecls(cls, code):
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code('#include "cpu/base.hh"')
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@classmethod
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def export_methods(cls, code):
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code('''
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void switchOut();
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void takeOverFrom(BaseCPU *cpu);
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''')
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def takeOverFrom(self, old_cpu):
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self._ccObject.takeOverFrom(old_cpu._ccObject)
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2006-07-13 02:22:07 +02:00
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system = Param.System(Parent.any, "system object")
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2008-11-03 03:56:57 +01:00
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cpu_id = Param.Int(-1, "CPU identifier")
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2008-08-11 21:22:16 +02:00
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numThreads = Param.Unsigned(1, "number of HW thread contexts")
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function_trace = Param.Bool(False, "Enable function trace")
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2012-08-21 11:49:43 +02:00
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function_trace_start = Param.Tick(0, "Tick to start function trace")
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2008-08-11 21:22:16 +02:00
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2009-01-31 01:08:13 +01:00
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checker = Param.BaseCPU(NULL, "checker CPU")
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2006-10-08 19:53:24 +02:00
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2008-12-17 18:51:18 +01:00
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do_checkpoint_insts = Param.Bool(True,
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"enable checkpoint pseudo instructions")
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do_statistics_insts = Param.Bool(True,
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"enable statistics pseudo instructions")
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2011-11-02 10:11:14 +01:00
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profile = Param.Latency('0ns', "trace the kernel stack")
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do_quiesce = Param.Bool(True, "enable quiesce instructions")
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2011-11-18 10:33:28 +01:00
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workload = VectorParam.Process([], "processes to run")
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2005-01-15 10:12:25 +01:00
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2009-09-23 00:24:16 +02:00
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if buildEnv['TARGET_ISA'] == 'sparc':
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2009-04-09 07:21:27 +02:00
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dtb = Param.SparcTLB(SparcTLB(), "Data TLB")
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itb = Param.SparcTLB(SparcTLB(), "Instruction TLB")
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2011-10-09 09:15:50 +02:00
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interrupts = Param.SparcInterrupts(
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2012-03-01 18:37:02 +01:00
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NULL, "Interrupt Controller")
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2009-09-23 00:24:16 +02:00
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elif buildEnv['TARGET_ISA'] == 'alpha':
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2009-04-09 07:21:27 +02:00
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dtb = Param.AlphaTLB(AlphaDTB(), "Data TLB")
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itb = Param.AlphaTLB(AlphaITB(), "Instruction TLB")
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2011-10-09 09:15:50 +02:00
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interrupts = Param.AlphaInterrupts(
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2012-03-01 18:37:02 +01:00
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NULL, "Interrupt Controller")
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2009-09-23 00:24:16 +02:00
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elif buildEnv['TARGET_ISA'] == 'x86':
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2009-04-09 07:21:27 +02:00
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dtb = Param.X86TLB(X86TLB(), "Data TLB")
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itb = Param.X86TLB(X86TLB(), "Instruction TLB")
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2012-03-01 18:37:02 +01:00
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interrupts = Param.X86LocalApic(NULL, "Interrupt Controller")
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2009-09-23 00:24:16 +02:00
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elif buildEnv['TARGET_ISA'] == 'mips':
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2009-04-09 07:21:27 +02:00
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dtb = Param.MipsTLB(MipsTLB(), "Data TLB")
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itb = Param.MipsTLB(MipsTLB(), "Instruction TLB")
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2011-10-09 09:15:50 +02:00
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interrupts = Param.MipsInterrupts(
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2012-03-01 18:37:02 +01:00
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NULL, "Interrupt Controller")
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2009-09-23 00:24:16 +02:00
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elif buildEnv['TARGET_ISA'] == 'arm':
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2009-04-22 00:40:25 +02:00
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dtb = Param.ArmTLB(ArmTLB(), "Data TLB")
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itb = Param.ArmTLB(ArmTLB(), "Instruction TLB")
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2011-10-09 09:15:50 +02:00
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interrupts = Param.ArmInterrupts(
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2012-03-01 18:37:02 +01:00
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NULL, "Interrupt Controller")
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2009-10-27 17:24:39 +01:00
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elif buildEnv['TARGET_ISA'] == 'power':
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UnifiedTLB = Param.Bool(True, "Is this a Unified TLB?")
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dtb = Param.PowerTLB(PowerTLB(), "Data TLB")
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itb = Param.PowerTLB(PowerTLB(), "Instruction TLB")
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2011-10-09 09:15:50 +02:00
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interrupts = Param.PowerInterrupts(
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2012-03-01 18:37:02 +01:00
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NULL, "Interrupt Controller")
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2007-08-27 05:24:18 +02:00
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else:
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print "Don't know what TLB to use for ISA %s" % \
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2009-09-23 00:24:16 +02:00
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buildEnv['TARGET_ISA']
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2007-08-27 05:24:18 +02:00
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sys.exit(1)
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2005-01-15 10:12:25 +01:00
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max_insts_all_threads = Param.Counter(0,
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"terminate when all threads have reached this inst count")
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max_insts_any_thread = Param.Counter(0,
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"terminate when any thread reaches this inst count")
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max_loads_all_threads = Param.Counter(0,
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"terminate when all threads have reached this load count")
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max_loads_any_thread = Param.Counter(0,
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"terminate when any thread reaches this load count")
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2012-08-28 20:30:33 +02:00
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progress_interval = Param.Frequency('0Hz',
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"frequency to print out the progress message")
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2005-01-15 10:12:25 +01:00
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2005-02-03 23:04:54 +01:00
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defer_registration = Param.Bool(False,
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2005-01-15 10:12:25 +01:00
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"defer registration with system (for sampling)")
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Make the notion of a global event tick independent of the actual
CPU cycle ticks. This allows the user to have CPUs of different
frequencies, and also allows frequencies and latencies that are
not evenly divisible by the CPU frequency. For now, the CPU
frequency is still set to the global frequency, but soon, we'll
hopefully make the global frequency fixed at something like 1THz
and set all other frequencies independently.
arch/alpha/ev5.cc:
The cycles counter is based on the current cpu cycle.
cpu/base_cpu.cc:
frequency isn't the cpu parameter anymore, cycleTime is.
cpu/base_cpu.hh:
frequency isn't the cpu parameter anymore, cycleTime is.
create several public functions for getting the cpu frequency
and the numbers of ticks for a given number of cycles, etc.
cpu/memtest/memtest.cc:
cpu/simple_cpu/simple_cpu.cc:
cpu/simple_cpu/simple_cpu.hh:
cpu/trace/trace_cpu.cc:
Now that ticks aren't cpu cycles, fixup code to advance
by the proper number of ticks.
cpu/memtest/memtest.hh:
cpu/trace/trace_cpu.hh:
Provide a function to get the number of ticks for a given
number of cycles.
dev/alpha_console.cc:
Update for changes in the way that frequencies and latencies are
accessed. Move some stuff to init()
dev/alpha_console.hh:
Need a pointer to the system and the cpu to get the frequency
so we can pass the info to the console code.
dev/etherbus.cc:
dev/etherbus.hh:
dev/etherlink.cc:
dev/etherlink.hh:
dev/ethertap.cc:
dev/ide_disk.hh:
dev/ns_gige.cc:
dev/ns_gige.hh:
update for changes in the way bandwidths are passed from
python to C++ to accomidate the new way that ticks works.
dev/ide_disk.cc:
update for changes in the way bandwidths are passed from
python to C++ to accomidate the new way that ticks works.
Add some extra debugging printfs
dev/platform.cc:
dev/sinic.cc:
dev/sinic.hh:
outline the constructor and destructor
dev/platform.hh:
outline the constructor and destructor.
don't keep track of the interrupt frequency. Only provide the
accessor function.
dev/tsunami.cc:
dev/tsunami.hh:
outline the constructor and destructor
Don't set the interrupt frequency here. Get it from the actual device
that does the interrupting.
dev/tsunami_io.cc:
dev/tsunami_io.hh:
Make the interrupt interval a configuration parameter. (And convert
the interval to the new latency/frequency stuff in the python)
kern/linux/linux_system.cc:
update for changes in the way bandwidths are passed from
python to C++ to accomidate the new way that ticks works.
For now, we must get the boot cpu's frequency as a parameter
since allowing the system to have a pointer to the boot cpu would
cause a cycle.
kern/tru64/tru64_system.cc:
For now, we must get the boot cpu's frequency as a parameter
since allowing the system to have a pointer to the boot cpu would
cause a cycle.
python/m5/config.py:
Fix support for cycle_time relative latencies and frequencies.
Add support for getting a NetworkBandwidth or a MemoryBandwidth.
python/m5/objects/BaseCPU.mpy:
All CPUs now have a cycle_time. The default is the global frequency,
but it is now possible to set the global frequency to some large value
(like 1THz) and set each CPU frequency independently.
python/m5/objects/BaseCache.mpy:
python/m5/objects/Ide.mpy:
Make this a Latency parameter
python/m5/objects/BaseSystem.mpy:
We need to pass the boot CPU's frequency to the system
python/m5/objects/Ethernet.mpy:
Update parameter types to use latency and bandwidth types
python/m5/objects/Platform.mpy:
this frequency isn't needed. We get it from the clock interrupt.
python/m5/objects/Tsunami.mpy:
The clock generator should hold the frequency
sim/eventq.hh:
Need to remove this assertion because the writeback event
queue is different from the CPU's event queue which can cause
this assertion to fail.
sim/process.cc:
Fix comment.
sim/system.hh:
Struct member to hold the boot CPU's frequency.
sim/universe.cc:
remove unneeded variable.
--HG--
extra : convert_revision : 51efe4041095234bf458d9b3b0d417f4cae16fdc
2005-04-11 21:32:06 +02:00
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2007-07-29 05:30:43 +02:00
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tracer = Param.InstTracer(default_tracer, "Instruction tracer")
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2012-02-13 12:43:09 +01:00
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icache_port = MasterPort("Instruction Port")
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dcache_port = MasterPort("Data Port")
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2012-01-17 19:55:08 +01:00
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_cached_ports = ['icache_port', 'dcache_port']
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2011-10-16 14:06:38 +02:00
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if buildEnv['TARGET_ISA'] in ['x86', 'arm']:
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2012-01-17 19:55:08 +01:00
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_cached_ports += ["itb.walker.port", "dtb.walker.port"]
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2011-02-04 05:23:00 +01:00
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2012-02-13 12:43:09 +01:00
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_uncached_slave_ports = []
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_uncached_master_ports = []
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2011-10-09 09:15:50 +02:00
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if buildEnv['TARGET_ISA'] == 'x86':
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2012-02-13 12:43:09 +01:00
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_uncached_slave_ports += ["interrupts.pio", "interrupts.int_slave"]
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_uncached_master_ports += ["interrupts.int_master"]
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2011-02-04 05:23:00 +01:00
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2012-03-01 18:37:02 +01:00
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def createInterruptController(self):
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if buildEnv['TARGET_ISA'] == 'sparc':
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self.interrupts = SparcInterrupts()
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elif buildEnv['TARGET_ISA'] == 'alpha':
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self.interrupts = AlphaInterrupts()
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elif buildEnv['TARGET_ISA'] == 'x86':
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_localApic = X86LocalApic(pio_addr=0x2000000000000000)
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self.interrupts = _localApic
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elif buildEnv['TARGET_ISA'] == 'mips':
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self.interrupts = MipsInterrupts()
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elif buildEnv['TARGET_ISA'] == 'arm':
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self.interrupts = ArmInterrupts()
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elif buildEnv['TARGET_ISA'] == 'power':
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self.interrupts = PowerInterrupts()
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else:
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print "Don't know what Interrupt Controller to use for ISA %s" % \
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buildEnv['TARGET_ISA']
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sys.exit(1)
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2011-02-04 05:23:00 +01:00
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def connectCachedPorts(self, bus):
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for p in self._cached_ports:
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2012-02-13 12:43:09 +01:00
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exec('self.%s = bus.slave' % p)
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2006-08-16 18:52:05 +02:00
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2011-02-04 05:23:00 +01:00
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def connectUncachedPorts(self, bus):
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2012-02-13 12:43:09 +01:00
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for p in self._uncached_slave_ports:
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exec('self.%s = bus.master' % p)
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for p in self._uncached_master_ports:
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exec('self.%s = bus.slave' % p)
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2010-06-02 19:58:16 +02:00
|
|
|
|
2011-02-04 05:23:00 +01:00
|
|
|
def connectAllPorts(self, cached_bus, uncached_bus = None):
|
|
|
|
self.connectCachedPorts(cached_bus)
|
|
|
|
if not uncached_bus:
|
|
|
|
uncached_bus = cached_bus
|
|
|
|
self.connectUncachedPorts(uncached_bus)
|
2006-08-16 18:52:05 +02:00
|
|
|
|
2011-02-02 03:28:41 +01:00
|
|
|
def addPrivateSplitL1Caches(self, ic, dc, iwc = None, dwc = None):
|
2006-08-16 18:52:05 +02:00
|
|
|
self.icache = ic
|
|
|
|
self.dcache = dc
|
|
|
|
self.icache_port = ic.cpu_side
|
|
|
|
self.dcache_port = dc.cpu_side
|
2011-02-04 05:23:00 +01:00
|
|
|
self._cached_ports = ['icache.mem_side', 'dcache.mem_side']
|
2012-01-07 11:15:35 +01:00
|
|
|
if buildEnv['TARGET_ISA'] in ['x86', 'arm']:
|
|
|
|
if iwc and dwc:
|
|
|
|
self.itb_walker_cache = iwc
|
|
|
|
self.dtb_walker_cache = dwc
|
|
|
|
self.itb.walker.port = iwc.cpu_side
|
|
|
|
self.dtb.walker.port = dwc.cpu_side
|
|
|
|
self._cached_ports += ["itb_walker_cache.mem_side", \
|
|
|
|
"dtb_walker_cache.mem_side"]
|
|
|
|
else:
|
|
|
|
self._cached_ports += ["itb.walker.port", "dtb.walker.port"]
|
2012-03-09 15:59:27 +01:00
|
|
|
|
2012-02-01 07:40:08 +01:00
|
|
|
# Checker doesn't need its own tlb caches because it does
|
|
|
|
# functional accesses only
|
2012-03-09 15:59:27 +01:00
|
|
|
if self.checker != NULL:
|
2012-02-01 07:40:08 +01:00
|
|
|
self._cached_ports += ["checker.itb.walker.port", \
|
|
|
|
"checker.dtb.walker.port"]
|
2006-08-16 18:52:05 +02:00
|
|
|
|
2011-02-02 03:28:41 +01:00
|
|
|
def addTwoLevelCacheHierarchy(self, ic, dc, l2c, iwc = None, dwc = None):
|
|
|
|
self.addPrivateSplitL1Caches(ic, dc, iwc, dwc)
|
2012-10-15 14:08:08 +02:00
|
|
|
# Override the default bus clock of 1 GHz and uses the CPU
|
|
|
|
# clock for the L1-to-L2 bus, and also set a width of 32 bytes
|
|
|
|
# (256-bits), which is four times that of the default bus.
|
|
|
|
self.toL2Bus = CoherentBus(clock = Parent.clock, width = 32)
|
2011-02-04 05:23:00 +01:00
|
|
|
self.connectCachedPorts(self.toL2Bus)
|
2006-08-16 18:52:05 +02:00
|
|
|
self.l2cache = l2c
|
2012-02-13 12:43:09 +01:00
|
|
|
self.toL2Bus.master = self.l2cache.cpu_side
|
2011-02-04 05:23:00 +01:00
|
|
|
self._cached_ports = ['l2cache.mem_side']
|
2012-03-09 15:59:27 +01:00
|
|
|
|
|
|
|
def addCheckerCpu(self):
|
|
|
|
pass
|